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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5 */
6
7#ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
8#define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H
9
10#include "mtk-pm-domains.h"
11#include <dt-bindings/power/mt8186-power.h>
12
13/*
14 * MT8186 power domain support
15 */
16
17static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = {
18 [MT8186_POWER_DOMAIN_MFG0] = {
19 .name = "mfg0",
20 .sta_mask = BIT(2),
21 .ctl_offs = 0x308,
22 .pwr_sta_offs = 0x16C,
23 .pwr_sta2nd_offs = 0x170,
24 .sram_pdn_bits = BIT(8),
25 .sram_pdn_ack_bits = BIT(12),
26 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
27 },
28 [MT8186_POWER_DOMAIN_MFG1] = {
29 .name = "mfg1",
30 .sta_mask = BIT(3),
31 .ctl_offs = 0x30c,
32 .pwr_sta_offs = 0x16C,
33 .pwr_sta2nd_offs = 0x170,
34 .sram_pdn_bits = BIT(8),
35 .sram_pdn_ack_bits = BIT(12),
36 .bp_infracfg = {
37 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1,
38 MT8186_TOP_AXI_PROT_EN_1_SET,
39 MT8186_TOP_AXI_PROT_EN_1_CLR,
40 MT8186_TOP_AXI_PROT_EN_1_STA),
41 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2,
42 MT8186_TOP_AXI_PROT_EN_SET,
43 MT8186_TOP_AXI_PROT_EN_CLR,
44 MT8186_TOP_AXI_PROT_EN_STA),
45 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3,
46 MT8186_TOP_AXI_PROT_EN_SET,
47 MT8186_TOP_AXI_PROT_EN_CLR,
48 MT8186_TOP_AXI_PROT_EN_STA),
49 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4,
50 MT8186_TOP_AXI_PROT_EN_1_SET,
51 MT8186_TOP_AXI_PROT_EN_1_CLR,
52 MT8186_TOP_AXI_PROT_EN_1_STA),
53 },
54 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
55 },
56 [MT8186_POWER_DOMAIN_MFG2] = {
57 .name = "mfg2",
58 .sta_mask = BIT(4),
59 .ctl_offs = 0x310,
60 .pwr_sta_offs = 0x16C,
61 .pwr_sta2nd_offs = 0x170,
62 .sram_pdn_bits = BIT(8),
63 .sram_pdn_ack_bits = BIT(12),
64 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
65 },
66 [MT8186_POWER_DOMAIN_MFG3] = {
67 .name = "mfg3",
68 .sta_mask = BIT(5),
69 .ctl_offs = 0x314,
70 .pwr_sta_offs = 0x16C,
71 .pwr_sta2nd_offs = 0x170,
72 .sram_pdn_bits = BIT(8),
73 .sram_pdn_ack_bits = BIT(12),
74 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
75 },
76 [MT8186_POWER_DOMAIN_SSUSB] = {
77 .name = "ssusb",
78 .sta_mask = BIT(20),
79 .ctl_offs = 0x9F0,
80 .pwr_sta_offs = 0x16C,
81 .pwr_sta2nd_offs = 0x170,
82 .sram_pdn_bits = BIT(8),
83 .sram_pdn_ack_bits = BIT(12),
84 .caps = MTK_SCPD_ACTIVE_WAKEUP,
85 },
86 [MT8186_POWER_DOMAIN_SSUSB_P1] = {
87 .name = "ssusb_p1",
88 .sta_mask = BIT(19),
89 .ctl_offs = 0x9F4,
90 .pwr_sta_offs = 0x16C,
91 .pwr_sta2nd_offs = 0x170,
92 .sram_pdn_bits = BIT(8),
93 .sram_pdn_ack_bits = BIT(12),
94 .caps = MTK_SCPD_ACTIVE_WAKEUP,
95 },
96 [MT8186_POWER_DOMAIN_DIS] = {
97 .name = "dis",
98 .sta_mask = BIT(21),
99 .ctl_offs = 0x354,
100 .pwr_sta_offs = 0x16C,
101 .pwr_sta2nd_offs = 0x170,
102 .sram_pdn_bits = BIT(8),
103 .sram_pdn_ack_bits = BIT(12),
104 .bp_infracfg = {
105 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1,
106 MT8186_TOP_AXI_PROT_EN_1_SET,
107 MT8186_TOP_AXI_PROT_EN_1_CLR,
108 MT8186_TOP_AXI_PROT_EN_1_STA),
109 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2,
110 MT8186_TOP_AXI_PROT_EN_SET,
111 MT8186_TOP_AXI_PROT_EN_CLR,
112 MT8186_TOP_AXI_PROT_EN_STA),
113 },
114 },
115 [MT8186_POWER_DOMAIN_IMG] = {
116 .name = "img",
117 .sta_mask = BIT(13),
118 .ctl_offs = 0x334,
119 .pwr_sta_offs = 0x16C,
120 .pwr_sta2nd_offs = 0x170,
121 .sram_pdn_bits = BIT(8),
122 .sram_pdn_ack_bits = BIT(12),
123 .bp_infracfg = {
124 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1,
125 MT8186_TOP_AXI_PROT_EN_1_SET,
126 MT8186_TOP_AXI_PROT_EN_1_CLR,
127 MT8186_TOP_AXI_PROT_EN_1_STA),
128 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2,
129 MT8186_TOP_AXI_PROT_EN_1_SET,
130 MT8186_TOP_AXI_PROT_EN_1_CLR,
131 MT8186_TOP_AXI_PROT_EN_1_STA),
132 },
133 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
134 },
135 [MT8186_POWER_DOMAIN_IMG2] = {
136 .name = "img2",
137 .sta_mask = BIT(14),
138 .ctl_offs = 0x338,
139 .pwr_sta_offs = 0x16C,
140 .pwr_sta2nd_offs = 0x170,
141 .sram_pdn_bits = BIT(8),
142 .sram_pdn_ack_bits = BIT(12),
143 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
144 },
145 [MT8186_POWER_DOMAIN_IPE] = {
146 .name = "ipe",
147 .sta_mask = BIT(15),
148 .ctl_offs = 0x33C,
149 .pwr_sta_offs = 0x16C,
150 .pwr_sta2nd_offs = 0x170,
151 .sram_pdn_bits = BIT(8),
152 .sram_pdn_ack_bits = BIT(12),
153 .bp_infracfg = {
154 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1,
155 MT8186_TOP_AXI_PROT_EN_1_SET,
156 MT8186_TOP_AXI_PROT_EN_1_CLR,
157 MT8186_TOP_AXI_PROT_EN_1_STA),
158 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2,
159 MT8186_TOP_AXI_PROT_EN_1_SET,
160 MT8186_TOP_AXI_PROT_EN_1_CLR,
161 MT8186_TOP_AXI_PROT_EN_1_STA),
162 },
163 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
164 },
165 [MT8186_POWER_DOMAIN_CAM] = {
166 .name = "cam",
167 .sta_mask = BIT(23),
168 .ctl_offs = 0x35C,
169 .pwr_sta_offs = 0x16C,
170 .pwr_sta2nd_offs = 0x170,
171 .sram_pdn_bits = BIT(8),
172 .sram_pdn_ack_bits = BIT(12),
173 .bp_infracfg = {
174 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1,
175 MT8186_TOP_AXI_PROT_EN_1_SET,
176 MT8186_TOP_AXI_PROT_EN_1_CLR,
177 MT8186_TOP_AXI_PROT_EN_1_STA),
178 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2,
179 MT8186_TOP_AXI_PROT_EN_1_SET,
180 MT8186_TOP_AXI_PROT_EN_1_CLR,
181 MT8186_TOP_AXI_PROT_EN_1_STA),
182 },
183 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
184 },
185 [MT8186_POWER_DOMAIN_CAM_RAWA] = {
186 .name = "cam_rawa",
187 .sta_mask = BIT(24),
188 .ctl_offs = 0x360,
189 .pwr_sta_offs = 0x16C,
190 .pwr_sta2nd_offs = 0x170,
191 .sram_pdn_bits = BIT(8),
192 .sram_pdn_ack_bits = BIT(12),
193 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
194 },
195 [MT8186_POWER_DOMAIN_CAM_RAWB] = {
196 .name = "cam_rawb",
197 .sta_mask = BIT(25),
198 .ctl_offs = 0x364,
199 .pwr_sta_offs = 0x16C,
200 .pwr_sta2nd_offs = 0x170,
201 .sram_pdn_bits = BIT(8),
202 .sram_pdn_ack_bits = BIT(12),
203 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
204 },
205 [MT8186_POWER_DOMAIN_VENC] = {
206 .name = "venc",
207 .sta_mask = BIT(18),
208 .ctl_offs = 0x348,
209 .pwr_sta_offs = 0x16C,
210 .pwr_sta2nd_offs = 0x170,
211 .sram_pdn_bits = BIT(8),
212 .sram_pdn_ack_bits = BIT(12),
213 .bp_infracfg = {
214 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1,
215 MT8186_TOP_AXI_PROT_EN_1_SET,
216 MT8186_TOP_AXI_PROT_EN_1_CLR,
217 MT8186_TOP_AXI_PROT_EN_1_STA),
218 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2,
219 MT8186_TOP_AXI_PROT_EN_1_SET,
220 MT8186_TOP_AXI_PROT_EN_1_CLR,
221 MT8186_TOP_AXI_PROT_EN_1_STA),
222 },
223 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
224 },
225 [MT8186_POWER_DOMAIN_VDEC] = {
226 .name = "vdec",
227 .sta_mask = BIT(16),
228 .ctl_offs = 0x340,
229 .pwr_sta_offs = 0x16C,
230 .pwr_sta2nd_offs = 0x170,
231 .sram_pdn_bits = BIT(8),
232 .sram_pdn_ack_bits = BIT(12),
233 .bp_infracfg = {
234 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1,
235 MT8186_TOP_AXI_PROT_EN_1_SET,
236 MT8186_TOP_AXI_PROT_EN_1_CLR,
237 MT8186_TOP_AXI_PROT_EN_1_STA),
238 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2,
239 MT8186_TOP_AXI_PROT_EN_1_SET,
240 MT8186_TOP_AXI_PROT_EN_1_CLR,
241 MT8186_TOP_AXI_PROT_EN_1_STA),
242 },
243 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
244 },
245 [MT8186_POWER_DOMAIN_WPE] = {
246 .name = "wpe",
247 .sta_mask = BIT(0),
248 .ctl_offs = 0x3F8,
249 .pwr_sta_offs = 0x16C,
250 .pwr_sta2nd_offs = 0x170,
251 .sram_pdn_bits = BIT(8),
252 .sram_pdn_ack_bits = BIT(12),
253 .bp_infracfg = {
254 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1,
255 MT8186_TOP_AXI_PROT_EN_2_SET,
256 MT8186_TOP_AXI_PROT_EN_2_CLR,
257 MT8186_TOP_AXI_PROT_EN_2_STA),
258 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2,
259 MT8186_TOP_AXI_PROT_EN_2_SET,
260 MT8186_TOP_AXI_PROT_EN_2_CLR,
261 MT8186_TOP_AXI_PROT_EN_2_STA),
262 },
263 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
264 },
265 [MT8186_POWER_DOMAIN_CONN_ON] = {
266 .name = "conn_on",
267 .sta_mask = BIT(1),
268 .ctl_offs = 0x304,
269 .pwr_sta_offs = 0x16C,
270 .pwr_sta2nd_offs = 0x170,
271 .bp_infracfg = {
272 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1,
273 MT8186_TOP_AXI_PROT_EN_1_SET,
274 MT8186_TOP_AXI_PROT_EN_1_CLR,
275 MT8186_TOP_AXI_PROT_EN_1_STA),
276 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2,
277 MT8186_TOP_AXI_PROT_EN_SET,
278 MT8186_TOP_AXI_PROT_EN_CLR,
279 MT8186_TOP_AXI_PROT_EN_STA),
280 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3,
281 MT8186_TOP_AXI_PROT_EN_SET,
282 MT8186_TOP_AXI_PROT_EN_CLR,
283 MT8186_TOP_AXI_PROT_EN_STA),
284 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4,
285 MT8186_TOP_AXI_PROT_EN_SET,
286 MT8186_TOP_AXI_PROT_EN_CLR,
287 MT8186_TOP_AXI_PROT_EN_STA),
288 },
289 .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
290 },
291 [MT8186_POWER_DOMAIN_CSIRX_TOP] = {
292 .name = "csirx_top",
293 .sta_mask = BIT(6),
294 .ctl_offs = 0x318,
295 .pwr_sta_offs = 0x16C,
296 .pwr_sta2nd_offs = 0x170,
297 .sram_pdn_bits = BIT(8),
298 .sram_pdn_ack_bits = BIT(12),
299 .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
300 },
301 [MT8186_POWER_DOMAIN_ADSP_AO] = {
302 .name = "adsp_ao",
303 .sta_mask = BIT(17),
304 .ctl_offs = 0x9FC,
305 .pwr_sta_offs = 0x16C,
306 .pwr_sta2nd_offs = 0x170,
307 },
308 [MT8186_POWER_DOMAIN_ADSP_INFRA] = {
309 .name = "adsp_infra",
310 .sta_mask = BIT(10),
311 .ctl_offs = 0x9F8,
312 .pwr_sta_offs = 0x16C,
313 .pwr_sta2nd_offs = 0x170,
314 },
315 [MT8186_POWER_DOMAIN_ADSP_TOP] = {
316 .name = "adsp_top",
317 .sta_mask = BIT(31),
318 .ctl_offs = 0x3E4,
319 .pwr_sta_offs = 0x16C,
320 .pwr_sta2nd_offs = 0x170,
321 .sram_pdn_bits = BIT(8),
322 .sram_pdn_ack_bits = BIT(12),
323 .bp_infracfg = {
324 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1,
325 MT8186_TOP_AXI_PROT_EN_3_SET,
326 MT8186_TOP_AXI_PROT_EN_3_CLR,
327 MT8186_TOP_AXI_PROT_EN_3_STA),
328 BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2,
329 MT8186_TOP_AXI_PROT_EN_3_SET,
330 MT8186_TOP_AXI_PROT_EN_3_CLR,
331 MT8186_TOP_AXI_PROT_EN_3_STA),
332 },
333 .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
334 },
335};
336
337static const struct scpsys_soc_data mt8186_scpsys_data = {
338 .domains_data = scpsys_domain_data_mt8186,
339 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186),
340};
341
342#endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */