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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASM_IO_H
9#define __ASM_IO_H
10
11#include <linux/types.h>
12#include <linux/pgtable.h>
13
14#include <asm/byteorder.h>
15#include <asm/barrier.h>
16#include <asm/memory.h>
17#include <asm/early_ioremap.h>
18#include <asm/alternative.h>
19#include <asm/cpufeature.h>
20
21/*
22 * Generic IO read/write. These perform native-endian accesses.
23 */
24#define __raw_writeb __raw_writeb
25static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
26{
27 asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
28}
29
30#define __raw_writew __raw_writew
31static inline void __raw_writew(u16 val, volatile void __iomem *addr)
32{
33 asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
34}
35
36#define __raw_writel __raw_writel
37static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
38{
39 asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
40}
41
42#define __raw_writeq __raw_writeq
43static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
44{
45 asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
46}
47
48#define __raw_readb __raw_readb
49static inline u8 __raw_readb(const volatile void __iomem *addr)
50{
51 u8 val;
52 asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
53 "ldarb %w0, [%1]",
54 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
55 : "=r" (val) : "r" (addr));
56 return val;
57}
58
59#define __raw_readw __raw_readw
60static inline u16 __raw_readw(const volatile void __iomem *addr)
61{
62 u16 val;
63
64 asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
65 "ldarh %w0, [%1]",
66 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
67 : "=r" (val) : "r" (addr));
68 return val;
69}
70
71#define __raw_readl __raw_readl
72static __always_inline u32 __raw_readl(const volatile void __iomem *addr)
73{
74 u32 val;
75 asm volatile(ALTERNATIVE("ldr %w0, [%1]",
76 "ldar %w0, [%1]",
77 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
78 : "=r" (val) : "r" (addr));
79 return val;
80}
81
82#define __raw_readq __raw_readq
83static inline u64 __raw_readq(const volatile void __iomem *addr)
84{
85 u64 val;
86 asm volatile(ALTERNATIVE("ldr %0, [%1]",
87 "ldar %0, [%1]",
88 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
89 : "=r" (val) : "r" (addr));
90 return val;
91}
92
93/* IO barriers */
94#define __io_ar(v) \
95({ \
96 unsigned long tmp; \
97 \
98 dma_rmb(); \
99 \
100 /* \
101 * Create a dummy control dependency from the IO read to any \
102 * later instructions. This ensures that a subsequent call to \
103 * udelay() will be ordered due to the ISB in get_cycles(). \
104 */ \
105 asm volatile("eor %0, %1, %1\n" \
106 "cbnz %0, ." \
107 : "=r" (tmp) : "r" ((unsigned long)(v)) \
108 : "memory"); \
109})
110
111#define __io_bw() dma_wmb()
112#define __io_br(v)
113#define __io_aw(v)
114
115/* arm64-specific, don't use in portable drivers */
116#define __iormb(v) __io_ar(v)
117#define __iowmb() __io_bw()
118#define __iomb() dma_mb()
119
120/*
121 * I/O port access primitives.
122 */
123#define arch_has_dev_port() (1)
124#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
125#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
126
127/*
128 * String version of I/O memory access operations.
129 */
130extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
131extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
132extern void __memset_io(volatile void __iomem *, int, size_t);
133
134#define memset_io(c,v,l) __memset_io((c),(v),(l))
135#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
136#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
137
138/*
139 * I/O memory mapping functions.
140 */
141
142bool ioremap_allowed(phys_addr_t phys_addr, size_t size, unsigned long prot);
143#define ioremap_allowed ioremap_allowed
144
145#define _PAGE_IOREMAP PROT_DEVICE_nGnRE
146
147#define ioremap_wc(addr, size) \
148 ioremap_prot((addr), (size), PROT_NORMAL_NC)
149#define ioremap_np(addr, size) \
150 ioremap_prot((addr), (size), PROT_DEVICE_nGnRnE)
151
152/*
153 * io{read,write}{16,32,64}be() macros
154 */
155#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
156#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
157#define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
158
159#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
160#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
161#define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
162
163#include <asm-generic/io.h>
164
165#define ioremap_cache ioremap_cache
166static inline void __iomem *ioremap_cache(phys_addr_t addr, size_t size)
167{
168 if (pfn_is_map_memory(__phys_to_pfn(addr)))
169 return (void __iomem *)__phys_to_virt(addr);
170
171 return ioremap_prot(addr, size, PROT_NORMAL);
172}
173
174/*
175 * More restrictive address range checking than the default implementation
176 * (PHYS_OFFSET and PHYS_MASK taken into account).
177 */
178#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
179extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
180extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
181
182extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
183 unsigned long flags);
184#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
185
186#endif /* __ASM_IO_H */