tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/io.h>
9#include <linux/interrupt.h>
10#include <linux/module.h>
11#include <linux/mod_devicetable.h>
12#include <linux/platform_device.h>
13
14#include "mtk_cec.h"
15#include "mtk_hdmi.h"
16#include "mtk_drm_drv.h"
17
18#define TR_CONFIG 0x00
19#define CLEAR_CEC_IRQ BIT(15)
20
21#define CEC_CKGEN 0x04
22#define CEC_32K_PDN BIT(19)
23#define PDN BIT(16)
24
25#define RX_EVENT 0x54
26#define HDMI_PORD BIT(25)
27#define HDMI_HTPLG BIT(24)
28#define HDMI_PORD_INT_EN BIT(9)
29#define HDMI_HTPLG_INT_EN BIT(8)
30
31#define RX_GEN_WD 0x58
32#define HDMI_PORD_INT_32K_STATUS BIT(26)
33#define RX_RISC_INT_32K_STATUS BIT(25)
34#define HDMI_HTPLG_INT_32K_STATUS BIT(24)
35#define HDMI_PORD_INT_32K_CLR BIT(18)
36#define RX_INT_32K_CLR BIT(17)
37#define HDMI_HTPLG_INT_32K_CLR BIT(16)
38#define HDMI_PORD_INT_32K_STA_MASK BIT(10)
39#define RX_RISC_INT_32K_STA_MASK BIT(9)
40#define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
41#define HDMI_PORD_INT_32K_EN BIT(2)
42#define RX_INT_32K_EN BIT(1)
43#define HDMI_HTPLG_INT_32K_EN BIT(0)
44
45#define NORMAL_INT_CTRL 0x5C
46#define HDMI_HTPLG_INT_STA BIT(0)
47#define HDMI_PORD_INT_STA BIT(1)
48#define HDMI_HTPLG_INT_CLR BIT(16)
49#define HDMI_PORD_INT_CLR BIT(17)
50#define HDMI_FULL_INT_CLR BIT(20)
51
52struct mtk_cec {
53 void __iomem *regs;
54 struct clk *clk;
55 int irq;
56 bool hpd;
57 void (*hpd_event)(bool hpd, struct device *dev);
58 struct device *hdmi_dev;
59 spinlock_t lock;
60};
61
62static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
63 unsigned int bits)
64{
65 void __iomem *reg = cec->regs + offset;
66 u32 tmp;
67
68 tmp = readl(reg);
69 tmp &= ~bits;
70 writel(tmp, reg);
71}
72
73static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
74 unsigned int bits)
75{
76 void __iomem *reg = cec->regs + offset;
77 u32 tmp;
78
79 tmp = readl(reg);
80 tmp |= bits;
81 writel(tmp, reg);
82}
83
84static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
85 unsigned int val, unsigned int mask)
86{
87 u32 tmp = readl(cec->regs + offset) & ~mask;
88
89 tmp |= val & mask;
90 writel(tmp, cec->regs + offset);
91}
92
93void mtk_cec_set_hpd_event(struct device *dev,
94 void (*hpd_event)(bool hpd, struct device *dev),
95 struct device *hdmi_dev)
96{
97 struct mtk_cec *cec = dev_get_drvdata(dev);
98 unsigned long flags;
99
100 spin_lock_irqsave(&cec->lock, flags);
101 cec->hdmi_dev = hdmi_dev;
102 cec->hpd_event = hpd_event;
103 spin_unlock_irqrestore(&cec->lock, flags);
104}
105
106bool mtk_cec_hpd_high(struct device *dev)
107{
108 struct mtk_cec *cec = dev_get_drvdata(dev);
109 unsigned int status;
110
111 status = readl(cec->regs + RX_EVENT);
112
113 return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
114}
115
116static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
117{
118 mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
119 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
120 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
121 mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
122 HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
123 RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
124}
125
126static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
127{
128 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
129}
130
131static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
132{
133 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
134}
135
136static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
137{
138 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
139 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
140 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
141 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
142 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
143 usleep_range(5, 10);
144 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
145 HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
146 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
147 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
148 RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
149}
150
151static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
152{
153 void (*hpd_event)(bool hpd, struct device *dev);
154 struct device *hdmi_dev;
155 unsigned long flags;
156
157 spin_lock_irqsave(&cec->lock, flags);
158 hpd_event = cec->hpd_event;
159 hdmi_dev = cec->hdmi_dev;
160 spin_unlock_irqrestore(&cec->lock, flags);
161
162 if (hpd_event)
163 hpd_event(hpd, hdmi_dev);
164}
165
166static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
167{
168 struct device *dev = arg;
169 struct mtk_cec *cec = dev_get_drvdata(dev);
170 bool hpd;
171
172 mtk_cec_clear_htplg_irq(cec);
173 hpd = mtk_cec_hpd_high(dev);
174
175 if (cec->hpd != hpd) {
176 dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
177 cec->hpd, hpd);
178 cec->hpd = hpd;
179 mtk_cec_hpd_event(cec, hpd);
180 }
181 return IRQ_HANDLED;
182}
183
184static int mtk_cec_probe(struct platform_device *pdev)
185{
186 struct device *dev = &pdev->dev;
187 struct mtk_cec *cec;
188 struct resource *res;
189 int ret;
190
191 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
192 if (!cec)
193 return -ENOMEM;
194
195 platform_set_drvdata(pdev, cec);
196 spin_lock_init(&cec->lock);
197
198 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
199 cec->regs = devm_ioremap_resource(dev, res);
200 if (IS_ERR(cec->regs)) {
201 ret = PTR_ERR(cec->regs);
202 dev_err(dev, "Failed to ioremap cec: %d\n", ret);
203 return ret;
204 }
205
206 cec->clk = devm_clk_get(dev, NULL);
207 if (IS_ERR(cec->clk)) {
208 ret = PTR_ERR(cec->clk);
209 dev_err(dev, "Failed to get cec clock: %d\n", ret);
210 return ret;
211 }
212
213 cec->irq = platform_get_irq(pdev, 0);
214 if (cec->irq < 0)
215 return cec->irq;
216
217 ret = devm_request_threaded_irq(dev, cec->irq, NULL,
218 mtk_cec_htplg_isr_thread,
219 IRQF_SHARED | IRQF_TRIGGER_LOW |
220 IRQF_ONESHOT, "hdmi hpd", dev);
221 if (ret) {
222 dev_err(dev, "Failed to register cec irq: %d\n", ret);
223 return ret;
224 }
225
226 ret = clk_prepare_enable(cec->clk);
227 if (ret) {
228 dev_err(dev, "Failed to enable cec clock: %d\n", ret);
229 return ret;
230 }
231
232 mtk_cec_htplg_irq_init(cec);
233 mtk_cec_htplg_irq_enable(cec);
234
235 return 0;
236}
237
238static int mtk_cec_remove(struct platform_device *pdev)
239{
240 struct mtk_cec *cec = platform_get_drvdata(pdev);
241
242 mtk_cec_htplg_irq_disable(cec);
243 clk_disable_unprepare(cec->clk);
244 return 0;
245}
246
247static const struct of_device_id mtk_cec_of_ids[] = {
248 { .compatible = "mediatek,mt8173-cec", },
249 {}
250};
251MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
252
253struct platform_driver mtk_cec_driver = {
254 .probe = mtk_cec_probe,
255 .remove = mtk_cec_remove,
256 .driver = {
257 .name = "mediatek-cec",
258 .of_match_table = mtk_cec_of_ids,
259 },
260};