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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/traps.h
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 */
7#ifndef __ASM_TRAP_H
8#define __ASM_TRAP_H
9
10#include <linux/list.h>
11#include <asm/esr.h>
12#include <asm/sections.h>
13
14struct pt_regs;
15
16#ifdef CONFIG_ARMV8_DEPRECATED
17bool try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn);
18#else
19static inline bool
20try_emulate_armv8_deprecated(struct pt_regs *regs, u32 insn)
21{
22 return false;
23}
24#endif /* CONFIG_ARMV8_DEPRECATED */
25
26void force_signal_inject(int signal, int code, unsigned long address, unsigned long err);
27void arm64_notify_segfault(unsigned long addr);
28void arm64_force_sig_fault(int signo, int code, unsigned long far, const char *str);
29void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, const char *str);
30void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, const char *str);
31
32/*
33 * Move regs->pc to next instruction and do necessary setup before it
34 * is executed.
35 */
36void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size);
37
38static inline int __in_irqentry_text(unsigned long ptr)
39{
40 return ptr >= (unsigned long)&__irqentry_text_start &&
41 ptr < (unsigned long)&__irqentry_text_end;
42}
43
44static inline int in_entry_text(unsigned long ptr)
45{
46 return ptr >= (unsigned long)&__entry_text_start &&
47 ptr < (unsigned long)&__entry_text_end;
48}
49
50/*
51 * CPUs with the RAS extensions have an Implementation-Defined-Syndrome bit
52 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
53 * have a ISS-Valid bit in the same position.
54 * If this bit is set, we know its not a RAS SError.
55 * If its clear, we need to know if the CPU supports RAS. Uncategorized RAS
56 * errors share the same encoding as an all-zeros encoding from a CPU that
57 * doesn't support RAS.
58 */
59static inline bool arm64_is_ras_serror(unsigned long esr)
60{
61 WARN_ON(preemptible());
62
63 if (esr & ESR_ELx_IDS)
64 return false;
65
66 if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN))
67 return true;
68 else
69 return false;
70}
71
72/*
73 * Return the AET bits from a RAS SError's ESR.
74 *
75 * It is implementation defined whether Uncategorized errors are containable.
76 * We treat them as Uncontainable.
77 * Non-RAS SError's are reported as Uncontained/Uncategorized.
78 */
79static inline unsigned long arm64_ras_serror_get_severity(unsigned long esr)
80{
81 unsigned long aet = esr & ESR_ELx_AET;
82
83 if (!arm64_is_ras_serror(esr)) {
84 /* Not a RAS error, we can't interpret the ESR. */
85 return ESR_ELx_AET_UC;
86 }
87
88 /*
89 * AET is RES0 if 'the value returned in the DFSC field is not
90 * [ESR_ELx_FSC_SERROR]'
91 */
92 if ((esr & ESR_ELx_FSC) != ESR_ELx_FSC_SERROR) {
93 /* No severity information : Uncategorized */
94 return ESR_ELx_AET_UC;
95 }
96
97 return aet;
98}
99
100bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned long esr);
101void __noreturn arm64_serror_panic(struct pt_regs *regs, unsigned long esr);
102#endif