tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0+
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP TJA11xx PHY
8
9maintainers:
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
13
14description:
15 Bindings for NXP TJA11xx automotive PHYs
16
17allOf:
18 - $ref: ethernet-phy.yaml#
19
20patternProperties:
21 "^ethernet-phy@[0-9a-f]+$":
22 type: object
23 description: |
24 Some packages have multiple PHYs. Secondary PHY should be defines as
25 subnode of the first (parent) PHY.
26
27 properties:
28 reg:
29 minimum: 0
30 maximum: 31
31 description:
32 The ID number for the child PHY. Should be +1 of parent PHY.
33
34 nxp,rmii-refclk-in:
35 type: boolean
36 description: |
37 The REF_CLK is provided for both transmitted and received data
38 in RMII mode. This clock signal is provided by the PHY and is
39 typically derived from an external 25MHz crystal. Alternatively,
40 a 50MHz clock signal generated by an external oscillator can be
41 connected to pin REF_CLK. A third option is to connect a 25MHz
42 clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
43 as input or output according to the actual circuit connection.
44 If present, indicates that the REF_CLK will be configured as
45 interface reference clock input when RMII mode enabled.
46 If not present, the REF_CLK will be configured as interface
47 reference clock output when RMII mode enabled.
48 Only supported on TJA1100 and TJA1101.
49
50 required:
51 - reg
52
53unevaluatedProperties: false
54
55examples:
56 - |
57 mdio {
58 #address-cells = <1>;
59 #size-cells = <0>;
60
61 tja1101_phy0: ethernet-phy@4 {
62 reg = <0x4>;
63 nxp,rmii-refclk-in;
64 };
65 };
66 - |
67 mdio {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 tja1102_phy0: ethernet-phy@4 {
72 reg = <0x4>;
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 tja1102_phy1: ethernet-phy@5 {
77 reg = <0x5>;
78 };
79 };
80 };