tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on SC7280
8
9maintainers:
10 - Taniya Das <tdas@codeaurora.org>
11
12description: |
13 Qualcomm global clock control module provides the clocks, resets and power
14 domains on SC7280.
15
16 See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
17
18properties:
19 compatible:
20 const: qcom,gcc-sc7280
21
22 clocks:
23 items:
24 - description: Board XO source
25 - description: Board active XO source
26 - description: Sleep clock source
27 - description: PCIE-0 pipe clock source
28 - description: PCIE-1 pipe clock source
29 - description: USF phy rx symbol 0 clock source
30 - description: USF phy rx symbol 1 clock source
31 - description: USF phy tx symbol 0 clock source
32 - description: USB30 phy wrapper pipe clock source
33
34 clock-names:
35 items:
36 - const: bi_tcxo
37 - const: bi_tcxo_ao
38 - const: sleep_clk
39 - const: pcie_0_pipe_clk
40 - const: pcie_1_pipe_clk
41 - const: ufs_phy_rx_symbol_0_clk
42 - const: ufs_phy_rx_symbol_1_clk
43 - const: ufs_phy_tx_symbol_0_clk
44 - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
45
46required:
47 - compatible
48 - clocks
49 - clock-names
50
51allOf:
52 - $ref: qcom,gcc.yaml#
53
54unevaluatedProperties: false
55
56examples:
57 - |
58 #include <dt-bindings/clock/qcom,rpmh.h>
59 clock-controller@100000 {
60 compatible = "qcom,gcc-sc7280";
61 reg = <0x00100000 0x1f0000>;
62 clocks = <&rpmhcc RPMH_CXO_CLK>,
63 <&rpmhcc RPMH_CXO_CLK_A>,
64 <&sleep_clk>,
65 <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
66 <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
67 <&ufs_phy_tx_symbol_0_clk>,
68 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
69
70 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
71 "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
72 "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
73 "usb3_phy_wrapper_gcc_usb30_pipe_clk";
74 #clock-cells = <1>;
75 #reset-cells = <1>;
76 #power-domain-cells = <1>;
77 };
78...