tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / drivers / pinctrl / qcom / pinctrl-qdu1000.c
at v6.3-rc2 1274 lines 38 kB view raw
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10#include <linux/pinctrl/pinctrl.h> 11 12#include "pinctrl-msm.h" 13 14#define FUNCTION(fname) \ 15 [msm_mux_##fname] = { \ 16 .name = #fname, \ 17 .groups = fname##_groups, \ 18 .ngroups = ARRAY_SIZE(fname##_groups), \ 19 } 20 21#define REG_BASE 0x100000 22#define REG_SIZE 0x1000 23#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 24 { \ 25 .name = "gpio" #id, \ 26 .pins = gpio##id##_pins, \ 27 .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ 28 .funcs = (int[]){ \ 29 msm_mux_gpio, /* gpio mode */ \ 30 msm_mux_##f1, \ 31 msm_mux_##f2, \ 32 msm_mux_##f3, \ 33 msm_mux_##f4, \ 34 msm_mux_##f5, \ 35 msm_mux_##f6, \ 36 msm_mux_##f7, \ 37 msm_mux_##f8, \ 38 msm_mux_##f9 \ 39 }, \ 40 .nfuncs = 10, \ 41 .ctl_reg = REG_BASE + REG_SIZE * id, \ 42 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \ 43 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 44 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \ 45 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \ 46 .mux_bit = 2, \ 47 .pull_bit = 0, \ 48 .drv_bit = 6, \ 49 .oe_bit = 9, \ 50 .in_bit = 0, \ 51 .out_bit = 1, \ 52 .intr_enable_bit = 0, \ 53 .intr_status_bit = 0, \ 54 .intr_target_bit = 5, \ 55 .intr_target_kpss_val = 3, \ 56 .intr_raw_status_bit = 4, \ 57 .intr_polarity_bit = 1, \ 58 .intr_detection_bit = 2, \ 59 .intr_detection_width = 2, \ 60 } 61 62#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 63 { \ 64 .name = #pg_name, \ 65 .pins = pg_name##_pins, \ 66 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 67 .ctl_reg = REG_BASE + ctl, \ 68 .io_reg = 0, \ 69 .intr_cfg_reg = 0, \ 70 .intr_status_reg = 0, \ 71 .intr_target_reg = 0, \ 72 .mux_bit = -1, \ 73 .pull_bit = pull, \ 74 .drv_bit = drv, \ 75 .oe_bit = -1, \ 76 .in_bit = -1, \ 77 .out_bit = -1, \ 78 .intr_enable_bit = -1, \ 79 .intr_status_bit = -1, \ 80 .intr_target_bit = -1, \ 81 .intr_raw_status_bit = -1, \ 82 .intr_polarity_bit = -1, \ 83 .intr_detection_bit = -1, \ 84 .intr_detection_width = -1, \ 85 } 86 87#define UFS_RESET(pg_name, offset) \ 88 { \ 89 .name = #pg_name, \ 90 .pins = pg_name##_pins, \ 91 .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ 92 .ctl_reg = offset, \ 93 .io_reg = offset + 0x4, \ 94 .intr_cfg_reg = 0, \ 95 .intr_status_reg = 0, \ 96 .intr_target_reg = 0, \ 97 .mux_bit = -1, \ 98 .pull_bit = 3, \ 99 .drv_bit = 0, \ 100 .oe_bit = -1, \ 101 .in_bit = -1, \ 102 .out_bit = 0, \ 103 .intr_enable_bit = -1, \ 104 .intr_status_bit = -1, \ 105 .intr_target_bit = -1, \ 106 .intr_raw_status_bit = -1, \ 107 .intr_polarity_bit = -1, \ 108 .intr_detection_bit = -1, \ 109 .intr_detection_width = -1, \ 110 } 111 112#define QUP_I3C(qup_mode, qup_offset) \ 113 { \ 114 .mode = qup_mode, \ 115 .offset = qup_offset, \ 116 } 117 118static const struct pinctrl_pin_desc qdu1000_pins[] = { 119 PINCTRL_PIN(0, "GPIO_0"), 120 PINCTRL_PIN(1, "GPIO_1"), 121 PINCTRL_PIN(2, "GPIO_2"), 122 PINCTRL_PIN(3, "GPIO_3"), 123 PINCTRL_PIN(4, "GPIO_4"), 124 PINCTRL_PIN(5, "GPIO_5"), 125 PINCTRL_PIN(6, "GPIO_6"), 126 PINCTRL_PIN(7, "GPIO_7"), 127 PINCTRL_PIN(8, "GPIO_8"), 128 PINCTRL_PIN(9, "GPIO_9"), 129 PINCTRL_PIN(10, "GPIO_10"), 130 PINCTRL_PIN(11, "GPIO_11"), 131 PINCTRL_PIN(12, "GPIO_12"), 132 PINCTRL_PIN(13, "GPIO_13"), 133 PINCTRL_PIN(14, "GPIO_14"), 134 PINCTRL_PIN(15, "GPIO_15"), 135 PINCTRL_PIN(16, "GPIO_16"), 136 PINCTRL_PIN(17, "GPIO_17"), 137 PINCTRL_PIN(18, "GPIO_18"), 138 PINCTRL_PIN(19, "GPIO_19"), 139 PINCTRL_PIN(20, "GPIO_20"), 140 PINCTRL_PIN(21, "GPIO_21"), 141 PINCTRL_PIN(22, "GPIO_22"), 142 PINCTRL_PIN(23, "GPIO_23"), 143 PINCTRL_PIN(24, "GPIO_24"), 144 PINCTRL_PIN(25, "GPIO_25"), 145 PINCTRL_PIN(26, "GPIO_26"), 146 PINCTRL_PIN(27, "GPIO_27"), 147 PINCTRL_PIN(28, "GPIO_28"), 148 PINCTRL_PIN(29, "GPIO_29"), 149 PINCTRL_PIN(30, "GPIO_30"), 150 PINCTRL_PIN(31, "GPIO_31"), 151 PINCTRL_PIN(32, "GPIO_32"), 152 PINCTRL_PIN(33, "GPIO_33"), 153 PINCTRL_PIN(34, "GPIO_34"), 154 PINCTRL_PIN(35, "GPIO_35"), 155 PINCTRL_PIN(36, "GPIO_36"), 156 PINCTRL_PIN(37, "GPIO_37"), 157 PINCTRL_PIN(38, "GPIO_38"), 158 PINCTRL_PIN(39, "GPIO_39"), 159 PINCTRL_PIN(40, "GPIO_40"), 160 PINCTRL_PIN(41, "GPIO_41"), 161 PINCTRL_PIN(42, "GPIO_42"), 162 PINCTRL_PIN(43, "GPIO_43"), 163 PINCTRL_PIN(44, "GPIO_44"), 164 PINCTRL_PIN(45, "GPIO_45"), 165 PINCTRL_PIN(46, "GPIO_46"), 166 PINCTRL_PIN(47, "GPIO_47"), 167 PINCTRL_PIN(48, "GPIO_48"), 168 PINCTRL_PIN(49, "GPIO_49"), 169 PINCTRL_PIN(50, "GPIO_50"), 170 PINCTRL_PIN(51, "GPIO_51"), 171 PINCTRL_PIN(52, "GPIO_52"), 172 PINCTRL_PIN(53, "GPIO_53"), 173 PINCTRL_PIN(54, "GPIO_54"), 174 PINCTRL_PIN(55, "GPIO_55"), 175 PINCTRL_PIN(56, "GPIO_56"), 176 PINCTRL_PIN(57, "GPIO_57"), 177 PINCTRL_PIN(58, "GPIO_58"), 178 PINCTRL_PIN(59, "GPIO_59"), 179 PINCTRL_PIN(60, "GPIO_60"), 180 PINCTRL_PIN(61, "GPIO_61"), 181 PINCTRL_PIN(62, "GPIO_62"), 182 PINCTRL_PIN(63, "GPIO_63"), 183 PINCTRL_PIN(64, "GPIO_64"), 184 PINCTRL_PIN(65, "GPIO_65"), 185 PINCTRL_PIN(66, "GPIO_66"), 186 PINCTRL_PIN(67, "GPIO_67"), 187 PINCTRL_PIN(68, "GPIO_68"), 188 PINCTRL_PIN(69, "GPIO_69"), 189 PINCTRL_PIN(70, "GPIO_70"), 190 PINCTRL_PIN(71, "GPIO_71"), 191 PINCTRL_PIN(72, "GPIO_72"), 192 PINCTRL_PIN(73, "GPIO_73"), 193 PINCTRL_PIN(74, "GPIO_74"), 194 PINCTRL_PIN(75, "GPIO_75"), 195 PINCTRL_PIN(76, "GPIO_76"), 196 PINCTRL_PIN(77, "GPIO_77"), 197 PINCTRL_PIN(78, "GPIO_78"), 198 PINCTRL_PIN(79, "GPIO_79"), 199 PINCTRL_PIN(80, "GPIO_80"), 200 PINCTRL_PIN(81, "GPIO_81"), 201 PINCTRL_PIN(82, "GPIO_82"), 202 PINCTRL_PIN(83, "GPIO_83"), 203 PINCTRL_PIN(84, "GPIO_84"), 204 PINCTRL_PIN(85, "GPIO_85"), 205 PINCTRL_PIN(86, "GPIO_86"), 206 PINCTRL_PIN(87, "GPIO_87"), 207 PINCTRL_PIN(88, "GPIO_88"), 208 PINCTRL_PIN(89, "GPIO_89"), 209 PINCTRL_PIN(90, "GPIO_90"), 210 PINCTRL_PIN(91, "GPIO_91"), 211 PINCTRL_PIN(92, "GPIO_92"), 212 PINCTRL_PIN(93, "GPIO_93"), 213 PINCTRL_PIN(94, "GPIO_94"), 214 PINCTRL_PIN(95, "GPIO_95"), 215 PINCTRL_PIN(96, "GPIO_96"), 216 PINCTRL_PIN(97, "GPIO_97"), 217 PINCTRL_PIN(98, "GPIO_98"), 218 PINCTRL_PIN(99, "GPIO_99"), 219 PINCTRL_PIN(100, "GPIO_100"), 220 PINCTRL_PIN(101, "GPIO_101"), 221 PINCTRL_PIN(102, "GPIO_102"), 222 PINCTRL_PIN(103, "GPIO_103"), 223 PINCTRL_PIN(104, "GPIO_104"), 224 PINCTRL_PIN(105, "GPIO_105"), 225 PINCTRL_PIN(106, "GPIO_106"), 226 PINCTRL_PIN(107, "GPIO_107"), 227 PINCTRL_PIN(108, "GPIO_108"), 228 PINCTRL_PIN(109, "GPIO_109"), 229 PINCTRL_PIN(110, "GPIO_110"), 230 PINCTRL_PIN(111, "GPIO_111"), 231 PINCTRL_PIN(112, "GPIO_112"), 232 PINCTRL_PIN(113, "GPIO_113"), 233 PINCTRL_PIN(114, "GPIO_114"), 234 PINCTRL_PIN(115, "GPIO_115"), 235 PINCTRL_PIN(116, "GPIO_116"), 236 PINCTRL_PIN(117, "GPIO_117"), 237 PINCTRL_PIN(118, "GPIO_118"), 238 PINCTRL_PIN(119, "GPIO_119"), 239 PINCTRL_PIN(120, "GPIO_120"), 240 PINCTRL_PIN(121, "GPIO_121"), 241 PINCTRL_PIN(122, "GPIO_122"), 242 PINCTRL_PIN(123, "GPIO_123"), 243 PINCTRL_PIN(124, "GPIO_124"), 244 PINCTRL_PIN(125, "GPIO_125"), 245 PINCTRL_PIN(126, "GPIO_126"), 246 PINCTRL_PIN(127, "GPIO_127"), 247 PINCTRL_PIN(128, "GPIO_128"), 248 PINCTRL_PIN(129, "GPIO_129"), 249 PINCTRL_PIN(130, "GPIO_130"), 250 PINCTRL_PIN(131, "GPIO_131"), 251 PINCTRL_PIN(132, "GPIO_132"), 252 PINCTRL_PIN(133, "GPIO_133"), 253 PINCTRL_PIN(134, "GPIO_134"), 254 PINCTRL_PIN(135, "GPIO_135"), 255 PINCTRL_PIN(136, "GPIO_136"), 256 PINCTRL_PIN(137, "GPIO_137"), 257 PINCTRL_PIN(138, "GPIO_138"), 258 PINCTRL_PIN(139, "GPIO_139"), 259 PINCTRL_PIN(140, "GPIO_140"), 260 PINCTRL_PIN(141, "GPIO_141"), 261 PINCTRL_PIN(142, "GPIO_142"), 262 PINCTRL_PIN(143, "GPIO_143"), 263 PINCTRL_PIN(144, "GPIO_144"), 264 PINCTRL_PIN(145, "GPIO_145"), 265 PINCTRL_PIN(146, "GPIO_146"), 266 PINCTRL_PIN(147, "GPIO_147"), 267 PINCTRL_PIN(148, "GPIO_148"), 268 PINCTRL_PIN(149, "GPIO_149"), 269 PINCTRL_PIN(150, "GPIO_150"), 270 PINCTRL_PIN(151, "SDC1_RCLK"), 271 PINCTRL_PIN(152, "SDC1_CLK"), 272 PINCTRL_PIN(153, "SDC1_CMD"), 273 PINCTRL_PIN(154, "SDC1_DATA"), 274}; 275 276#define DECLARE_MSM_GPIO_PINS(pin) \ 277 static const unsigned int gpio##pin##_pins[] = { pin } 278DECLARE_MSM_GPIO_PINS(0); 279DECLARE_MSM_GPIO_PINS(1); 280DECLARE_MSM_GPIO_PINS(2); 281DECLARE_MSM_GPIO_PINS(3); 282DECLARE_MSM_GPIO_PINS(4); 283DECLARE_MSM_GPIO_PINS(5); 284DECLARE_MSM_GPIO_PINS(6); 285DECLARE_MSM_GPIO_PINS(7); 286DECLARE_MSM_GPIO_PINS(8); 287DECLARE_MSM_GPIO_PINS(9); 288DECLARE_MSM_GPIO_PINS(10); 289DECLARE_MSM_GPIO_PINS(11); 290DECLARE_MSM_GPIO_PINS(12); 291DECLARE_MSM_GPIO_PINS(13); 292DECLARE_MSM_GPIO_PINS(14); 293DECLARE_MSM_GPIO_PINS(15); 294DECLARE_MSM_GPIO_PINS(16); 295DECLARE_MSM_GPIO_PINS(17); 296DECLARE_MSM_GPIO_PINS(18); 297DECLARE_MSM_GPIO_PINS(19); 298DECLARE_MSM_GPIO_PINS(20); 299DECLARE_MSM_GPIO_PINS(21); 300DECLARE_MSM_GPIO_PINS(22); 301DECLARE_MSM_GPIO_PINS(23); 302DECLARE_MSM_GPIO_PINS(24); 303DECLARE_MSM_GPIO_PINS(25); 304DECLARE_MSM_GPIO_PINS(26); 305DECLARE_MSM_GPIO_PINS(27); 306DECLARE_MSM_GPIO_PINS(28); 307DECLARE_MSM_GPIO_PINS(29); 308DECLARE_MSM_GPIO_PINS(30); 309DECLARE_MSM_GPIO_PINS(31); 310DECLARE_MSM_GPIO_PINS(32); 311DECLARE_MSM_GPIO_PINS(33); 312DECLARE_MSM_GPIO_PINS(34); 313DECLARE_MSM_GPIO_PINS(35); 314DECLARE_MSM_GPIO_PINS(36); 315DECLARE_MSM_GPIO_PINS(37); 316DECLARE_MSM_GPIO_PINS(38); 317DECLARE_MSM_GPIO_PINS(39); 318DECLARE_MSM_GPIO_PINS(40); 319DECLARE_MSM_GPIO_PINS(41); 320DECLARE_MSM_GPIO_PINS(42); 321DECLARE_MSM_GPIO_PINS(43); 322DECLARE_MSM_GPIO_PINS(44); 323DECLARE_MSM_GPIO_PINS(45); 324DECLARE_MSM_GPIO_PINS(46); 325DECLARE_MSM_GPIO_PINS(47); 326DECLARE_MSM_GPIO_PINS(48); 327DECLARE_MSM_GPIO_PINS(49); 328DECLARE_MSM_GPIO_PINS(50); 329DECLARE_MSM_GPIO_PINS(51); 330DECLARE_MSM_GPIO_PINS(52); 331DECLARE_MSM_GPIO_PINS(53); 332DECLARE_MSM_GPIO_PINS(54); 333DECLARE_MSM_GPIO_PINS(55); 334DECLARE_MSM_GPIO_PINS(56); 335DECLARE_MSM_GPIO_PINS(57); 336DECLARE_MSM_GPIO_PINS(58); 337DECLARE_MSM_GPIO_PINS(59); 338DECLARE_MSM_GPIO_PINS(60); 339DECLARE_MSM_GPIO_PINS(61); 340DECLARE_MSM_GPIO_PINS(62); 341DECLARE_MSM_GPIO_PINS(63); 342DECLARE_MSM_GPIO_PINS(64); 343DECLARE_MSM_GPIO_PINS(65); 344DECLARE_MSM_GPIO_PINS(66); 345DECLARE_MSM_GPIO_PINS(67); 346DECLARE_MSM_GPIO_PINS(68); 347DECLARE_MSM_GPIO_PINS(69); 348DECLARE_MSM_GPIO_PINS(70); 349DECLARE_MSM_GPIO_PINS(71); 350DECLARE_MSM_GPIO_PINS(72); 351DECLARE_MSM_GPIO_PINS(73); 352DECLARE_MSM_GPIO_PINS(74); 353DECLARE_MSM_GPIO_PINS(75); 354DECLARE_MSM_GPIO_PINS(76); 355DECLARE_MSM_GPIO_PINS(77); 356DECLARE_MSM_GPIO_PINS(78); 357DECLARE_MSM_GPIO_PINS(79); 358DECLARE_MSM_GPIO_PINS(80); 359DECLARE_MSM_GPIO_PINS(81); 360DECLARE_MSM_GPIO_PINS(82); 361DECLARE_MSM_GPIO_PINS(83); 362DECLARE_MSM_GPIO_PINS(84); 363DECLARE_MSM_GPIO_PINS(85); 364DECLARE_MSM_GPIO_PINS(86); 365DECLARE_MSM_GPIO_PINS(87); 366DECLARE_MSM_GPIO_PINS(88); 367DECLARE_MSM_GPIO_PINS(89); 368DECLARE_MSM_GPIO_PINS(90); 369DECLARE_MSM_GPIO_PINS(91); 370DECLARE_MSM_GPIO_PINS(92); 371DECLARE_MSM_GPIO_PINS(93); 372DECLARE_MSM_GPIO_PINS(94); 373DECLARE_MSM_GPIO_PINS(95); 374DECLARE_MSM_GPIO_PINS(96); 375DECLARE_MSM_GPIO_PINS(97); 376DECLARE_MSM_GPIO_PINS(98); 377DECLARE_MSM_GPIO_PINS(99); 378DECLARE_MSM_GPIO_PINS(100); 379DECLARE_MSM_GPIO_PINS(101); 380DECLARE_MSM_GPIO_PINS(102); 381DECLARE_MSM_GPIO_PINS(103); 382DECLARE_MSM_GPIO_PINS(104); 383DECLARE_MSM_GPIO_PINS(105); 384DECLARE_MSM_GPIO_PINS(106); 385DECLARE_MSM_GPIO_PINS(107); 386DECLARE_MSM_GPIO_PINS(108); 387DECLARE_MSM_GPIO_PINS(109); 388DECLARE_MSM_GPIO_PINS(110); 389DECLARE_MSM_GPIO_PINS(111); 390DECLARE_MSM_GPIO_PINS(112); 391DECLARE_MSM_GPIO_PINS(113); 392DECLARE_MSM_GPIO_PINS(114); 393DECLARE_MSM_GPIO_PINS(115); 394DECLARE_MSM_GPIO_PINS(116); 395DECLARE_MSM_GPIO_PINS(117); 396DECLARE_MSM_GPIO_PINS(118); 397DECLARE_MSM_GPIO_PINS(119); 398DECLARE_MSM_GPIO_PINS(120); 399DECLARE_MSM_GPIO_PINS(121); 400DECLARE_MSM_GPIO_PINS(122); 401DECLARE_MSM_GPIO_PINS(123); 402DECLARE_MSM_GPIO_PINS(124); 403DECLARE_MSM_GPIO_PINS(125); 404DECLARE_MSM_GPIO_PINS(126); 405DECLARE_MSM_GPIO_PINS(127); 406DECLARE_MSM_GPIO_PINS(128); 407DECLARE_MSM_GPIO_PINS(129); 408DECLARE_MSM_GPIO_PINS(130); 409DECLARE_MSM_GPIO_PINS(131); 410DECLARE_MSM_GPIO_PINS(132); 411DECLARE_MSM_GPIO_PINS(133); 412DECLARE_MSM_GPIO_PINS(134); 413DECLARE_MSM_GPIO_PINS(135); 414DECLARE_MSM_GPIO_PINS(136); 415DECLARE_MSM_GPIO_PINS(137); 416DECLARE_MSM_GPIO_PINS(138); 417DECLARE_MSM_GPIO_PINS(139); 418DECLARE_MSM_GPIO_PINS(140); 419DECLARE_MSM_GPIO_PINS(141); 420DECLARE_MSM_GPIO_PINS(142); 421DECLARE_MSM_GPIO_PINS(143); 422DECLARE_MSM_GPIO_PINS(144); 423DECLARE_MSM_GPIO_PINS(145); 424DECLARE_MSM_GPIO_PINS(146); 425DECLARE_MSM_GPIO_PINS(147); 426DECLARE_MSM_GPIO_PINS(148); 427DECLARE_MSM_GPIO_PINS(149); 428DECLARE_MSM_GPIO_PINS(150); 429 430static const unsigned int sdc1_rclk_pins[] = { 151 }; 431static const unsigned int sdc1_clk_pins[] = { 152 }; 432static const unsigned int sdc1_cmd_pins[] = { 153 }; 433static const unsigned int sdc1_data_pins[] = { 154 }; 434 435enum qdu1000_functions { 436 msm_mux_gpio, 437 msm_mux_cmo_pri, 438 msm_mux_si5518_int, 439 msm_mux_atest_char, 440 msm_mux_atest_usb, 441 msm_mux_char_exec, 442 msm_mux_cmu_rng, 443 msm_mux_dbg_out_clk, 444 msm_mux_ddr_bist, 445 msm_mux_ddr_pxi0, 446 msm_mux_ddr_pxi1, 447 msm_mux_ddr_pxi2, 448 msm_mux_ddr_pxi3, 449 msm_mux_ddr_pxi4, 450 msm_mux_ddr_pxi5, 451 msm_mux_ddr_pxi6, 452 msm_mux_ddr_pxi7, 453 msm_mux_eth012_int_n, 454 msm_mux_eth345_int_n, 455 msm_mux_eth6_int_n, 456 msm_mux_gcc_gp1, 457 msm_mux_gcc_gp2, 458 msm_mux_gcc_gp3, 459 msm_mux_gps_pps_in, 460 msm_mux_hardsync_pps_in, 461 msm_mux_intr_c, 462 msm_mux_jitter_bist_ref, 463 msm_mux_pcie_clkreqn, 464 msm_mux_phase_flag, 465 msm_mux_pll_bist, 466 msm_mux_pll_clk, 467 msm_mux_prng_rosc, 468 msm_mux_qdss_cti, 469 msm_mux_qdss_gpio, 470 msm_mux_qlink0_enable, 471 msm_mux_qlink0_request, 472 msm_mux_qlink0_wmss, 473 msm_mux_qlink1_enable, 474 msm_mux_qlink1_request, 475 msm_mux_qlink1_wmss, 476 msm_mux_qlink2_enable, 477 msm_mux_qlink2_request, 478 msm_mux_qlink2_wmss, 479 msm_mux_qlink3_enable, 480 msm_mux_qlink3_request, 481 msm_mux_qlink3_wmss, 482 msm_mux_qlink4_enable, 483 msm_mux_qlink4_request, 484 msm_mux_qlink4_wmss, 485 msm_mux_qlink5_enable, 486 msm_mux_qlink5_request, 487 msm_mux_qlink5_wmss, 488 msm_mux_qlink6_enable, 489 msm_mux_qlink6_request, 490 msm_mux_qlink6_wmss, 491 msm_mux_qlink7_enable, 492 msm_mux_qlink7_request, 493 msm_mux_qlink7_wmss, 494 msm_mux_qspi_clk, 495 msm_mux_qspi_cs, 496 msm_mux_qspi0, 497 msm_mux_qspi1, 498 msm_mux_qspi2, 499 msm_mux_qspi3, 500 msm_mux_qup00, 501 msm_mux_qup01, 502 msm_mux_qup02, 503 msm_mux_qup03, 504 msm_mux_qup04, 505 msm_mux_qup05, 506 msm_mux_qup06, 507 msm_mux_qup07, 508 msm_mux_qup08, 509 msm_mux_qup10, 510 msm_mux_qup11, 511 msm_mux_qup12, 512 msm_mux_qup13, 513 msm_mux_qup14, 514 msm_mux_qup15, 515 msm_mux_qup16, 516 msm_mux_qup17, 517 msm_mux_qup20, 518 msm_mux_qup21, 519 msm_mux_qup22, 520 msm_mux_smb_alert, 521 msm_mux_smb_clk, 522 msm_mux_smb_dat, 523 msm_mux_tb_trig, 524 msm_mux_tgu_ch0, 525 msm_mux_tgu_ch1, 526 msm_mux_tgu_ch2, 527 msm_mux_tgu_ch3, 528 msm_mux_tgu_ch4, 529 msm_mux_tgu_ch5, 530 msm_mux_tgu_ch6, 531 msm_mux_tgu_ch7, 532 msm_mux_tmess_prng0, 533 msm_mux_tmess_prng1, 534 msm_mux_tmess_prng2, 535 msm_mux_tmess_prng3, 536 msm_mux_tod_pps_in, 537 msm_mux_tsense_pwm1, 538 msm_mux_tsense_pwm2, 539 msm_mux_usb2phy_ac, 540 msm_mux_usb_con_det, 541 msm_mux_usb_dfp_en, 542 msm_mux_usb_phy, 543 msm_mux_vfr_0, 544 msm_mux_vfr_1, 545 msm_mux_vsense_trigger, 546 msm_mux__, 547}; 548 549static const char * const gpio_groups[] = { 550 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 551 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 552 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 553 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 554 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 555 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 556 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 557 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 558 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", 559 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", 560 "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", 561 "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", 562 "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", 563 "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", 564 "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", 565 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 566 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 567 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 568 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 569 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 570 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 571 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 572 "gpio147", "gpio148", "gpio149", "gpio150", 573}; 574static const char * const cmo_pri_groups[] = { 575 "gpio103", 576}; 577static const char * const si5518_int_groups[] = { 578 "gpio44", 579}; 580static const char * const atest_char_groups[] = { 581 "gpio89", "gpio90", "gpio91", "gpio92", "gpio95", 582}; 583static const char * const atest_usb_groups[] = { 584 "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", 585}; 586static const char * const char_exec_groups[] = { 587 "gpio99", "gpio100", 588}; 589static const char * const cmu_rng_groups[] = { 590 "gpio89", "gpio90", "gpio91", "gpio92", 591}; 592static const char * const dbg_out_clk_groups[] = { 593 "gpio136", 594}; 595static const char * const ddr_bist_groups[] = { 596 "gpio0", "gpio1", "gpio2", "gpio3", 597}; 598static const char * const ddr_pxi0_groups[] = { 599 "gpio114", "gpio115", 600}; 601static const char * const ddr_pxi1_groups[] = { 602 "gpio116", "gpio117", 603}; 604static const char * const ddr_pxi2_groups[] = { 605 "gpio118", "gpio119", 606}; 607static const char * const ddr_pxi3_groups[] = { 608 "gpio120", "gpio121", 609}; 610static const char * const ddr_pxi4_groups[] = { 611 "gpio122", "gpio123", 612}; 613static const char * const ddr_pxi5_groups[] = { 614 "gpio124", "gpio125", 615}; 616static const char * const ddr_pxi6_groups[] = { 617 "gpio126", "gpio127", 618}; 619static const char * const ddr_pxi7_groups[] = { 620 "gpio128", "gpio129", 621}; 622static const char * const eth012_int_n_groups[] = { 623 "gpio86", 624}; 625static const char * const eth345_int_n_groups[] = { 626 "gpio87", 627}; 628static const char * const eth6_int_n_groups[] = { 629 "gpio88", 630}; 631static const char * const gcc_gp1_groups[] = { 632 "gpio86", "gpio134", 633}; 634static const char * const gcc_gp2_groups[] = { 635 "gpio87", "gpio135", 636}; 637static const char * const gcc_gp3_groups[] = { 638 "gpio88", "gpio136", 639}; 640static const char * const gps_pps_in_groups[] = { 641 "gpio49", 642}; 643static const char * const hardsync_pps_in_groups[] = { 644 "gpio47", 645}; 646static const char * const intr_c_groups[] = { 647 "gpio26", "gpio27", "gpio28", "gpio141", "gpio142", "gpio143", 648}; 649static const char * const jitter_bist_ref_groups[] = { 650 "gpio130", 651}; 652static const char * const pcie_clkreqn_groups[] = { 653 "gpio98", "gpio99", "gpio100", 654}; 655static const char * const phase_flag_groups[] = { 656 "gpio6", "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", "gpio18", 657 "gpio19", "gpio20", "gpio22", "gpio21", "gpio23", "gpio24", "gpio25", 658 "gpio26", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32", 659 "gpio33", "gpio42", "gpio43", "gpio89", "gpio90", "gpio91", "gpio92", 660 "gpio95", "gpio96", "gpio97", "gpio102", 661}; 662static const char * const pll_bist_groups[] = { 663 "gpio20", 664}; 665static const char * const pll_clk_groups[] = { 666 "gpio98", 667}; 668static const char * const prng_rosc_groups[] = { 669 "gpio18", "gpio19", "gpio20", "gpio21", 670}; 671static const char * const qdss_cti_groups[] = { 672 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio48", 673 "gpio49", "gpio86", "gpio87", "gpio93", "gpio94", "gpio130", "gpio131", 674 "gpio132", "gpio133", "gpio134", "gpio135", "gpio144", "gpio145", 675}; 676static const char * const qdss_gpio_groups[] = { 677 "gpio6", "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", "gpio18", 678 "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio25", "gpio26", 679 "gpio27", "gpio28", "gpio24", "gpio29", "gpio30", "gpio31", "gpio32", 680 "gpio33", "gpio34", "gpio35", "gpio42", "gpio43", "gpio88", "gpio89", 681 "gpio90", "gpio91", "gpio92", "gpio95", "gpio96", "gpio97", "gpio102", 682 "gpio103", 683}; 684static const char * const qlink0_enable_groups[] = { 685 "gpio67", 686}; 687static const char * const qlink0_request_groups[] = { 688 "gpio66", 689}; 690static const char * const qlink0_wmss_groups[] = { 691 "gpio82", 692}; 693static const char * const qlink1_enable_groups[] = { 694 "gpio69", 695}; 696static const char * const qlink1_request_groups[] = { 697 "gpio68", 698}; 699static const char * const qlink1_wmss_groups[] = { 700 "gpio83", 701}; 702static const char * const qlink2_enable_groups[] = { 703 "gpio71", 704}; 705static const char * const qlink2_request_groups[] = { 706 "gpio70", 707}; 708static const char * const qlink2_wmss_groups[] = { 709 "gpio138", 710}; 711static const char * const qlink3_enable_groups[] = { 712 "gpio73", 713}; 714static const char * const qlink3_request_groups[] = { 715 "gpio72", 716}; 717static const char * const qlink3_wmss_groups[] = { 718 "gpio139", 719}; 720static const char * const qlink4_enable_groups[] = { 721 "gpio75", 722}; 723static const char * const qlink4_request_groups[] = { 724 "gpio74", 725}; 726static const char * const qlink4_wmss_groups[] = { 727 "gpio84", 728}; 729static const char * const qlink5_enable_groups[] = { 730 "gpio77", 731}; 732static const char * const qlink5_request_groups[] = { 733 "gpio76", 734}; 735static const char * const qlink5_wmss_groups[] = { 736 "gpio85", 737}; 738static const char * const qlink6_enable_groups[] = { 739 "gpio79", 740}; 741static const char * const qlink6_request_groups[] = { 742 "gpio78", 743}; 744static const char * const qlink6_wmss_groups[] = { 745 "gpio56", 746}; 747static const char * const qlink7_enable_groups[] = { 748 "gpio81", 749}; 750static const char * const qlink7_request_groups[] = { 751 "gpio80", 752}; 753static const char * const qlink7_wmss_groups[] = { 754 "gpio57", 755}; 756static const char * const qspi0_groups[] = { 757 "gpio114", 758}; 759static const char * const qspi1_groups[] = { 760 "gpio115", 761}; 762static const char * const qspi2_groups[] = { 763 "gpio116", 764}; 765static const char * const qspi3_groups[] = { 766 "gpio117", 767}; 768static const char * const qspi_clk_groups[] = { 769 "gpio126", 770}; 771static const char * const qspi_cs_groups[] = { 772 "gpio125", 773}; 774static const char * const qup00_groups[] = { 775 "gpio6", "gpio7", "gpio8", "gpio9", 776}; 777static const char * const qup01_groups[] = { 778 "gpio10", "gpio11", "gpio12", "gpio13", 779}; 780static const char * const qup02_groups[] = { 781 "gpio10", "gpio11", "gpio12", "gpio13", 782}; 783static const char * const qup03_groups[] = { 784 "gpio14", "gpio15", "gpio16", "gpio17", 785}; 786static const char * const qup04_groups[] = { 787 "gpio14", "gpio15", "gpio16", "gpio17", 788}; 789static const char * const qup05_groups[] = { 790 "gpio130", "gpio131", "gpio132", "gpio133", 791}; 792static const char * const qup06_groups[] = { 793 "gpio130", "gpio131", "gpio132", "gpio133", 794}; 795static const char * const qup07_groups[] = { 796 "gpio134", "gpio135", 797}; 798static const char * const qup08_groups[] = { 799 "gpio134", "gpio135", 800}; 801static const char * const qup10_groups[] = { 802 "gpio18", "gpio19", "gpio20", "gpio21", 803}; 804static const char * const qup11_groups[] = { 805 "gpio22", "gpio23", "gpio24", "gpio25", 806}; 807static const char * const qup12_groups[] = { 808 "gpio22", "gpio23", "gpio24", "gpio25", 809}; 810static const char * const qup13_groups[] = { 811 "gpio26", "gpio27", "gpio28", "gpio29", 812}; 813static const char * const qup14_groups[] = { 814 "gpio26", "gpio27", "gpio28", "gpio29", 815}; 816static const char * const qup15_groups[] = { 817 "gpio30", "gpio31", "gpio32", "gpio33", 818}; 819static const char * const qup16_groups[] = { 820 "gpio29", "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", 821}; 822static const char * const qup17_groups[] = { 823 "gpio12", "gpio13", "gpio14", "gpio30", "gpio31", "gpio40", "gpio41", 824}; 825static const char * const qup20_groups[] = { 826 "gpio0", "gpio1", "gpio2", "gpio3", 827}; 828static const char * const qup21_groups[] = { 829 "gpio0", "gpio1", "gpio2", "gpio3", 830}; 831static const char * const qup22_groups[] = { 832 "gpio4", "gpio5", "gpio128", "gpio129", 833}; 834static const char * const smb_alert_groups[] = { 835 "gpio88", "gpio101", 836}; 837static const char * const smb_clk_groups[] = { 838 "gpio133", 839}; 840static const char * const smb_dat_groups[] = { 841 "gpio132", 842}; 843static const char * const tb_trig_groups[] = { 844 "gpio114", 845}; 846static const char * const tgu_ch0_groups[] = { 847 "gpio6", 848}; 849static const char * const tgu_ch1_groups[] = { 850 "gpio7", 851}; 852static const char * const tgu_ch2_groups[] = { 853 "gpio8", 854}; 855static const char * const tgu_ch3_groups[] = { 856 "gpio9", 857}; 858static const char * const tgu_ch4_groups[] = { 859 "gpio44", 860}; 861static const char * const tgu_ch5_groups[] = { 862 "gpio45", 863}; 864static const char * const tgu_ch6_groups[] = { 865 "gpio46", 866}; 867static const char * const tgu_ch7_groups[] = { 868 "gpio47", 869}; 870static const char * const tmess_prng0_groups[] = { 871 "gpio33", 872}; 873static const char * const tmess_prng1_groups[] = { 874 "gpio32", 875}; 876static const char * const tmess_prng2_groups[] = { 877 "gpio31", 878}; 879static const char * const tmess_prng3_groups[] = { 880 "gpio30", 881}; 882static const char * const tod_pps_in_groups[] = { 883 "gpio48", 884}; 885static const char * const tsense_pwm1_groups[] = { 886 "gpio2", 887}; 888static const char * const tsense_pwm2_groups[] = { 889 "gpio3", 890}; 891static const char * const usb2phy_ac_groups[] = { 892 "gpio90", 893}; 894static const char * const usb_con_det_groups[] = { 895 "gpio42", 896}; 897static const char * const usb_dfp_en_groups[] = { 898 "gpio43", 899}; 900static const char * const usb_phy_groups[] = { 901 "gpio91", 902}; 903static const char * const vfr_0_groups[] = { 904 "gpio93", 905}; 906static const char * const vfr_1_groups[] = { 907 "gpio94", 908}; 909static const char * const vsense_trigger_groups[] = { 910 "gpio135", 911}; 912 913static const struct msm_function qdu1000_functions[] = { 914 FUNCTION(gpio), 915 FUNCTION(cmo_pri), 916 FUNCTION(si5518_int), 917 FUNCTION(atest_char), 918 FUNCTION(atest_usb), 919 FUNCTION(char_exec), 920 FUNCTION(cmu_rng), 921 FUNCTION(dbg_out_clk), 922 FUNCTION(ddr_bist), 923 FUNCTION(ddr_pxi0), 924 FUNCTION(ddr_pxi1), 925 FUNCTION(ddr_pxi2), 926 FUNCTION(ddr_pxi3), 927 FUNCTION(ddr_pxi4), 928 FUNCTION(ddr_pxi5), 929 FUNCTION(ddr_pxi6), 930 FUNCTION(ddr_pxi7), 931 FUNCTION(eth012_int_n), 932 FUNCTION(eth345_int_n), 933 FUNCTION(eth6_int_n), 934 FUNCTION(gcc_gp1), 935 FUNCTION(gcc_gp2), 936 FUNCTION(gcc_gp3), 937 FUNCTION(gps_pps_in), 938 FUNCTION(hardsync_pps_in), 939 FUNCTION(intr_c), 940 FUNCTION(jitter_bist_ref), 941 FUNCTION(pcie_clkreqn), 942 FUNCTION(phase_flag), 943 FUNCTION(pll_bist), 944 FUNCTION(pll_clk), 945 FUNCTION(prng_rosc), 946 FUNCTION(qdss_cti), 947 FUNCTION(qdss_gpio), 948 FUNCTION(qlink0_enable), 949 FUNCTION(qlink0_request), 950 FUNCTION(qlink0_wmss), 951 FUNCTION(qlink1_enable), 952 FUNCTION(qlink1_request), 953 FUNCTION(qlink1_wmss), 954 FUNCTION(qlink2_enable), 955 FUNCTION(qlink2_request), 956 FUNCTION(qlink2_wmss), 957 FUNCTION(qlink3_enable), 958 FUNCTION(qlink3_request), 959 FUNCTION(qlink3_wmss), 960 FUNCTION(qlink4_enable), 961 FUNCTION(qlink4_request), 962 FUNCTION(qlink4_wmss), 963 FUNCTION(qlink5_enable), 964 FUNCTION(qlink5_request), 965 FUNCTION(qlink5_wmss), 966 FUNCTION(qlink6_enable), 967 FUNCTION(qlink6_request), 968 FUNCTION(qlink6_wmss), 969 FUNCTION(qlink7_enable), 970 FUNCTION(qlink7_request), 971 FUNCTION(qlink7_wmss), 972 FUNCTION(qspi0), 973 FUNCTION(qspi1), 974 FUNCTION(qspi2), 975 FUNCTION(qspi3), 976 FUNCTION(qspi_clk), 977 FUNCTION(qspi_cs), 978 FUNCTION(qup00), 979 FUNCTION(qup01), 980 FUNCTION(qup02), 981 FUNCTION(qup03), 982 FUNCTION(qup04), 983 FUNCTION(qup05), 984 FUNCTION(qup06), 985 FUNCTION(qup07), 986 FUNCTION(qup08), 987 FUNCTION(qup10), 988 FUNCTION(qup11), 989 FUNCTION(qup12), 990 FUNCTION(qup13), 991 FUNCTION(qup14), 992 FUNCTION(qup15), 993 FUNCTION(qup16), 994 FUNCTION(qup17), 995 FUNCTION(qup20), 996 FUNCTION(qup21), 997 FUNCTION(qup22), 998 FUNCTION(smb_alert), 999 FUNCTION(smb_clk), 1000 FUNCTION(smb_dat), 1001 FUNCTION(tb_trig), 1002 FUNCTION(tgu_ch0), 1003 FUNCTION(tgu_ch1), 1004 FUNCTION(tgu_ch2), 1005 FUNCTION(tgu_ch3), 1006 FUNCTION(tgu_ch4), 1007 FUNCTION(tgu_ch5), 1008 FUNCTION(tgu_ch6), 1009 FUNCTION(tgu_ch7), 1010 FUNCTION(tmess_prng0), 1011 FUNCTION(tmess_prng1), 1012 FUNCTION(tmess_prng2), 1013 FUNCTION(tmess_prng3), 1014 FUNCTION(tod_pps_in), 1015 FUNCTION(tsense_pwm1), 1016 FUNCTION(tsense_pwm2), 1017 FUNCTION(usb2phy_ac), 1018 FUNCTION(usb_con_det), 1019 FUNCTION(usb_dfp_en), 1020 FUNCTION(usb_phy), 1021 FUNCTION(vfr_0), 1022 FUNCTION(vfr_1), 1023 FUNCTION(vsense_trigger), 1024}; 1025 1026/* 1027 * Every pin is maintained as a single group, and missing or non-existing pin 1028 * would be maintained as dummy group to synchronize pin group index with 1029 * pin descriptor registered with pinctrl core. 1030 * Clients would not be able to request these dummy pin groups. 1031 */ 1032static const struct msm_pingroup qdu1000_groups[] = { 1033 [0] = PINGROUP(0, qup20, qup21, ddr_bist, _, _, _, _, _, _), 1034 [1] = PINGROUP(1, qup20, qup21, ddr_bist, _, _, _, _, _, _), 1035 [2] = PINGROUP(2, qup21, qup20, ddr_bist, _, 1036 tsense_pwm1, _, _, _, _), 1037 [3] = PINGROUP(3, qup21, qup20, ddr_bist, _, 1038 tsense_pwm2, _, _, _, _), 1039 [4] = PINGROUP(4, qup22, _, _, _, _, _, _, _, _), 1040 [5] = PINGROUP(5, qup22, _, _, _, _, _, _, _, _), 1041 [6] = PINGROUP(6, qup00, tgu_ch0, phase_flag, _, 1042 qdss_gpio, _, _, _, _), 1043 [7] = PINGROUP(7, qup00, tgu_ch1, phase_flag, _, 1044 qdss_gpio, _, _, _, _), 1045 [8] = PINGROUP(8, qup00, tgu_ch2, phase_flag, _, 1046 qdss_gpio, _, _, _, _), 1047 [9] = PINGROUP(9, qup00, tgu_ch3, phase_flag, _, 1048 qdss_gpio, _, _, _, _), 1049 [10] = PINGROUP(10, qup01, qup02, _, _, _, _, _, _, _), 1050 [11] = PINGROUP(11, qup01, qup02, _, _, _, _, _, _, _), 1051 [12] = PINGROUP(12, qup02, qup01, qup17, _, _, _, _, _, _), 1052 [13] = PINGROUP(13, qup02, qup01, qup17, _, _, _, _, _, _), 1053 [14] = PINGROUP(14, qup03, qup04, qup17, _, _, _, _, _, _), 1054 [15] = PINGROUP(15, qup03, qup04, _, _, _, _, _, _, _), 1055 [16] = PINGROUP(16, qup04, qup03, phase_flag, _, 1056 qdss_gpio, _, _, _, _), 1057 [17] = PINGROUP(17, qup04, qup03, phase_flag, _, 1058 qdss_gpio, _, _, _, _), 1059 [18] = PINGROUP(18, qup10, prng_rosc, phase_flag, 1060 _, qdss_gpio, _, _, _, _), 1061 [19] = PINGROUP(19, qup10, prng_rosc, phase_flag, 1062 _, qdss_gpio, _, _, _, _), 1063 [20] = PINGROUP(20, qup10, prng_rosc, pll_bist, 1064 phase_flag, _, qdss_gpio, _, _, _), 1065 [21] = PINGROUP(21, qup10, prng_rosc, phase_flag, 1066 _, qdss_gpio, _, _, _, _), 1067 [22] = PINGROUP(22, qup11, qup12, phase_flag, _, 1068 qdss_gpio, _, _, _, _), 1069 [23] = PINGROUP(23, qup11, qup12, phase_flag, _, 1070 qdss_gpio, _, _, _, _), 1071 [24] = PINGROUP(24, qup12, qup11, phase_flag, _, 1072 qdss_gpio, _, _, _, _), 1073 [25] = PINGROUP(25, qup12, qup11, phase_flag, _, 1074 qdss_gpio, _, _, _, _), 1075 [26] = PINGROUP(26, qup13, qup14, intr_c, 1076 phase_flag, _, qdss_gpio, _, _, _), 1077 [27] = PINGROUP(27, qup13, qup14, intr_c, 1078 phase_flag, _, qdss_gpio, _, _, _), 1079 [28] = PINGROUP(28, qup14, qup13, intr_c, 1080 phase_flag, _, qdss_gpio, _, _, _), 1081 [29] = PINGROUP(29, qup14, qup13, qup16, 1082 phase_flag, _, qdss_gpio, _, _, _), 1083 [30] = PINGROUP(30, qup17, qup15, tmess_prng3, 1084 phase_flag, _, qdss_gpio, _, _, _), 1085 [31] = PINGROUP(31, qup17, qup15, tmess_prng2, 1086 phase_flag, _, qdss_gpio, _, _, _), 1087 [32] = PINGROUP(32, qup15, tmess_prng1, phase_flag, 1088 _, qdss_gpio, _, _, _, _), 1089 [33] = PINGROUP(33, qup15, tmess_prng0, phase_flag, 1090 _, qdss_gpio, _, _, _, _), 1091 [34] = PINGROUP(34, qup16, qdss_gpio, _, _, _, _, _, _, _), 1092 [35] = PINGROUP(35, qup16, qdss_gpio, _, _, _, _, _, _, _), 1093 [36] = PINGROUP(36, qup16, qdss_cti, _, _, _, _, _, _, _), 1094 [37] = PINGROUP(37, qup16, qdss_cti, _, _, _, _, _, _, _), 1095 [38] = PINGROUP(38, qup16, qdss_cti, _, _, _, _, _, _, _), 1096 [39] = PINGROUP(39, qup16, qdss_cti, _, _, _, _, _, _, _), 1097 [40] = PINGROUP(40, qup17, qdss_cti, _, _, _, _, _, _, _), 1098 [41] = PINGROUP(41, qup17, qdss_cti, _, _, _, _, _, _, _), 1099 [42] = PINGROUP(42, usb_con_det, phase_flag, _, 1100 qdss_gpio, _, _, _, _, _), 1101 [43] = PINGROUP(43, usb_dfp_en, phase_flag, _, 1102 qdss_gpio, _, _, _, _, _), 1103 [44] = PINGROUP(44, si5518_int, tgu_ch4, _, _, _, _, _, _, _), 1104 [45] = PINGROUP(45, tgu_ch5, _, _, _, _, _, _, _, _), 1105 [46] = PINGROUP(46, tgu_ch6, _, _, _, _, _, _, _, _), 1106 [47] = PINGROUP(47, hardsync_pps_in, tgu_ch7, _, _, _, _, _, _, _), 1107 [48] = PINGROUP(48, tod_pps_in, qdss_cti, _, _, _, _, _, _, _), 1108 [49] = PINGROUP(49, gps_pps_in, qdss_cti, _, _, _, _, _, _, _), 1109 [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _), 1110 [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _), 1111 [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _), 1112 [53] = PINGROUP(53, _, _, _, _, _, _, _, _, _), 1113 [54] = PINGROUP(54, _, _, _, _, _, _, _, _, _), 1114 [55] = PINGROUP(55, _, _, _, _, _, _, _, _, _), 1115 [56] = PINGROUP(56, _, qlink6_wmss, _, _, _, _, _, _, _), 1116 [57] = PINGROUP(57, _, qlink7_wmss, _, _, _, _, _, _, _), 1117 [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _), 1118 [59] = PINGROUP(59, _, _, _, _, _, _, _, _, _), 1119 [60] = PINGROUP(60, _, _, _, _, _, _, _, _, _), 1120 [61] = PINGROUP(61, _, _, _, _, _, _, _, _, _), 1121 [62] = PINGROUP(62, _, _, _, _, _, _, _, _, _), 1122 [63] = PINGROUP(63, _, _, _, _, _, _, _, _, _), 1123 [64] = PINGROUP(64, _, _, _, _, _, _, _, _, _), 1124 [65] = PINGROUP(65, _, _, _, _, _, _, _, _, _), 1125 [66] = PINGROUP(66, qlink0_request, _, _, _, _, _, _, _, _), 1126 [67] = PINGROUP(67, qlink0_enable, _, _, _, _, _, _, _, _), 1127 [68] = PINGROUP(68, qlink1_request, _, _, _, _, _, _, _, _), 1128 [69] = PINGROUP(69, qlink1_enable, _, _, _, _, _, _, _, _), 1129 [70] = PINGROUP(70, qlink2_request, _, _, _, _, _, _, _, _), 1130 [71] = PINGROUP(71, qlink2_enable, _, _, _, _, _, _, _, _), 1131 [72] = PINGROUP(72, qlink3_request, _, _, _, _, _, _, _, _), 1132 [73] = PINGROUP(73, qlink3_enable, _, _, _, _, _, _, _, _), 1133 [74] = PINGROUP(74, qlink4_request, _, _, _, _, _, _, _, _), 1134 [75] = PINGROUP(75, qlink4_enable, _, _, _, _, _, _, _, _), 1135 [76] = PINGROUP(76, qlink5_request, _, _, _, _, _, _, _, _), 1136 [77] = PINGROUP(77, qlink5_enable, _, _, _, _, _, _, _, _), 1137 [78] = PINGROUP(78, qlink6_request, _, _, _, _, _, _, _, _), 1138 [79] = PINGROUP(79, qlink6_enable, _, _, _, _, _, _, _, _), 1139 [80] = PINGROUP(80, qlink7_request, _, _, _, _, _, _, _, _), 1140 [81] = PINGROUP(81, qlink7_enable, _, _, _, _, _, _, _, _), 1141 [82] = PINGROUP(82, qlink0_wmss, _, _, _, _, _, _, _, _), 1142 [83] = PINGROUP(83, qlink1_wmss, _, _, _, _, _, _, _, _), 1143 [84] = PINGROUP(84, qlink4_wmss, _, _, _, _, _, _, _, _), 1144 [85] = PINGROUP(85, qlink5_wmss, _, _, _, _, _, _, _, _), 1145 [86] = PINGROUP(86, eth012_int_n, gcc_gp1, _, qdss_cti, _, _, _, _, _), 1146 [87] = PINGROUP(87, eth345_int_n, gcc_gp2, _, qdss_cti, _, _, _, _, _), 1147 [88] = PINGROUP(88, eth6_int_n, smb_alert, gcc_gp3, _, 1148 qdss_gpio, _, _, _, _), 1149 [89] = PINGROUP(89, phase_flag, cmu_rng, _, 1150 qdss_gpio, atest_char, _, _, _, _), 1151 [90] = PINGROUP(90, usb2phy_ac, phase_flag, 1152 cmu_rng, _, qdss_gpio, 1153 atest_char, _, _, _), 1154 [91] = PINGROUP(91, usb_phy, phase_flag, cmu_rng, 1155 _, qdss_gpio, atest_char, _, _, _), 1156 [92] = PINGROUP(92, phase_flag, cmu_rng, _, 1157 qdss_gpio, atest_char, _, _, _, _), 1158 [93] = PINGROUP(93, vfr_0, qdss_cti, _, _, _, _, _, _, _), 1159 [94] = PINGROUP(94, vfr_1, qdss_cti, _, _, _, _, _, _, _), 1160 [95] = PINGROUP(95, phase_flag, _, qdss_gpio, 1161 atest_char, _, _, _, _, _), 1162 [96] = PINGROUP(96, phase_flag, _, qdss_gpio, _, _, _, _, _, _), 1163 [97] = PINGROUP(97, phase_flag, _, qdss_gpio, _, _, _, _, _, _), 1164 [98] = PINGROUP(98, pll_clk, _, _, _, _, _, _, _, _), 1165 [99] = PINGROUP(99, pcie_clkreqn, char_exec, _, _, _, _, _, _, _), 1166 [100] = PINGROUP(100, char_exec, _, _, _, _, _, _, _, _), 1167 [101] = PINGROUP(101, smb_alert, _, _, _, _, _, _, _, _), 1168 [102] = PINGROUP(102, phase_flag, _, qdss_gpio, _, _, _, _, _, _), 1169 [103] = PINGROUP(103, cmo_pri, qdss_gpio, _, _, _, _, _, _, _), 1170 [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _), 1171 [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _), 1172 [106] = PINGROUP(106, _, _, _, _, _, _, _, _, _), 1173 [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _), 1174 [108] = PINGROUP(108, _, _, _, _, _, _, _, _, _), 1175 [109] = PINGROUP(109, _, _, _, _, _, _, _, _, _), 1176 [110] = PINGROUP(110, _, _, _, _, _, _, _, _, _), 1177 [111] = PINGROUP(111, _, _, _, _, _, _, _, _, _), 1178 [112] = PINGROUP(112, _, _, _, _, _, _, _, _, _), 1179 [113] = PINGROUP(113, _, _, _, _, _, _, _, _, _), 1180 [114] = PINGROUP(114, qspi0, tb_trig, _, 1181 atest_usb, ddr_pxi0, _, _, _, _), 1182 [115] = PINGROUP(115, qspi1, _, atest_usb, 1183 ddr_pxi0, _, _, _, _, _), 1184 [116] = PINGROUP(116, qspi2, _, atest_usb, 1185 ddr_pxi1, _, _, _, _, _), 1186 [117] = PINGROUP(117, qspi3, _, atest_usb, 1187 ddr_pxi1, _, _, _, _, _), 1188 [118] = PINGROUP(118, _, atest_usb, ddr_pxi2, _, _, _, _, _, _), 1189 [119] = PINGROUP(119, _, _, ddr_pxi2, _, _, _, _, _, _), 1190 [120] = PINGROUP(120, _, _, ddr_pxi3, _, _, _, _, _, _), 1191 [121] = PINGROUP(121, _, ddr_pxi3, _, _, _, _, _, _, _), 1192 [122] = PINGROUP(122, _, ddr_pxi4, _, _, _, _, _, _, _), 1193 [123] = PINGROUP(123, _, ddr_pxi4, _, _, _, _, _, _, _), 1194 [124] = PINGROUP(124, _, ddr_pxi5, _, _, _, _, _, _, _), 1195 [125] = PINGROUP(125, qspi_cs, _, ddr_pxi5, _, _, _, _, _, _), 1196 [126] = PINGROUP(126, qspi_clk, _, ddr_pxi6, _, _, _, _, _, _), 1197 [127] = PINGROUP(127, _, ddr_pxi6, _, _, _, _, _, _, _), 1198 [128] = PINGROUP(128, qup22, _, ddr_pxi7, _, _, _, _, _, _), 1199 [129] = PINGROUP(129, qup22, ddr_pxi7, _, _, _, _, _, _, _), 1200 [130] = PINGROUP(130, qup05, qup06, jitter_bist_ref, 1201 qdss_cti, _, _, _, _, _), 1202 [131] = PINGROUP(131, qup05, qup06, qdss_cti, _, _, _, _, _, _), 1203 [132] = PINGROUP(132, qup06, qup05, smb_dat, 1204 qdss_cti, _, _, _, _, _), 1205 [133] = PINGROUP(133, qup06, qup05, smb_clk, 1206 qdss_cti, _, _, _, _, _), 1207 [134] = PINGROUP(134, qup08, qup07, gcc_gp1, _, 1208 qdss_cti, _, _, _, _), 1209 [135] = PINGROUP(135, qup08, qup07, gcc_gp2, _, 1210 qdss_cti, vsense_trigger, _, _, _), 1211 [136] = PINGROUP(136, gcc_gp3, dbg_out_clk, _, _, _, _, _, _, _), 1212 [137] = PINGROUP(137, _, _, _, _, _, _, _, _, _), 1213 [138] = PINGROUP(138, qlink2_wmss, _, _, _, _, _, _, _, _), 1214 [139] = PINGROUP(139, qlink3_wmss, _, _, _, _, _, _, _, _), 1215 [140] = PINGROUP(140, _, _, _, _, _, _, _, _, _), 1216 [141] = PINGROUP(141, intr_c, _, _, _, _, _, _, _, _), 1217 [142] = PINGROUP(142, intr_c, _, _, _, _, _, _, _, _), 1218 [143] = PINGROUP(143, intr_c, _, _, _, _, _, _, _, _), 1219 [144] = PINGROUP(144, qdss_cti, _, _, _, _, _, _, _, _), 1220 [145] = PINGROUP(145, qdss_cti, _, _, _, _, _, _, _, _), 1221 [146] = PINGROUP(146, _, _, _, _, _, _, _, _, _), 1222 [147] = PINGROUP(147, _, _, _, _, _, _, _, _, _), 1223 [148] = PINGROUP(148, _, _, _, _, _, _, _, _, _), 1224 [149] = PINGROUP(149, _, _, _, _, _, _, _, _, _), 1225 [150] = PINGROUP(150, _, _, _, _, _, _, _, _, _), 1226 [151] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9e000, 0, 0), 1227 [152] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9d000, 13, 6), 1228 [153] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9d000, 11, 3), 1229 [154] = SDC_QDSD_PINGROUP(sdc1_data, 0x9d000, 9, 0), 1230}; 1231static const struct msm_pinctrl_soc_data qdu1000_tlmm = { 1232 .pins = qdu1000_pins, 1233 .npins = ARRAY_SIZE(qdu1000_pins), 1234 .functions = qdu1000_functions, 1235 .nfunctions = ARRAY_SIZE(qdu1000_functions), 1236 .groups = qdu1000_groups, 1237 .ngroups = ARRAY_SIZE(qdu1000_groups), 1238 .ngpios = 151, 1239}; 1240 1241static int qdu1000_tlmm_probe(struct platform_device *pdev) 1242{ 1243 return msm_pinctrl_probe(pdev, &qdu1000_tlmm); 1244} 1245 1246static const struct of_device_id qdu1000_tlmm_of_match[] = { 1247 { .compatible = "qcom,qdu1000-tlmm", }, 1248 { }, 1249}; 1250MODULE_DEVICE_TABLE(of, qdu1000_tlmm_of_match); 1251 1252static struct platform_driver qdu1000_tlmm_driver = { 1253 .driver = { 1254 .name = "qdu1000-tlmm", 1255 .of_match_table = qdu1000_tlmm_of_match, 1256 }, 1257 .probe = qdu1000_tlmm_probe, 1258 .remove = msm_pinctrl_remove, 1259}; 1260 1261static int __init qdu1000_tlmm_init(void) 1262{ 1263 return platform_driver_register(&qdu1000_tlmm_driver); 1264} 1265arch_initcall(qdu1000_tlmm_init); 1266 1267static void __exit qdu1000_tlmm_exit(void) 1268{ 1269 platform_driver_unregister(&qdu1000_tlmm_driver); 1270} 1271module_exit(qdu1000_tlmm_exit); 1272 1273MODULE_DESCRIPTION("QTI QDU1000 TLMM driver"); 1274MODULE_LICENSE("GPL");