tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / drivers / irqchip / Kconfig
at v6.3-rc2 678 lines 16 kB view raw
1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 select IRQ_DOMAIN_HIERARCHY 11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 12 13config ARM_GIC_PM 14 bool 15 depends on PM 16 select ARM_GIC 17 18config ARM_GIC_MAX_NR 19 int 20 depends on ARM_GIC 21 default 2 if ARCH_REALVIEW 22 default 1 23 24config ARM_GIC_V2M 25 bool 26 depends on PCI 27 select ARM_GIC 28 select PCI_MSI 29 30config GIC_NON_BANKED 31 bool 32 33config ARM_GIC_V3 34 bool 35 select IRQ_DOMAIN_HIERARCHY 36 select PARTITION_PERCPU 37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 38 39config ARM_GIC_V3_ITS 40 bool 41 select GENERIC_MSI_IRQ 42 default ARM_GIC_V3 43 44config ARM_GIC_V3_ITS_PCI 45 bool 46 depends on ARM_GIC_V3_ITS 47 depends on PCI 48 depends on PCI_MSI 49 default ARM_GIC_V3_ITS 50 51config ARM_GIC_V3_ITS_FSL_MC 52 bool 53 depends on ARM_GIC_V3_ITS 54 depends on FSL_MC_BUS 55 default ARM_GIC_V3_ITS 56 57config ARM_NVIC 58 bool 59 select IRQ_DOMAIN_HIERARCHY 60 select GENERIC_IRQ_CHIP 61 62config ARM_VIC 63 bool 64 select IRQ_DOMAIN 65 66config ARM_VIC_NR 67 int 68 default 4 if ARCH_S5PV210 69 default 2 70 depends on ARM_VIC 71 help 72 The maximum number of VICs available in the system, for 73 power management. 74 75config ARMADA_370_XP_IRQ 76 bool 77 select GENERIC_IRQ_CHIP 78 select PCI_MSI if PCI 79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 80 81config ALPINE_MSI 82 bool 83 depends on PCI 84 select PCI_MSI 85 select GENERIC_IRQ_CHIP 86 87config AL_FIC 88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 89 depends on OF 90 select GENERIC_IRQ_CHIP 91 select IRQ_DOMAIN 92 help 93 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 94 95config ATMEL_AIC_IRQ 96 bool 97 select GENERIC_IRQ_CHIP 98 select IRQ_DOMAIN 99 select SPARSE_IRQ 100 101config ATMEL_AIC5_IRQ 102 bool 103 select GENERIC_IRQ_CHIP 104 select IRQ_DOMAIN 105 select SPARSE_IRQ 106 107config I8259 108 bool 109 select IRQ_DOMAIN 110 111config BCM6345_L1_IRQ 112 bool 113 select GENERIC_IRQ_CHIP 114 select IRQ_DOMAIN 115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 116 117config BCM7038_L1_IRQ 118 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 119 depends on ARCH_BRCMSTB || BMIPS_GENERIC 120 default ARCH_BRCMSTB || BMIPS_GENERIC 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 124 125config BCM7120_L2_IRQ 126 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 127 depends on ARCH_BRCMSTB || BMIPS_GENERIC 128 default ARCH_BRCMSTB || BMIPS_GENERIC 129 select GENERIC_IRQ_CHIP 130 select IRQ_DOMAIN 131 132config BRCMSTB_L2_IRQ 133 tristate "Broadcom STB generic L2 interrupt controller driver" 134 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 135 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 136 select GENERIC_IRQ_CHIP 137 select IRQ_DOMAIN 138 139config DAVINCI_CP_INTC 140 bool 141 select GENERIC_IRQ_CHIP 142 select IRQ_DOMAIN 143 144config DW_APB_ICTL 145 bool 146 select GENERIC_IRQ_CHIP 147 select IRQ_DOMAIN_HIERARCHY 148 149config FARADAY_FTINTC010 150 bool 151 select IRQ_DOMAIN 152 select SPARSE_IRQ 153 154config HISILICON_IRQ_MBIGEN 155 bool 156 select ARM_GIC_V3 157 select ARM_GIC_V3_ITS 158 159config IMGPDC_IRQ 160 bool 161 select GENERIC_IRQ_CHIP 162 select IRQ_DOMAIN 163 164config IXP4XX_IRQ 165 bool 166 select IRQ_DOMAIN 167 select SPARSE_IRQ 168 169config MADERA_IRQ 170 tristate 171 172config IRQ_MIPS_CPU 173 bool 174 select GENERIC_IRQ_CHIP 175 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 176 select IRQ_DOMAIN 177 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 178 179config CLPS711X_IRQCHIP 180 bool 181 depends on ARCH_CLPS711X 182 select IRQ_DOMAIN 183 select SPARSE_IRQ 184 default y 185 186config OMPIC 187 bool 188 189config OR1K_PIC 190 bool 191 select IRQ_DOMAIN 192 193config OMAP_IRQCHIP 194 bool 195 select GENERIC_IRQ_CHIP 196 select IRQ_DOMAIN 197 198config ORION_IRQCHIP 199 bool 200 select IRQ_DOMAIN 201 202config PIC32_EVIC 203 bool 204 select GENERIC_IRQ_CHIP 205 select IRQ_DOMAIN 206 207config JCORE_AIC 208 bool "J-Core integrated AIC" if COMPILE_TEST 209 depends on OF 210 select IRQ_DOMAIN 211 help 212 Support for the J-Core integrated AIC. 213 214config RDA_INTC 215 bool 216 select IRQ_DOMAIN 217 218config RENESAS_INTC_IRQPIN 219 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 220 select IRQ_DOMAIN 221 help 222 Enable support for the Renesas Interrupt Controller for external 223 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 224 225config RENESAS_IRQC 226 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 227 select GENERIC_IRQ_CHIP 228 select IRQ_DOMAIN 229 help 230 Enable support for the Renesas Interrupt Controller for external 231 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 232 233config RENESAS_RZA1_IRQC 234 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 235 select IRQ_DOMAIN_HIERARCHY 236 help 237 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 238 to 8 external interrupts with configurable sense select. 239 240config RENESAS_RZG2L_IRQC 241 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 242 select GENERIC_IRQ_CHIP 243 select IRQ_DOMAIN_HIERARCHY 244 help 245 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 246 for external devices. 247 248config SL28CPLD_INTC 249 bool "Kontron sl28cpld IRQ controller" 250 depends on MFD_SL28CPLD=y || COMPILE_TEST 251 select REGMAP_IRQ 252 help 253 Interrupt controller driver for the board management controller 254 found on the Kontron sl28 CPLD. 255 256config ST_IRQCHIP 257 bool 258 select REGMAP 259 select MFD_SYSCON 260 help 261 Enables SysCfg Controlled IRQs on STi based platforms. 262 263config SUN4I_INTC 264 bool 265 266config SUN6I_R_INTC 267 bool 268 select IRQ_DOMAIN_HIERARCHY 269 select IRQ_FASTEOI_HIERARCHY_HANDLERS 270 271config SUNXI_NMI_INTC 272 bool 273 select GENERIC_IRQ_CHIP 274 275config TB10X_IRQC 276 bool 277 select IRQ_DOMAIN 278 select GENERIC_IRQ_CHIP 279 280config TS4800_IRQ 281 tristate "TS-4800 IRQ controller" 282 select IRQ_DOMAIN 283 depends on HAS_IOMEM 284 depends on SOC_IMX51 || COMPILE_TEST 285 help 286 Support for the TS-4800 FPGA IRQ controller 287 288config VERSATILE_FPGA_IRQ 289 bool 290 select IRQ_DOMAIN 291 292config VERSATILE_FPGA_IRQ_NR 293 int 294 default 4 295 depends on VERSATILE_FPGA_IRQ 296 297config XTENSA_MX 298 bool 299 select IRQ_DOMAIN 300 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 301 302config XILINX_INTC 303 bool "Xilinx Interrupt Controller IP" 304 depends on OF_ADDRESS 305 select IRQ_DOMAIN 306 help 307 Support for the Xilinx Interrupt Controller IP core. 308 This is used as a primary controller with MicroBlaze and can also 309 be used as a secondary chained controller on other platforms. 310 311config IRQ_CROSSBAR 312 bool 313 help 314 Support for a CROSSBAR ip that precedes the main interrupt controller. 315 The primary irqchip invokes the crossbar's callback which inturn allocates 316 a free irq and configures the IP. Thus the peripheral interrupts are 317 routed to one of the free irqchip interrupt lines. 318 319config KEYSTONE_IRQ 320 tristate "Keystone 2 IRQ controller IP" 321 depends on ARCH_KEYSTONE 322 help 323 Support for Texas Instruments Keystone 2 IRQ controller IP which 324 is part of the Keystone 2 IPC mechanism 325 326config MIPS_GIC 327 bool 328 select GENERIC_IRQ_IPI if SMP 329 select IRQ_DOMAIN_HIERARCHY 330 select MIPS_CM 331 332config INGENIC_IRQ 333 bool 334 depends on MACH_INGENIC 335 default y 336 337config INGENIC_TCU_IRQ 338 bool "Ingenic JZ47xx TCU interrupt controller" 339 default MACH_INGENIC 340 depends on MIPS || COMPILE_TEST 341 select MFD_SYSCON 342 select GENERIC_IRQ_CHIP 343 help 344 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 345 JZ47xx SoCs. 346 347 If unsure, say N. 348 349config IMX_GPCV2 350 bool 351 select IRQ_DOMAIN 352 help 353 Enables the wakeup IRQs for IMX platforms with GPCv2 block 354 355config IRQ_MXS 356 def_bool y if MACH_ASM9260 || ARCH_MXS 357 select IRQ_DOMAIN 358 select STMP_DEVICE 359 360config MSCC_OCELOT_IRQ 361 bool 362 select IRQ_DOMAIN 363 select GENERIC_IRQ_CHIP 364 365config MVEBU_GICP 366 bool 367 368config MVEBU_ICU 369 bool 370 371config MVEBU_ODMI 372 bool 373 select GENERIC_MSI_IRQ 374 375config MVEBU_PIC 376 bool 377 378config MVEBU_SEI 379 bool 380 381config LS_EXTIRQ 382 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 383 select MFD_SYSCON 384 385config LS_SCFG_MSI 386 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 387 depends on PCI_MSI 388 389config PARTITION_PERCPU 390 bool 391 392config STM32_EXTI 393 bool 394 select IRQ_DOMAIN 395 select GENERIC_IRQ_CHIP 396 397config QCOM_IRQ_COMBINER 398 bool "QCOM IRQ combiner support" 399 depends on ARCH_QCOM && ACPI 400 select IRQ_DOMAIN_HIERARCHY 401 help 402 Say yes here to add support for the IRQ combiner devices embedded 403 in Qualcomm Technologies chips. 404 405config IRQ_UNIPHIER_AIDET 406 bool "UniPhier AIDET support" if COMPILE_TEST 407 depends on ARCH_UNIPHIER || COMPILE_TEST 408 default ARCH_UNIPHIER 409 select IRQ_DOMAIN_HIERARCHY 410 help 411 Support for the UniPhier AIDET (ARM Interrupt Detector). 412 413config MESON_IRQ_GPIO 414 tristate "Meson GPIO Interrupt Multiplexer" 415 depends on ARCH_MESON || COMPILE_TEST 416 default ARCH_MESON 417 select IRQ_DOMAIN_HIERARCHY 418 help 419 Support Meson SoC Family GPIO Interrupt Multiplexer 420 421config GOLDFISH_PIC 422 bool "Goldfish programmable interrupt controller" 423 depends on MIPS && (GOLDFISH || COMPILE_TEST) 424 select GENERIC_IRQ_CHIP 425 select IRQ_DOMAIN 426 help 427 Say yes here to enable Goldfish interrupt controller driver used 428 for Goldfish based virtual platforms. 429 430config QCOM_PDC 431 tristate "QCOM PDC" 432 depends on ARCH_QCOM 433 select IRQ_DOMAIN_HIERARCHY 434 help 435 Power Domain Controller driver to manage and configure wakeup 436 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 437 438config QCOM_MPM 439 tristate "QCOM MPM" 440 depends on ARCH_QCOM 441 depends on MAILBOX 442 select IRQ_DOMAIN_HIERARCHY 443 help 444 MSM Power Manager driver to manage and configure wakeup 445 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 446 447config CSKY_MPINTC 448 bool 449 depends on CSKY 450 help 451 Say yes here to enable C-SKY SMP interrupt controller driver used 452 for C-SKY SMP system. 453 In fact it's not mmio map in hardware and it uses ld/st to visit the 454 controller's register inside CPU. 455 456config CSKY_APB_INTC 457 bool "C-SKY APB Interrupt Controller" 458 depends on CSKY 459 help 460 Say yes here to enable C-SKY APB interrupt controller driver used 461 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 462 the controller's register. 463 464config IMX_IRQSTEER 465 bool "i.MX IRQSTEER support" 466 depends on ARCH_MXC || COMPILE_TEST 467 default ARCH_MXC 468 select IRQ_DOMAIN 469 help 470 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 471 472config IMX_INTMUX 473 bool "i.MX INTMUX support" if COMPILE_TEST 474 default y if ARCH_MXC 475 select IRQ_DOMAIN 476 help 477 Support for the i.MX INTMUX interrupt multiplexer. 478 479config IMX_MU_MSI 480 tristate "i.MX MU used as MSI controller" 481 depends on OF && HAS_IOMEM 482 depends on ARCH_MXC || COMPILE_TEST 483 default m if ARCH_MXC 484 select IRQ_DOMAIN 485 select IRQ_DOMAIN_HIERARCHY 486 select GENERIC_MSI_IRQ 487 help 488 Provide a driver for the i.MX Messaging Unit block used as a 489 CPU-to-CPU MSI controller. This requires a specially crafted DT 490 to make use of this driver. 491 492 If unsure, say N 493 494config LS1X_IRQ 495 bool "Loongson-1 Interrupt Controller" 496 depends on MACH_LOONGSON32 497 default y 498 select IRQ_DOMAIN 499 select GENERIC_IRQ_CHIP 500 help 501 Support for the Loongson-1 platform Interrupt Controller. 502 503config TI_SCI_INTR_IRQCHIP 504 bool 505 depends on TI_SCI_PROTOCOL 506 select IRQ_DOMAIN_HIERARCHY 507 help 508 This enables the irqchip driver support for K3 Interrupt router 509 over TI System Control Interface available on some new TI's SoCs. 510 If you wish to use interrupt router irq resources managed by the 511 TI System Controller, say Y here. Otherwise, say N. 512 513config TI_SCI_INTA_IRQCHIP 514 bool 515 depends on TI_SCI_PROTOCOL 516 select IRQ_DOMAIN_HIERARCHY 517 select TI_SCI_INTA_MSI_DOMAIN 518 help 519 This enables the irqchip driver support for K3 Interrupt aggregator 520 over TI System Control Interface available on some new TI's SoCs. 521 If you wish to use interrupt aggregator irq resources managed by the 522 TI System Controller, say Y here. Otherwise, say N. 523 524config TI_PRUSS_INTC 525 tristate 526 depends on TI_PRUSS 527 default TI_PRUSS 528 select IRQ_DOMAIN 529 help 530 This enables support for the PRU-ICSS Local Interrupt Controller 531 present within a PRU-ICSS subsystem present on various TI SoCs. 532 The PRUSS INTC enables various interrupts to be routed to multiple 533 different processors within the SoC. 534 535config RISCV_INTC 536 bool 537 depends on RISCV 538 539config SIFIVE_PLIC 540 bool 541 depends on RISCV 542 select IRQ_DOMAIN_HIERARCHY 543 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 544 545config EXYNOS_IRQ_COMBINER 546 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 547 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 548 help 549 Say yes here to add support for the IRQ combiner devices embedded 550 in Samsung Exynos chips. 551 552config IRQ_LOONGARCH_CPU 553 bool 554 select GENERIC_IRQ_CHIP 555 select IRQ_DOMAIN 556 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 557 select LOONGSON_HTVEC 558 select LOONGSON_LIOINTC 559 select LOONGSON_EIOINTC 560 select LOONGSON_PCH_PIC 561 select LOONGSON_PCH_MSI 562 select LOONGSON_PCH_LPC 563 help 564 Support for the LoongArch CPU Interrupt Controller. For details of 565 irq chip hierarchy on LoongArch platforms please read the document 566 Documentation/loongarch/irq-chip-model.rst. 567 568config LOONGSON_LIOINTC 569 bool "Loongson Local I/O Interrupt Controller" 570 depends on MACH_LOONGSON64 571 default y 572 select IRQ_DOMAIN 573 select GENERIC_IRQ_CHIP 574 help 575 Support for the Loongson Local I/O Interrupt Controller. 576 577config LOONGSON_EIOINTC 578 bool "Loongson Extend I/O Interrupt Controller" 579 depends on LOONGARCH 580 depends on MACH_LOONGSON64 581 default MACH_LOONGSON64 582 select IRQ_DOMAIN_HIERARCHY 583 select GENERIC_IRQ_CHIP 584 help 585 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 586 587config LOONGSON_HTPIC 588 bool "Loongson3 HyperTransport PIC Controller" 589 depends on MACH_LOONGSON64 && MIPS 590 default y 591 select IRQ_DOMAIN 592 select GENERIC_IRQ_CHIP 593 help 594 Support for the Loongson-3 HyperTransport PIC Controller. 595 596config LOONGSON_HTVEC 597 bool "Loongson HyperTransport Interrupt Vector Controller" 598 depends on MACH_LOONGSON64 599 default MACH_LOONGSON64 600 select IRQ_DOMAIN_HIERARCHY 601 help 602 Support for the Loongson HyperTransport Interrupt Vector Controller. 603 604config LOONGSON_PCH_PIC 605 bool "Loongson PCH PIC Controller" 606 depends on MACH_LOONGSON64 607 default MACH_LOONGSON64 608 select IRQ_DOMAIN_HIERARCHY 609 select IRQ_FASTEOI_HIERARCHY_HANDLERS 610 help 611 Support for the Loongson PCH PIC Controller. 612 613config LOONGSON_PCH_MSI 614 bool "Loongson PCH MSI Controller" 615 depends on MACH_LOONGSON64 616 depends on PCI 617 default MACH_LOONGSON64 618 select IRQ_DOMAIN_HIERARCHY 619 select PCI_MSI 620 help 621 Support for the Loongson PCH MSI Controller. 622 623config LOONGSON_PCH_LPC 624 bool "Loongson PCH LPC Controller" 625 depends on LOONGARCH 626 depends on MACH_LOONGSON64 627 default MACH_LOONGSON64 628 select IRQ_DOMAIN_HIERARCHY 629 help 630 Support for the Loongson PCH LPC Controller. 631 632config MST_IRQ 633 bool "MStar Interrupt Controller" 634 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 635 default ARCH_MEDIATEK 636 select IRQ_DOMAIN 637 select IRQ_DOMAIN_HIERARCHY 638 help 639 Support MStar Interrupt Controller. 640 641config WPCM450_AIC 642 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 643 depends on ARCH_WPCM450 644 help 645 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 646 647config IRQ_IDT3243X 648 bool 649 select GENERIC_IRQ_CHIP 650 select IRQ_DOMAIN 651 652config APPLE_AIC 653 bool "Apple Interrupt Controller (AIC)" 654 depends on ARM64 655 depends on ARCH_APPLE || COMPILE_TEST 656 select GENERIC_IRQ_IPI_MUX 657 help 658 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 659 such as the M1. 660 661config MCHP_EIC 662 bool "Microchip External Interrupt Controller" 663 depends on ARCH_AT91 || COMPILE_TEST 664 select IRQ_DOMAIN 665 select IRQ_DOMAIN_HIERARCHY 666 help 667 Support for Microchip External Interrupt Controller. 668 669config SUNPLUS_SP7021_INTC 670 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 671 default SOC_SP7021 672 help 673 Support for the Sunplus SP7021 Interrupt Controller IP core. 674 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 675 chained controller, routing all interrupt source in P-Chip to 676 the primary controller on C-Chip. 677 678endmenu