tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include "amdgpu.h"
26#include "amdgpu_vcn.h"
27#include "amdgpu_pm.h"
28#include "amdgpu_cs.h"
29#include "soc15.h"
30#include "soc15d.h"
31#include "soc15_hw_ip.h"
32#include "vcn_v2_0.h"
33#include "mmsch_v4_0.h"
34#include "vcn_v4_0.h"
35
36#include "vcn/vcn_4_0_0_offset.h"
37#include "vcn/vcn_4_0_0_sh_mask.h"
38#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
39
40#include <drm/drm_drv.h>
41
42#define mmUVD_DPG_LMA_CTL regUVD_DPG_LMA_CTL
43#define mmUVD_DPG_LMA_CTL_BASE_IDX regUVD_DPG_LMA_CTL_BASE_IDX
44#define mmUVD_DPG_LMA_DATA regUVD_DPG_LMA_DATA
45#define mmUVD_DPG_LMA_DATA_BASE_IDX regUVD_DPG_LMA_DATA_BASE_IDX
46
47#define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
48#define VCN1_VID_SOC_ADDRESS_3_0 0x48300
49
50#define VCN_HARVEST_MMSCH 0
51
52#define RDECODE_MSG_CREATE 0x00000000
53#define RDECODE_MESSAGE_CREATE 0x00000001
54
55static int amdgpu_ih_clientid_vcns[] = {
56 SOC15_IH_CLIENTID_VCN,
57 SOC15_IH_CLIENTID_VCN1
58};
59
60static int vcn_v4_0_start_sriov(struct amdgpu_device *adev);
61static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev);
62static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev);
63static int vcn_v4_0_set_powergating_state(void *handle,
64 enum amd_powergating_state state);
65static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
66 int inst_idx, struct dpg_pause_state *new_state);
67static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
68static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
69
70/**
71 * vcn_v4_0_early_init - set function pointers and load microcode
72 *
73 * @handle: amdgpu_device pointer
74 *
75 * Set ring and irq function pointers
76 * Load microcode from filesystem
77 */
78static int vcn_v4_0_early_init(void *handle)
79{
80 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
81 int i;
82
83 if (amdgpu_sriov_vf(adev)) {
84 adev->vcn.harvest_config = VCN_HARVEST_MMSCH;
85 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
86 if (amdgpu_vcn_is_disabled_vcn(adev, VCN_ENCODE_RING, i)) {
87 adev->vcn.harvest_config |= 1 << i;
88 dev_info(adev->dev, "VCN%d is disabled by hypervisor\n", i);
89 }
90 }
91 }
92
93 /* re-use enc ring as unified ring */
94 adev->vcn.num_enc_rings = 1;
95
96 vcn_v4_0_set_unified_ring_funcs(adev);
97 vcn_v4_0_set_irq_funcs(adev);
98 vcn_v4_0_set_ras_funcs(adev);
99
100 return amdgpu_vcn_early_init(adev);
101}
102
103/**
104 * vcn_v4_0_sw_init - sw init for VCN block
105 *
106 * @handle: amdgpu_device pointer
107 *
108 * Load firmware and sw initialization
109 */
110static int vcn_v4_0_sw_init(void *handle)
111{
112 struct amdgpu_ring *ring;
113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
114 int i, r;
115
116 r = amdgpu_vcn_sw_init(adev);
117 if (r)
118 return r;
119
120 amdgpu_vcn_setup_ucode(adev);
121
122 r = amdgpu_vcn_resume(adev);
123 if (r)
124 return r;
125
126 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
127 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
128
129 if (adev->vcn.harvest_config & (1 << i))
130 continue;
131
132 atomic_set(&adev->vcn.inst[i].sched_score, 0);
133
134 /* VCN UNIFIED TRAP */
135 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
136 VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq);
137 if (r)
138 return r;
139
140 /* VCN POISON TRAP */
141 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i],
142 VCN_4_0__SRCID_UVD_POISON, &adev->vcn.inst[i].irq);
143 if (r)
144 return r;
145
146 ring = &adev->vcn.inst[i].ring_enc[0];
147 ring->use_doorbell = true;
148 if (amdgpu_sriov_vf(adev))
149 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + i * (adev->vcn.num_enc_rings + 1) + 1;
150 else
151 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + 8 * i;
152
153 sprintf(ring->name, "vcn_unified_%d", i);
154
155 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
156 AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
157 if (r)
158 return r;
159
160 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
161 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_FW_SHARED_FLAG_0_UNIFIED_QUEUE);
162 fw_shared->sq.is_enabled = 1;
163
164 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG);
165 fw_shared->smu_dpm_interface.smu_interface_type = (adev->flags & AMD_IS_APU) ?
166 AMDGPU_VCN_SMU_DPM_INTERFACE_APU : AMDGPU_VCN_SMU_DPM_INTERFACE_DGPU;
167
168 if (amdgpu_sriov_vf(adev))
169 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
170
171 if (amdgpu_vcnfw_log)
172 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
173 }
174
175 if (amdgpu_sriov_vf(adev)) {
176 r = amdgpu_virt_alloc_mm_table(adev);
177 if (r)
178 return r;
179 }
180
181 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
182 adev->vcn.pause_dpg_mode = vcn_v4_0_pause_dpg_mode;
183
184 return 0;
185}
186
187/**
188 * vcn_v4_0_sw_fini - sw fini for VCN block
189 *
190 * @handle: amdgpu_device pointer
191 *
192 * VCN suspend and free up sw allocation
193 */
194static int vcn_v4_0_sw_fini(void *handle)
195{
196 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
197 int i, r, idx;
198
199 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
200 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
201 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
202
203 if (adev->vcn.harvest_config & (1 << i))
204 continue;
205
206 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
207 fw_shared->present_flag_0 = 0;
208 fw_shared->sq.is_enabled = 0;
209 }
210
211 drm_dev_exit(idx);
212 }
213
214 if (amdgpu_sriov_vf(adev))
215 amdgpu_virt_free_mm_table(adev);
216
217 r = amdgpu_vcn_suspend(adev);
218 if (r)
219 return r;
220
221 r = amdgpu_vcn_sw_fini(adev);
222
223 return r;
224}
225
226/**
227 * vcn_v4_0_hw_init - start and test VCN block
228 *
229 * @handle: amdgpu_device pointer
230 *
231 * Initialize the hardware, boot up the VCPU and do some testing
232 */
233static int vcn_v4_0_hw_init(void *handle)
234{
235 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
236 struct amdgpu_ring *ring;
237 int i, r;
238
239 if (amdgpu_sriov_vf(adev)) {
240 r = vcn_v4_0_start_sriov(adev);
241 if (r)
242 goto done;
243
244 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
245 if (adev->vcn.harvest_config & (1 << i))
246 continue;
247
248 ring = &adev->vcn.inst[i].ring_enc[0];
249 ring->wptr = 0;
250 ring->wptr_old = 0;
251 vcn_v4_0_unified_ring_set_wptr(ring);
252 ring->sched.ready = true;
253
254 }
255 } else {
256 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
257 if (adev->vcn.harvest_config & (1 << i))
258 continue;
259
260 ring = &adev->vcn.inst[i].ring_enc[0];
261
262 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
263 ((adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i), i);
264
265 r = amdgpu_ring_test_helper(ring);
266 if (r)
267 goto done;
268
269 }
270 }
271
272done:
273 if (!r)
274 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
275 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
276
277 return r;
278}
279
280/**
281 * vcn_v4_0_hw_fini - stop the hardware block
282 *
283 * @handle: amdgpu_device pointer
284 *
285 * Stop the VCN block, mark ring as not ready any more
286 */
287static int vcn_v4_0_hw_fini(void *handle)
288{
289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
290 int i;
291
292 cancel_delayed_work_sync(&adev->vcn.idle_work);
293
294 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
295 if (adev->vcn.harvest_config & (1 << i))
296 continue;
297 if (!amdgpu_sriov_vf(adev)) {
298 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
299 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
300 RREG32_SOC15(VCN, i, regUVD_STATUS))) {
301 vcn_v4_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
302 }
303 }
304
305 amdgpu_irq_put(adev, &adev->vcn.inst[i].irq, 0);
306 }
307
308 return 0;
309}
310
311/**
312 * vcn_v4_0_suspend - suspend VCN block
313 *
314 * @handle: amdgpu_device pointer
315 *
316 * HW fini and suspend VCN block
317 */
318static int vcn_v4_0_suspend(void *handle)
319{
320 int r;
321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
322
323 r = vcn_v4_0_hw_fini(adev);
324 if (r)
325 return r;
326
327 r = amdgpu_vcn_suspend(adev);
328
329 return r;
330}
331
332/**
333 * vcn_v4_0_resume - resume VCN block
334 *
335 * @handle: amdgpu_device pointer
336 *
337 * Resume firmware and hw init VCN block
338 */
339static int vcn_v4_0_resume(void *handle)
340{
341 int r;
342 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
343
344 r = amdgpu_vcn_resume(adev);
345 if (r)
346 return r;
347
348 r = vcn_v4_0_hw_init(adev);
349
350 return r;
351}
352
353/**
354 * vcn_v4_0_mc_resume - memory controller programming
355 *
356 * @adev: amdgpu_device pointer
357 * @inst: instance number
358 *
359 * Let the VCN memory controller know it's offsets
360 */
361static void vcn_v4_0_mc_resume(struct amdgpu_device *adev, int inst)
362{
363 uint32_t offset, size;
364 const struct common_firmware_header *hdr;
365
366 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
367 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
368
369 /* cache window 0: fw */
370 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
371 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
372 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo));
373 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
374 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi));
375 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, 0);
376 offset = 0;
377 } else {
378 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
379 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
380 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
381 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
382 offset = size;
383 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
384 }
385 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE0, size);
386
387 /* cache window 1: stack */
388 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
389 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
390 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
391 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
392 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0);
393 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
394
395 /* cache window 2: context */
396 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
397 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
398 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
399 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
400 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET2, 0);
401 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
402
403 /* non-cache window */
404 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,
405 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
406 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,
407 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
408 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_OFFSET0, 0);
409 WREG32_SOC15(VCN, inst, regUVD_VCPU_NONCACHE_SIZE0,
410 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
411}
412
413/**
414 * vcn_v4_0_mc_resume_dpg_mode - memory controller programming for dpg mode
415 *
416 * @adev: amdgpu_device pointer
417 * @inst_idx: instance number index
418 * @indirect: indirectly write sram
419 *
420 * Let the VCN memory controller know it's offsets with dpg mode
421 */
422static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
423{
424 uint32_t offset, size;
425 const struct common_firmware_header *hdr;
426 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
427 size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
428
429 /* cache window 0: fw */
430 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
431 if (!indirect) {
432 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
433 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
434 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
435 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
436 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
437 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
438 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
439 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
440 } else {
441 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
442 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
443 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
444 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
445 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
446 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
447 }
448 offset = 0;
449 } else {
450 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
451 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
452 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
453 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
454 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
455 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
456 offset = size;
457 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
458 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0),
459 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
460 }
461
462 if (!indirect)
463 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
464 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
465 else
466 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
467 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
468
469 /* cache window 1: stack */
470 if (!indirect) {
471 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
472 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
473 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
474 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
475 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
476 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
477 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
478 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
479 } else {
480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
481 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
482 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
483 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
484 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
485 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
486 }
487 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
488 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
489
490 /* cache window 2: context */
491 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
492 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
493 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
494 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
495 VCN, inst_idx, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
496 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
498 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
499 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
500 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
501
502 /* non-cache window */
503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
504 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
505 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
507 VCN, inst_idx, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
508 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);
509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
510 VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
511 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
512 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0),
513 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);
514
515 /* VCN global tiling registers */
516 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
517 VCN, 0, regUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
518}
519
520/**
521 * vcn_v4_0_disable_static_power_gating - disable VCN static power gating
522 *
523 * @adev: amdgpu_device pointer
524 * @inst: instance number
525 *
526 * Disable static power gating for VCN block
527 */
528static void vcn_v4_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
529{
530 uint32_t data = 0;
531
532 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
533 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
534 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
535 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
536 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
537 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
538 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
539 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
540 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
541 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
542 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
543 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
544 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
545 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
546 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
547
548 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
549 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS,
550 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF);
551 } else {
552 uint32_t value;
553
554 value = (inst) ? 0x2200800 : 0;
555 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
556 | 1 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
557 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
558 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
559 | 1 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
560 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
561 | 1 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
562 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
563 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
564 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
565 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
566 | 1 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
567 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
568 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
569
570 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
571 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, value, 0x3F3FFFFF);
572 }
573
574 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
575 data &= ~0x103;
576 if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
577 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON |
578 UVD_POWER_STATUS__UVD_PG_EN_MASK;
579
580 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
581
582 return;
583}
584
585/**
586 * vcn_v4_0_enable_static_power_gating - enable VCN static power gating
587 *
588 * @adev: amdgpu_device pointer
589 * @inst: instance number
590 *
591 * Enable static power gating for VCN block
592 */
593static void vcn_v4_0_enable_static_power_gating(struct amdgpu_device *adev, int inst)
594{
595 uint32_t data;
596
597 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
598 /* Before power off, this indicator has to be turned on */
599 data = RREG32_SOC15(VCN, inst, regUVD_POWER_STATUS);
600 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
601 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
602 WREG32_SOC15(VCN, inst, regUVD_POWER_STATUS, data);
603
604 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
605 | 2 << UVD_PGFSM_CONFIG__UVDS_PWR_CONFIG__SHIFT
606 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
607 | 2 << UVD_PGFSM_CONFIG__UVDTC_PWR_CONFIG__SHIFT
608 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
609 | 2 << UVD_PGFSM_CONFIG__UVDTA_PWR_CONFIG__SHIFT
610 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT
611 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
612 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
613 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
614 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT
615 | 2 << UVD_PGFSM_CONFIG__UVDTB_PWR_CONFIG__SHIFT
616 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT
617 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT);
618 WREG32_SOC15(VCN, inst, regUVD_PGFSM_CONFIG, data);
619
620 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
621 | 2 << UVD_PGFSM_STATUS__UVDS_PWR_STATUS__SHIFT
622 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
623 | 2 << UVD_PGFSM_STATUS__UVDTC_PWR_STATUS__SHIFT
624 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
625 | 2 << UVD_PGFSM_STATUS__UVDTA_PWR_STATUS__SHIFT
626 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT
627 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
628 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
629 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
630 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT
631 | 2 << UVD_PGFSM_STATUS__UVDTB_PWR_STATUS__SHIFT
632 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT
633 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT);
634 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF);
635 }
636
637 return;
638}
639
640/**
641 * vcn_v4_0_disable_clock_gating - disable VCN clock gating
642 *
643 * @adev: amdgpu_device pointer
644 * @inst: instance number
645 *
646 * Disable clock gating for VCN block
647 */
648static void vcn_v4_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
649{
650 uint32_t data;
651
652 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
653 return;
654
655 /* VCN disable CGC */
656 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
657 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
658 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
659 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
660 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
661
662 data = RREG32_SOC15(VCN, inst, regUVD_CGC_GATE);
663 data &= ~(UVD_CGC_GATE__SYS_MASK
664 | UVD_CGC_GATE__UDEC_MASK
665 | UVD_CGC_GATE__MPEG2_MASK
666 | UVD_CGC_GATE__REGS_MASK
667 | UVD_CGC_GATE__RBC_MASK
668 | UVD_CGC_GATE__LMI_MC_MASK
669 | UVD_CGC_GATE__LMI_UMC_MASK
670 | UVD_CGC_GATE__IDCT_MASK
671 | UVD_CGC_GATE__MPRD_MASK
672 | UVD_CGC_GATE__MPC_MASK
673 | UVD_CGC_GATE__LBSI_MASK
674 | UVD_CGC_GATE__LRBBM_MASK
675 | UVD_CGC_GATE__UDEC_RE_MASK
676 | UVD_CGC_GATE__UDEC_CM_MASK
677 | UVD_CGC_GATE__UDEC_IT_MASK
678 | UVD_CGC_GATE__UDEC_DB_MASK
679 | UVD_CGC_GATE__UDEC_MP_MASK
680 | UVD_CGC_GATE__WCB_MASK
681 | UVD_CGC_GATE__VCPU_MASK
682 | UVD_CGC_GATE__MMSCH_MASK);
683
684 WREG32_SOC15(VCN, inst, regUVD_CGC_GATE, data);
685 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF);
686
687 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
688 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
689 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
690 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
691 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
692 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
693 | UVD_CGC_CTRL__SYS_MODE_MASK
694 | UVD_CGC_CTRL__UDEC_MODE_MASK
695 | UVD_CGC_CTRL__MPEG2_MODE_MASK
696 | UVD_CGC_CTRL__REGS_MODE_MASK
697 | UVD_CGC_CTRL__RBC_MODE_MASK
698 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
699 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
700 | UVD_CGC_CTRL__IDCT_MODE_MASK
701 | UVD_CGC_CTRL__MPRD_MODE_MASK
702 | UVD_CGC_CTRL__MPC_MODE_MASK
703 | UVD_CGC_CTRL__LBSI_MODE_MASK
704 | UVD_CGC_CTRL__LRBBM_MODE_MASK
705 | UVD_CGC_CTRL__WCB_MODE_MASK
706 | UVD_CGC_CTRL__VCPU_MODE_MASK
707 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
708 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
709
710 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE);
711 data |= (UVD_SUVD_CGC_GATE__SRE_MASK
712 | UVD_SUVD_CGC_GATE__SIT_MASK
713 | UVD_SUVD_CGC_GATE__SMP_MASK
714 | UVD_SUVD_CGC_GATE__SCM_MASK
715 | UVD_SUVD_CGC_GATE__SDB_MASK
716 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
717 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
718 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
719 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
720 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
721 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
722 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
723 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
724 | UVD_SUVD_CGC_GATE__SCLR_MASK
725 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
726 | UVD_SUVD_CGC_GATE__ENT_MASK
727 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
728 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
729 | UVD_SUVD_CGC_GATE__SITE_MASK
730 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
731 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
732 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
733 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
734 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
735 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_GATE, data);
736
737 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
738 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
739 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
740 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
741 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
742 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
743 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
744 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
745 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
746 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
747 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
748 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
749}
750
751/**
752 * vcn_v4_0_disable_clock_gating_dpg_mode - disable VCN clock gating dpg mode
753 *
754 * @adev: amdgpu_device pointer
755 * @sram_sel: sram select
756 * @inst_idx: instance number index
757 * @indirect: indirectly write sram
758 *
759 * Disable clock gating for VCN block with dpg mode
760 */
761static void vcn_v4_0_disable_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel,
762 int inst_idx, uint8_t indirect)
763{
764 uint32_t reg_data = 0;
765
766 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
767 return;
768
769 /* enable sw clock gating control */
770 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
771 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
772 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
773 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
774 UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
775 UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
776 UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
777 UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
778 UVD_CGC_CTRL__SYS_MODE_MASK |
779 UVD_CGC_CTRL__UDEC_MODE_MASK |
780 UVD_CGC_CTRL__MPEG2_MODE_MASK |
781 UVD_CGC_CTRL__REGS_MODE_MASK |
782 UVD_CGC_CTRL__RBC_MODE_MASK |
783 UVD_CGC_CTRL__LMI_MC_MODE_MASK |
784 UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
785 UVD_CGC_CTRL__IDCT_MODE_MASK |
786 UVD_CGC_CTRL__MPRD_MODE_MASK |
787 UVD_CGC_CTRL__MPC_MODE_MASK |
788 UVD_CGC_CTRL__LBSI_MODE_MASK |
789 UVD_CGC_CTRL__LRBBM_MODE_MASK |
790 UVD_CGC_CTRL__WCB_MODE_MASK |
791 UVD_CGC_CTRL__VCPU_MODE_MASK);
792 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
793 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
794
795 /* turn off clock gating */
796 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
797 VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);
798
799 /* turn on SUVD clock gating */
800 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
801 VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
802
803 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
804 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
805 VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
806}
807
808/**
809 * vcn_v4_0_enable_clock_gating - enable VCN clock gating
810 *
811 * @adev: amdgpu_device pointer
812 * @inst: instance number
813 *
814 * Enable clock gating for VCN block
815 */
816static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
817{
818 uint32_t data;
819
820 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
821 return;
822
823 /* enable VCN CGC */
824 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
825 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
826 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
827 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
828 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
829
830 data = RREG32_SOC15(VCN, inst, regUVD_CGC_CTRL);
831 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
832 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
833 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
834 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
835 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
836 | UVD_CGC_CTRL__SYS_MODE_MASK
837 | UVD_CGC_CTRL__UDEC_MODE_MASK
838 | UVD_CGC_CTRL__MPEG2_MODE_MASK
839 | UVD_CGC_CTRL__REGS_MODE_MASK
840 | UVD_CGC_CTRL__RBC_MODE_MASK
841 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
842 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
843 | UVD_CGC_CTRL__IDCT_MODE_MASK
844 | UVD_CGC_CTRL__MPRD_MODE_MASK
845 | UVD_CGC_CTRL__MPC_MODE_MASK
846 | UVD_CGC_CTRL__LBSI_MODE_MASK
847 | UVD_CGC_CTRL__LRBBM_MODE_MASK
848 | UVD_CGC_CTRL__WCB_MODE_MASK
849 | UVD_CGC_CTRL__VCPU_MODE_MASK
850 | UVD_CGC_CTRL__MMSCH_MODE_MASK);
851 WREG32_SOC15(VCN, inst, regUVD_CGC_CTRL, data);
852
853 data = RREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL);
854 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
855 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
856 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
857 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
858 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
859 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
860 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
861 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
862 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
863 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
864 WREG32_SOC15(VCN, inst, regUVD_SUVD_CGC_CTRL, data);
865
866 return;
867}
868
869static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
870 bool indirect)
871{
872 uint32_t tmp;
873
874 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
875 return;
876
877 tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
878 VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
879 VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
880 VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
881 WREG32_SOC15_DPG_MODE(inst_idx,
882 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
883 tmp, 0, indirect);
884
885 tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
886 WREG32_SOC15_DPG_MODE(inst_idx,
887 SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
888 tmp, 0, indirect);
889}
890
891/**
892 * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
893 *
894 * @adev: amdgpu_device pointer
895 * @inst_idx: instance number index
896 * @indirect: indirectly write sram
897 *
898 * Start VCN block with dpg mode
899 */
900static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
901{
902 volatile struct amdgpu_vcn4_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
903 struct amdgpu_ring *ring;
904 uint32_t tmp;
905
906 /* disable register anti-hang mechanism */
907 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 1,
908 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
909 /* enable dynamic power gating mode */
910 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS);
911 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
912 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
913 WREG32_SOC15(VCN, inst_idx, regUVD_POWER_STATUS, tmp);
914
915 if (indirect)
916 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
917
918 /* enable clock gating */
919 vcn_v4_0_disable_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
920
921 /* enable VCPU clock */
922 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
923 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK;
924 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
925 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
926
927 /* disable master interupt */
928 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
929 VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);
930
931 /* setup regUVD_LMI_CTRL */
932 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
933 UVD_LMI_CTRL__REQ_MODE_MASK |
934 UVD_LMI_CTRL__CRC_RESET_MASK |
935 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
936 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
937 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
938 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
939 0x00100000L);
940 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
941 VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);
942
943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
944 VCN, inst_idx, regUVD_MPC_CNTL),
945 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
946
947 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
948 VCN, inst_idx, regUVD_MPC_SET_MUXA0),
949 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
950 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
951 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
952 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
953
954 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
955 VCN, inst_idx, regUVD_MPC_SET_MUXB0),
956 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
957 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
958 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
959 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
960
961 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
962 VCN, inst_idx, regUVD_MPC_SET_MUX),
963 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
964 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
965 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
966
967 vcn_v4_0_mc_resume_dpg_mode(adev, inst_idx, indirect);
968
969 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
970 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
972 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);
973
974 /* enable LMI MC and UMC channels */
975 tmp = 0x1f << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT;
976 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
977 VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
978
979 vcn_v4_0_enable_ras(adev, inst_idx, indirect);
980
981 /* enable master interrupt */
982 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
983 VCN, inst_idx, regUVD_MASTINT_EN),
984 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
985
986
987 if (indirect)
988 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
989 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
990 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
991
992 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
993
994 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_LO, ring->gpu_addr);
995 WREG32_SOC15(VCN, inst_idx, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
996 WREG32_SOC15(VCN, inst_idx, regUVD_RB_SIZE, ring->ring_size / 4);
997
998 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
999 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1000 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1001 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1002 WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
1003 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
1004
1005 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
1006 WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
1007 ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1008
1009 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE);
1010 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1011 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp);
1012 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1013
1014 WREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL,
1015 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1016 VCN_RB1_DB_CTRL__EN_MASK);
1017
1018 return 0;
1019}
1020
1021
1022/**
1023 * vcn_v4_0_start - VCN start
1024 *
1025 * @adev: amdgpu_device pointer
1026 *
1027 * Start VCN block
1028 */
1029static int vcn_v4_0_start(struct amdgpu_device *adev)
1030{
1031 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1032 struct amdgpu_ring *ring;
1033 uint32_t tmp;
1034 int i, j, k, r;
1035
1036 if (adev->pm.dpm_enabled)
1037 amdgpu_dpm_enable_uvd(adev, true);
1038
1039 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1040 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1041
1042 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1043 r = vcn_v4_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
1044 continue;
1045 }
1046
1047 /* disable VCN power gating */
1048 vcn_v4_0_disable_static_power_gating(adev, i);
1049
1050 /* set VCN status busy */
1051 tmp = RREG32_SOC15(VCN, i, regUVD_STATUS) | UVD_STATUS__UVD_BUSY;
1052 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp);
1053
1054 /*SW clock gating */
1055 vcn_v4_0_disable_clock_gating(adev, i);
1056
1057 /* enable VCPU clock */
1058 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1059 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK);
1060
1061 /* disable master interrupt */
1062 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN), 0,
1063 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1064
1065 /* enable LMI MC and UMC channels */
1066 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_LMI_CTRL2), 0,
1067 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1068
1069 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1070 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1071 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1072 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1073
1074 /* setup regUVD_LMI_CTRL */
1075 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL);
1076 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL, tmp |
1077 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1078 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1079 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1080 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
1081
1082 /* setup regUVD_MPC_CNTL */
1083 tmp = RREG32_SOC15(VCN, i, regUVD_MPC_CNTL);
1084 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
1085 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
1086 WREG32_SOC15(VCN, i, regUVD_MPC_CNTL, tmp);
1087
1088 /* setup UVD_MPC_SET_MUXA0 */
1089 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXA0,
1090 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1091 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1092 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1093 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
1094
1095 /* setup UVD_MPC_SET_MUXB0 */
1096 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUXB0,
1097 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1098 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1099 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1100 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
1101
1102 /* setup UVD_MPC_SET_MUX */
1103 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX,
1104 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1105 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1106 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
1107
1108 vcn_v4_0_mc_resume(adev, i);
1109
1110 /* VCN global tiling registers */
1111 WREG32_SOC15(VCN, i, regUVD_GFX10_ADDR_CONFIG,
1112 adev->gfx.config.gb_addr_config);
1113
1114 /* unblock VCPU register access */
1115 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL), 0,
1116 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1117
1118 /* release VCPU reset to boot */
1119 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1120 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1121
1122 for (j = 0; j < 10; ++j) {
1123 uint32_t status;
1124
1125 for (k = 0; k < 100; ++k) {
1126 status = RREG32_SOC15(VCN, i, regUVD_STATUS);
1127 if (status & 2)
1128 break;
1129 mdelay(10);
1130 if (amdgpu_emu_mode==1)
1131 msleep(1);
1132 }
1133
1134 if (amdgpu_emu_mode==1) {
1135 r = -1;
1136 if (status & 2) {
1137 r = 0;
1138 break;
1139 }
1140 } else {
1141 r = 0;
1142 if (status & 2)
1143 break;
1144
1145 dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
1146 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1147 UVD_VCPU_CNTL__BLK_RST_MASK,
1148 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1149 mdelay(10);
1150 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1151 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1152
1153 mdelay(10);
1154 r = -1;
1155 }
1156 }
1157
1158 if (r) {
1159 dev_err(adev->dev, "VCN[%d] is not responding, giving up!!!\n", i);
1160 return r;
1161 }
1162
1163 /* enable master interrupt */
1164 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_MASTINT_EN),
1165 UVD_MASTINT_EN__VCPU_EN_MASK,
1166 ~UVD_MASTINT_EN__VCPU_EN_MASK);
1167
1168 /* clear the busy bit of VCN_STATUS */
1169 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_STATUS), 0,
1170 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1171
1172 ring = &adev->vcn.inst[i].ring_enc[0];
1173 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL,
1174 ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
1175 VCN_RB1_DB_CTRL__EN_MASK);
1176
1177 WREG32_SOC15(VCN, i, regUVD_RB_BASE_LO, ring->gpu_addr);
1178 WREG32_SOC15(VCN, i, regUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1179 WREG32_SOC15(VCN, i, regUVD_RB_SIZE, ring->ring_size / 4);
1180
1181 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1182 tmp &= ~(VCN_RB_ENABLE__RB1_EN_MASK);
1183 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1184 fw_shared->sq.queue_mode |= FW_QUEUE_RING_RESET;
1185 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0);
1186 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0);
1187
1188 tmp = RREG32_SOC15(VCN, i, regUVD_RB_RPTR);
1189 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, tmp);
1190 ring->wptr = RREG32_SOC15(VCN, i, regUVD_RB_WPTR);
1191
1192 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
1193 tmp |= VCN_RB_ENABLE__RB1_EN_MASK;
1194 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
1195 fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);
1196 }
1197
1198 return 0;
1199}
1200
1201static int vcn_v4_0_start_sriov(struct amdgpu_device *adev)
1202{
1203 int i;
1204 struct amdgpu_ring *ring_enc;
1205 uint64_t cache_addr;
1206 uint64_t rb_enc_addr;
1207 uint64_t ctx_addr;
1208 uint32_t param, resp, expected;
1209 uint32_t offset, cache_size;
1210 uint32_t tmp, timeout;
1211
1212 struct amdgpu_mm_table *table = &adev->virt.mm_table;
1213 uint32_t *table_loc;
1214 uint32_t table_size;
1215 uint32_t size, size_dw;
1216 uint32_t init_status;
1217 uint32_t enabled_vcn;
1218
1219 struct mmsch_v4_0_cmd_direct_write
1220 direct_wt = { {0} };
1221 struct mmsch_v4_0_cmd_direct_read_modify_write
1222 direct_rd_mod_wt = { {0} };
1223 struct mmsch_v4_0_cmd_end end = { {0} };
1224 struct mmsch_v4_0_init_header header;
1225
1226 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1227 volatile struct amdgpu_fw_shared_rb_setup *rb_setup;
1228
1229 direct_wt.cmd_header.command_type =
1230 MMSCH_COMMAND__DIRECT_REG_WRITE;
1231 direct_rd_mod_wt.cmd_header.command_type =
1232 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1233 end.cmd_header.command_type =
1234 MMSCH_COMMAND__END;
1235
1236 header.version = MMSCH_VERSION;
1237 header.total_size = sizeof(struct mmsch_v4_0_init_header) >> 2;
1238 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) {
1239 header.inst[i].init_status = 0;
1240 header.inst[i].table_offset = 0;
1241 header.inst[i].table_size = 0;
1242 }
1243
1244 table_loc = (uint32_t *)table->cpu_addr;
1245 table_loc += header.total_size;
1246 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1247 if (adev->vcn.harvest_config & (1 << i))
1248 continue;
1249
1250 table_size = 0;
1251
1252 MMSCH_V4_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,
1253 regUVD_STATUS),
1254 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY);
1255
1256 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
1257
1258 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1259 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1260 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1261 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
1262 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1263 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1264 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
1265 offset = 0;
1266 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1267 regUVD_VCPU_CACHE_OFFSET0),
1268 0);
1269 } else {
1270 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1271 regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
1272 lower_32_bits(adev->vcn.inst[i].gpu_addr));
1273 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1274 regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
1275 upper_32_bits(adev->vcn.inst[i].gpu_addr));
1276 offset = cache_size;
1277 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1278 regUVD_VCPU_CACHE_OFFSET0),
1279 AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
1280 }
1281
1282 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1283 regUVD_VCPU_CACHE_SIZE0),
1284 cache_size);
1285
1286 cache_addr = adev->vcn.inst[i].gpu_addr + offset;
1287 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1288 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
1289 lower_32_bits(cache_addr));
1290 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1291 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
1292 upper_32_bits(cache_addr));
1293 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1294 regUVD_VCPU_CACHE_OFFSET1),
1295 0);
1296 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1297 regUVD_VCPU_CACHE_SIZE1),
1298 AMDGPU_VCN_STACK_SIZE);
1299
1300 cache_addr = adev->vcn.inst[i].gpu_addr + offset +
1301 AMDGPU_VCN_STACK_SIZE;
1302 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1303 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
1304 lower_32_bits(cache_addr));
1305 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1306 regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
1307 upper_32_bits(cache_addr));
1308 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1309 regUVD_VCPU_CACHE_OFFSET2),
1310 0);
1311 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1312 regUVD_VCPU_CACHE_SIZE2),
1313 AMDGPU_VCN_CONTEXT_SIZE);
1314
1315 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1316 rb_setup = &fw_shared->rb_setup;
1317
1318 ring_enc = &adev->vcn.inst[i].ring_enc[0];
1319 ring_enc->wptr = 0;
1320 rb_enc_addr = ring_enc->gpu_addr;
1321
1322 rb_setup->is_rb_enabled_flags |= RB_ENABLED;
1323 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr);
1324 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr);
1325 rb_setup->rb_size = ring_enc->ring_size / 4;
1326 fw_shared->present_flag_0 |= cpu_to_le32(AMDGPU_VCN_VF_RB_SETUP_FLAG);
1327
1328 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1329 regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
1330 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1331 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1332 regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
1333 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
1334 MMSCH_V4_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
1335 regUVD_VCPU_NONCACHE_SIZE0),
1336 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)));
1337
1338 /* add end packet */
1339 MMSCH_V4_0_INSERT_END();
1340
1341 /* refine header */
1342 header.inst[i].init_status = 0;
1343 header.inst[i].table_offset = header.total_size;
1344 header.inst[i].table_size = table_size;
1345 header.total_size += table_size;
1346 }
1347
1348 /* Update init table header in memory */
1349 size = sizeof(struct mmsch_v4_0_init_header);
1350 table_loc = (uint32_t *)table->cpu_addr;
1351 memcpy((void *)table_loc, &header, size);
1352
1353 /* message MMSCH (in VCN[0]) to initialize this client
1354 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr
1355 * of memory descriptor location
1356 */
1357 ctx_addr = table->gpu_addr;
1358 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr));
1359 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr));
1360
1361 /* 2, update vmid of descriptor */
1362 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID);
1363 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK;
1364 /* use domain0 for MM scheduler */
1365 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT);
1366 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp);
1367
1368 /* 3, notify mmsch about the size of this descriptor */
1369 size = header.total_size;
1370 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size);
1371
1372 /* 4, set resp to zero */
1373 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0);
1374
1375 /* 5, kick off the initialization and wait until
1376 * MMSCH_VF_MAILBOX_RESP becomes non-zero
1377 */
1378 param = 0x00000001;
1379 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param);
1380 tmp = 0;
1381 timeout = 1000;
1382 resp = 0;
1383 expected = MMSCH_VF_MAILBOX_RESP__OK;
1384 while (resp != expected) {
1385 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP);
1386 if (resp != 0)
1387 break;
1388
1389 udelay(10);
1390 tmp = tmp + 10;
1391 if (tmp >= timeout) {
1392 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\
1393 " waiting for regMMSCH_VF_MAILBOX_RESP "\
1394 "(expected=0x%08x, readback=0x%08x)\n",
1395 tmp, expected, resp);
1396 return -EBUSY;
1397 }
1398 }
1399 enabled_vcn = amdgpu_vcn_is_disabled_vcn(adev, VCN_DECODE_RING, 0) ? 1 : 0;
1400 init_status = ((struct mmsch_v4_0_init_header *)(table_loc))->inst[enabled_vcn].init_status;
1401 if (resp != expected && resp != MMSCH_VF_MAILBOX_RESP__INCOMPLETE
1402 && init_status != MMSCH_VF_ENGINE_STATUS__PASS)
1403 DRM_ERROR("MMSCH init status is incorrect! readback=0x%08x, header init "\
1404 "status for VCN%x: 0x%x\n", resp, enabled_vcn, init_status);
1405
1406 return 0;
1407}
1408
1409/**
1410 * vcn_v4_0_stop_dpg_mode - VCN stop with dpg mode
1411 *
1412 * @adev: amdgpu_device pointer
1413 * @inst_idx: instance number index
1414 *
1415 * Stop VCN block with dpg mode
1416 */
1417static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1418{
1419 uint32_t tmp;
1420
1421 /* Wait for power status to be 1 */
1422 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1423 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1424
1425 /* wait for read ptr to be equal to write ptr */
1426 tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
1427 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1428
1429 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
1430 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1431
1432 /* disable dynamic power gating mode */
1433 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, regUVD_POWER_STATUS), 0,
1434 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1435}
1436
1437/**
1438 * vcn_v4_0_stop - VCN stop
1439 *
1440 * @adev: amdgpu_device pointer
1441 *
1442 * Stop VCN block
1443 */
1444static int vcn_v4_0_stop(struct amdgpu_device *adev)
1445{
1446 volatile struct amdgpu_vcn4_fw_shared *fw_shared;
1447 uint32_t tmp;
1448 int i, r = 0;
1449
1450 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1451 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1452 fw_shared->sq.queue_mode |= FW_QUEUE_DPG_HOLD_OFF;
1453
1454 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1455 vcn_v4_0_stop_dpg_mode(adev, i);
1456 continue;
1457 }
1458
1459 /* wait for vcn idle */
1460 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1461 if (r)
1462 return r;
1463
1464 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1465 UVD_LMI_STATUS__READ_CLEAN_MASK |
1466 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1467 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1468 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1469 if (r)
1470 return r;
1471
1472 /* disable LMI UMC channel */
1473 tmp = RREG32_SOC15(VCN, i, regUVD_LMI_CTRL2);
1474 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK;
1475 WREG32_SOC15(VCN, i, regUVD_LMI_CTRL2, tmp);
1476 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1477 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1478 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp);
1479 if (r)
1480 return r;
1481
1482 /* block VCPU register access */
1483 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_RB_ARB_CTRL),
1484 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,
1485 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK);
1486
1487 /* reset VCPU */
1488 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
1489 UVD_VCPU_CNTL__BLK_RST_MASK,
1490 ~UVD_VCPU_CNTL__BLK_RST_MASK);
1491
1492 /* disable VCPU clock */
1493 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
1494 ~(UVD_VCPU_CNTL__CLK_EN_MASK));
1495
1496 /* apply soft reset */
1497 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1498 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
1499 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1500 tmp = RREG32_SOC15(VCN, i, regUVD_SOFT_RESET);
1501 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
1502 WREG32_SOC15(VCN, i, regUVD_SOFT_RESET, tmp);
1503
1504 /* clear status */
1505 WREG32_SOC15(VCN, i, regUVD_STATUS, 0);
1506
1507 /* apply HW clock gating */
1508 vcn_v4_0_enable_clock_gating(adev, i);
1509
1510 /* enable VCN power gating */
1511 vcn_v4_0_enable_static_power_gating(adev, i);
1512 }
1513
1514 if (adev->pm.dpm_enabled)
1515 amdgpu_dpm_enable_uvd(adev, false);
1516
1517 return 0;
1518}
1519
1520/**
1521 * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
1522 *
1523 * @adev: amdgpu_device pointer
1524 * @inst_idx: instance number index
1525 * @new_state: pause state
1526 *
1527 * Pause dpg mode for VCN block
1528 */
1529static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
1530 struct dpg_pause_state *new_state)
1531{
1532 uint32_t reg_data = 0;
1533 int ret_code;
1534
1535 /* pause/unpause if state is changed */
1536 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1537 DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d",
1538 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based);
1539 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) &
1540 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1541
1542 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1543 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 0x1,
1544 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1545
1546 if (!ret_code) {
1547 /* pause DPG */
1548 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1549 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1550
1551 /* wait for ACK */
1552 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE,
1553 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1554 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1555
1556 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS,
1557 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1558 }
1559 } else {
1560 /* unpause dpg, no need to wait */
1561 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1562 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data);
1563 }
1564 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1565 }
1566
1567 return 0;
1568}
1569
1570/**
1571 * vcn_v4_0_unified_ring_get_rptr - get unified read pointer
1572 *
1573 * @ring: amdgpu_ring pointer
1574 *
1575 * Returns the current hardware unified read pointer
1576 */
1577static uint64_t vcn_v4_0_unified_ring_get_rptr(struct amdgpu_ring *ring)
1578{
1579 struct amdgpu_device *adev = ring->adev;
1580
1581 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1582 DRM_ERROR("wrong ring id is identified in %s", __func__);
1583
1584 return RREG32_SOC15(VCN, ring->me, regUVD_RB_RPTR);
1585}
1586
1587/**
1588 * vcn_v4_0_unified_ring_get_wptr - get unified write pointer
1589 *
1590 * @ring: amdgpu_ring pointer
1591 *
1592 * Returns the current hardware unified write pointer
1593 */
1594static uint64_t vcn_v4_0_unified_ring_get_wptr(struct amdgpu_ring *ring)
1595{
1596 struct amdgpu_device *adev = ring->adev;
1597
1598 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1599 DRM_ERROR("wrong ring id is identified in %s", __func__);
1600
1601 if (ring->use_doorbell)
1602 return *ring->wptr_cpu_addr;
1603 else
1604 return RREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR);
1605}
1606
1607/**
1608 * vcn_v4_0_unified_ring_set_wptr - set enc write pointer
1609 *
1610 * @ring: amdgpu_ring pointer
1611 *
1612 * Commits the enc write pointer to the hardware
1613 */
1614static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring)
1615{
1616 struct amdgpu_device *adev = ring->adev;
1617
1618 if (ring != &adev->vcn.inst[ring->me].ring_enc[0])
1619 DRM_ERROR("wrong ring id is identified in %s", __func__);
1620
1621 if (ring->use_doorbell) {
1622 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
1623 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
1624 } else {
1625 WREG32_SOC15(VCN, ring->me, regUVD_RB_WPTR, lower_32_bits(ring->wptr));
1626 }
1627}
1628
1629static int vcn_v4_0_limit_sched(struct amdgpu_cs_parser *p,
1630 struct amdgpu_job *job)
1631{
1632 struct drm_gpu_scheduler **scheds;
1633
1634 /* The create msg must be in the first IB submitted */
1635 if (atomic_read(&job->base.entity->fence_seq))
1636 return -EINVAL;
1637
1638 /* if VCN0 is harvested, we can't support AV1 */
1639 if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)
1640 return -EINVAL;
1641
1642 scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC]
1643 [AMDGPU_RING_PRIO_0].sched;
1644 drm_sched_entity_modify_sched(job->base.entity, scheds, 1);
1645 return 0;
1646}
1647
1648static int vcn_v4_0_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
1649 uint64_t addr)
1650{
1651 struct ttm_operation_ctx ctx = { false, false };
1652 struct amdgpu_bo_va_mapping *map;
1653 uint32_t *msg, num_buffers;
1654 struct amdgpu_bo *bo;
1655 uint64_t start, end;
1656 unsigned int i;
1657 void *ptr;
1658 int r;
1659
1660 addr &= AMDGPU_GMC_HOLE_MASK;
1661 r = amdgpu_cs_find_mapping(p, addr, &bo, &map);
1662 if (r) {
1663 DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr);
1664 return r;
1665 }
1666
1667 start = map->start * AMDGPU_GPU_PAGE_SIZE;
1668 end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE;
1669 if (addr & 0x7) {
1670 DRM_ERROR("VCN messages must be 8 byte aligned!\n");
1671 return -EINVAL;
1672 }
1673
1674 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1675 amdgpu_bo_placement_from_domain(bo, bo->allowed_domains);
1676 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1677 if (r) {
1678 DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r);
1679 return r;
1680 }
1681
1682 r = amdgpu_bo_kmap(bo, &ptr);
1683 if (r) {
1684 DRM_ERROR("Failed mapping the VCN message (%d)!\n", r);
1685 return r;
1686 }
1687
1688 msg = ptr + addr - start;
1689
1690 /* Check length */
1691 if (msg[1] > end - addr) {
1692 r = -EINVAL;
1693 goto out;
1694 }
1695
1696 if (msg[3] != RDECODE_MSG_CREATE)
1697 goto out;
1698
1699 num_buffers = msg[2];
1700 for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) {
1701 uint32_t offset, size, *create;
1702
1703 if (msg[0] != RDECODE_MESSAGE_CREATE)
1704 continue;
1705
1706 offset = msg[1];
1707 size = msg[2];
1708
1709 if (offset + size > end) {
1710 r = -EINVAL;
1711 goto out;
1712 }
1713
1714 create = ptr + addr + offset - start;
1715
1716 /* H264, HEVC and VP9 can run on any instance */
1717 if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11)
1718 continue;
1719
1720 r = vcn_v4_0_limit_sched(p, job);
1721 if (r)
1722 goto out;
1723 }
1724
1725out:
1726 amdgpu_bo_kunmap(bo);
1727 return r;
1728}
1729
1730#define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002)
1731#define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003)
1732
1733#define RADEON_VCN_ENGINE_INFO (0x30000001)
1734#define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16
1735
1736#define RENCODE_ENCODE_STANDARD_AV1 2
1737#define RENCODE_IB_PARAM_SESSION_INIT 0x00000003
1738#define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64
1739
1740/* return the offset in ib if id is found, -1 otherwise
1741 * to speed up the searching we only search upto max_offset
1742 */
1743static int vcn_v4_0_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset)
1744{
1745 int i;
1746
1747 for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) {
1748 if (ib->ptr[i + 1] == id)
1749 return i;
1750 }
1751 return -1;
1752}
1753
1754static int vcn_v4_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1755 struct amdgpu_job *job,
1756 struct amdgpu_ib *ib)
1757{
1758 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1759 struct amdgpu_vcn_decode_buffer *decode_buffer;
1760 uint64_t addr;
1761 uint32_t val;
1762 int idx;
1763
1764 /* The first instance can decode anything */
1765 if (!ring->me)
1766 return 0;
1767
1768 /* RADEON_VCN_ENGINE_INFO is at the top of ib block */
1769 idx = vcn_v4_0_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO,
1770 RADEON_VCN_ENGINE_INFO_MAX_OFFSET);
1771 if (idx < 0) /* engine info is missing */
1772 return 0;
1773
1774 val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
1775 if (val == RADEON_VCN_ENGINE_TYPE_DECODE) {
1776 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6];
1777
1778 if (!(decode_buffer->valid_buf_flag & 0x1))
1779 return 0;
1780
1781 addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 |
1782 decode_buffer->msg_buffer_address_lo;
1783 return vcn_v4_0_dec_msg(p, job, addr);
1784 } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) {
1785 idx = vcn_v4_0_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT,
1786 RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET);
1787 if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1)
1788 return vcn_v4_0_limit_sched(p, job);
1789 }
1790 return 0;
1791}
1792
1793static const struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = {
1794 .type = AMDGPU_RING_TYPE_VCN_ENC,
1795 .align_mask = 0x3f,
1796 .nop = VCN_ENC_CMD_NO_OP,
1797 .vmhub = AMDGPU_MMHUB_0,
1798 .get_rptr = vcn_v4_0_unified_ring_get_rptr,
1799 .get_wptr = vcn_v4_0_unified_ring_get_wptr,
1800 .set_wptr = vcn_v4_0_unified_ring_set_wptr,
1801 .patch_cs_in_place = vcn_v4_0_ring_patch_cs_in_place,
1802 .emit_frame_size =
1803 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1804 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1805 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1806 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1807 1, /* vcn_v2_0_enc_ring_insert_end */
1808 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1809 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1810 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1811 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1812 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1813 .test_ib = amdgpu_vcn_unified_ring_test_ib,
1814 .insert_nop = amdgpu_ring_insert_nop,
1815 .insert_end = vcn_v2_0_enc_ring_insert_end,
1816 .pad_ib = amdgpu_ring_generic_pad_ib,
1817 .begin_use = amdgpu_vcn_ring_begin_use,
1818 .end_use = amdgpu_vcn_ring_end_use,
1819 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1820 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1821 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1822};
1823
1824/**
1825 * vcn_v4_0_set_unified_ring_funcs - set unified ring functions
1826 *
1827 * @adev: amdgpu_device pointer
1828 *
1829 * Set unified ring functions
1830 */
1831static void vcn_v4_0_set_unified_ring_funcs(struct amdgpu_device *adev)
1832{
1833 int i;
1834
1835 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1836 if (adev->vcn.harvest_config & (1 << i))
1837 continue;
1838
1839 adev->vcn.inst[i].ring_enc[0].funcs = &vcn_v4_0_unified_ring_vm_funcs;
1840 adev->vcn.inst[i].ring_enc[0].me = i;
1841
1842 DRM_INFO("VCN(%d) encode/decode are enabled in VM mode\n", i);
1843 }
1844}
1845
1846/**
1847 * vcn_v4_0_is_idle - check VCN block is idle
1848 *
1849 * @handle: amdgpu_device pointer
1850 *
1851 * Check whether VCN block is idle
1852 */
1853static bool vcn_v4_0_is_idle(void *handle)
1854{
1855 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1856 int i, ret = 1;
1857
1858 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1859 if (adev->vcn.harvest_config & (1 << i))
1860 continue;
1861
1862 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE);
1863 }
1864
1865 return ret;
1866}
1867
1868/**
1869 * vcn_v4_0_wait_for_idle - wait for VCN block idle
1870 *
1871 * @handle: amdgpu_device pointer
1872 *
1873 * Wait for VCN block idle
1874 */
1875static int vcn_v4_0_wait_for_idle(void *handle)
1876{
1877 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1878 int i, ret = 0;
1879
1880 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1881 if (adev->vcn.harvest_config & (1 << i))
1882 continue;
1883
1884 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE,
1885 UVD_STATUS__IDLE);
1886 if (ret)
1887 return ret;
1888 }
1889
1890 return ret;
1891}
1892
1893/**
1894 * vcn_v4_0_set_clockgating_state - set VCN block clockgating state
1895 *
1896 * @handle: amdgpu_device pointer
1897 * @state: clock gating state
1898 *
1899 * Set VCN block clockgating state
1900 */
1901static int vcn_v4_0_set_clockgating_state(void *handle, enum amd_clockgating_state state)
1902{
1903 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1904 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1905 int i;
1906
1907 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1908 if (adev->vcn.harvest_config & (1 << i))
1909 continue;
1910
1911 if (enable) {
1912 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE)
1913 return -EBUSY;
1914 vcn_v4_0_enable_clock_gating(adev, i);
1915 } else {
1916 vcn_v4_0_disable_clock_gating(adev, i);
1917 }
1918 }
1919
1920 return 0;
1921}
1922
1923/**
1924 * vcn_v4_0_set_powergating_state - set VCN block powergating state
1925 *
1926 * @handle: amdgpu_device pointer
1927 * @state: power gating state
1928 *
1929 * Set VCN block powergating state
1930 */
1931static int vcn_v4_0_set_powergating_state(void *handle, enum amd_powergating_state state)
1932{
1933 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1934 int ret;
1935
1936 /* for SRIOV, guest should not control VCN Power-gating
1937 * MMSCH FW should control Power-gating and clock-gating
1938 * guest should avoid touching CGC and PG
1939 */
1940 if (amdgpu_sriov_vf(adev)) {
1941 adev->vcn.cur_state = AMD_PG_STATE_UNGATE;
1942 return 0;
1943 }
1944
1945 if(state == adev->vcn.cur_state)
1946 return 0;
1947
1948 if (state == AMD_PG_STATE_GATE)
1949 ret = vcn_v4_0_stop(adev);
1950 else
1951 ret = vcn_v4_0_start(adev);
1952
1953 if(!ret)
1954 adev->vcn.cur_state = state;
1955
1956 return ret;
1957}
1958
1959/**
1960 * vcn_v4_0_set_interrupt_state - set VCN block interrupt state
1961 *
1962 * @adev: amdgpu_device pointer
1963 * @source: interrupt sources
1964 * @type: interrupt types
1965 * @state: interrupt states
1966 *
1967 * Set VCN block interrupt state
1968 */
1969static int vcn_v4_0_set_interrupt_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1970 unsigned type, enum amdgpu_interrupt_state state)
1971{
1972 return 0;
1973}
1974
1975/**
1976 * vcn_v4_0_process_interrupt - process VCN block interrupt
1977 *
1978 * @adev: amdgpu_device pointer
1979 * @source: interrupt sources
1980 * @entry: interrupt entry from clients and sources
1981 *
1982 * Process VCN block interrupt
1983 */
1984static int vcn_v4_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source,
1985 struct amdgpu_iv_entry *entry)
1986{
1987 uint32_t ip_instance;
1988
1989 switch (entry->client_id) {
1990 case SOC15_IH_CLIENTID_VCN:
1991 ip_instance = 0;
1992 break;
1993 case SOC15_IH_CLIENTID_VCN1:
1994 ip_instance = 1;
1995 break;
1996 default:
1997 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1998 return 0;
1999 }
2000
2001 DRM_DEBUG("IH: VCN TRAP\n");
2002
2003 switch (entry->src_id) {
2004 case VCN_4_0__SRCID__UVD_ENC_GENERAL_PURPOSE:
2005 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
2006 break;
2007 case VCN_4_0__SRCID_UVD_POISON:
2008 amdgpu_vcn_process_poison_irq(adev, source, entry);
2009 break;
2010 default:
2011 DRM_ERROR("Unhandled interrupt: %d %d\n",
2012 entry->src_id, entry->src_data[0]);
2013 break;
2014 }
2015
2016 return 0;
2017}
2018
2019static const struct amdgpu_irq_src_funcs vcn_v4_0_irq_funcs = {
2020 .set = vcn_v4_0_set_interrupt_state,
2021 .process = vcn_v4_0_process_interrupt,
2022};
2023
2024/**
2025 * vcn_v4_0_set_irq_funcs - set VCN block interrupt irq functions
2026 *
2027 * @adev: amdgpu_device pointer
2028 *
2029 * Set VCN block interrupt irq functions
2030 */
2031static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
2032{
2033 int i;
2034
2035 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2036 if (adev->vcn.harvest_config & (1 << i))
2037 continue;
2038
2039 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
2040 adev->vcn.inst[i].irq.funcs = &vcn_v4_0_irq_funcs;
2041 }
2042}
2043
2044static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
2045 .name = "vcn_v4_0",
2046 .early_init = vcn_v4_0_early_init,
2047 .late_init = NULL,
2048 .sw_init = vcn_v4_0_sw_init,
2049 .sw_fini = vcn_v4_0_sw_fini,
2050 .hw_init = vcn_v4_0_hw_init,
2051 .hw_fini = vcn_v4_0_hw_fini,
2052 .suspend = vcn_v4_0_suspend,
2053 .resume = vcn_v4_0_resume,
2054 .is_idle = vcn_v4_0_is_idle,
2055 .wait_for_idle = vcn_v4_0_wait_for_idle,
2056 .check_soft_reset = NULL,
2057 .pre_soft_reset = NULL,
2058 .soft_reset = NULL,
2059 .post_soft_reset = NULL,
2060 .set_clockgating_state = vcn_v4_0_set_clockgating_state,
2061 .set_powergating_state = vcn_v4_0_set_powergating_state,
2062};
2063
2064const struct amdgpu_ip_block_version vcn_v4_0_ip_block =
2065{
2066 .type = AMD_IP_BLOCK_TYPE_VCN,
2067 .major = 4,
2068 .minor = 0,
2069 .rev = 0,
2070 .funcs = &vcn_v4_0_ip_funcs,
2071};
2072
2073static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,
2074 uint32_t instance, uint32_t sub_block)
2075{
2076 uint32_t poison_stat = 0, reg_value = 0;
2077
2078 switch (sub_block) {
2079 case AMDGPU_VCN_V4_0_VCPU_VCODEC:
2080 reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);
2081 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);
2082 break;
2083 default:
2084 break;
2085 }
2086
2087 if (poison_stat)
2088 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",
2089 instance, sub_block);
2090
2091 return poison_stat;
2092}
2093
2094static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)
2095{
2096 uint32_t inst, sub;
2097 uint32_t poison_stat = 0;
2098
2099 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
2100 for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)
2101 poison_stat +=
2102 vcn_v4_0_query_poison_by_instance(adev, inst, sub);
2103
2104 return !!poison_stat;
2105}
2106
2107const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {
2108 .query_poison_status = vcn_v4_0_query_ras_poison_status,
2109};
2110
2111static struct amdgpu_vcn_ras vcn_v4_0_ras = {
2112 .ras_block = {
2113 .hw_ops = &vcn_v4_0_ras_hw_ops,
2114 },
2115};
2116
2117static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)
2118{
2119 switch (adev->ip_versions[VCN_HWIP][0]) {
2120 case IP_VERSION(4, 0, 0):
2121 adev->vcn.ras = &vcn_v4_0_ras;
2122 break;
2123 default:
2124 break;
2125 }
2126
2127 amdgpu_vcn_set_ras_funcs(adev);
2128}