Linux kernel mirror (for testing)
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1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_QP_H
34#define MLX5_QP_H
35
36#include <linux/mlx5/device.h>
37#include <linux/mlx5/driver.h>
38
39#define MLX5_INVALID_LKEY 0x100
40/* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
41#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8)
42#define MLX5_DIF_SIZE 8
43#define MLX5_STRIDE_BLOCK_OP 0x400
44#define MLX5_CPY_GRD_MASK 0xc0
45#define MLX5_CPY_APP_MASK 0x30
46#define MLX5_CPY_REF_MASK 0x0f
47#define MLX5_BSF_INC_REFTAG (1 << 6)
48#define MLX5_BSF_INL_VALID (1 << 15)
49#define MLX5_BSF_REFRESH_DIF (1 << 14)
50#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
51#define MLX5_BSF_APPTAG_ESCAPE 0x1
52#define MLX5_BSF_APPREF_ESCAPE 0x2
53
54enum mlx5_qp_optpar {
55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
56 MLX5_QP_OPTPAR_RRE = 1 << 1,
57 MLX5_QP_OPTPAR_RAE = 1 << 2,
58 MLX5_QP_OPTPAR_RWE = 1 << 3,
59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
69 MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15,
70 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
71 MLX5_QP_OPTPAR_SRQN = 1 << 18,
72 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
73 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
74 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
75 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25,
76};
77
78enum mlx5_qp_state {
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
88 MLX5_QP_NUM_STATE,
89 MLX5_QP_STATE,
90 MLX5_QP_STATE_BAD,
91};
92
93enum {
94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
98};
99
100enum {
101 MLX5_QP_ST_RC = 0x0,
102 MLX5_QP_ST_UC = 0x1,
103 MLX5_QP_ST_UD = 0x2,
104 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR = 0xc,
116 MLX5_QP_ST_MAX
117};
118
119enum {
120 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM = 0x1
123};
124
125enum {
126 MLX5_NON_ZERO_RQ = 0x0,
127 MLX5_SRQ_RQ = 0x1,
128 MLX5_CRQ_RQ = 0x2,
129 MLX5_ZERO_LEN_RQ = 0x3
130};
131
132/* TODO REM */
133enum {
134 /* params1 */
135 MLX5_QP_BIT_SRE = 1 << 15,
136 MLX5_QP_BIT_SWE = 1 << 14,
137 MLX5_QP_BIT_SAE = 1 << 13,
138 /* params2 */
139 MLX5_QP_BIT_RRE = 1 << 15,
140 MLX5_QP_BIT_RWE = 1 << 14,
141 MLX5_QP_BIT_RAE = 1 << 13,
142 MLX5_QP_BIT_RIC = 1 << 4,
143 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
144 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
145 MLX5_QP_BIT_CC_MASTER = 1 << 0
146};
147
148enum {
149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
151 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
152};
153
154enum {
155 MLX5_SEND_WQE_DS = 16,
156 MLX5_SEND_WQE_BB = 64,
157};
158
159#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
160
161enum {
162 MLX5_SEND_WQE_MAX_WQEBBS = 16,
163};
164
165#define MLX5_SEND_WQE_MAX_SIZE (MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQE_BB)
166
167enum {
168 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
169 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
170 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
171 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
172 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
173};
174
175enum {
176 MLX5_FENCE_MODE_NONE = 0 << 5,
177 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
178 MLX5_FENCE_MODE_FENCE = 2 << 5,
179 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
180 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
181};
182
183enum {
184 MLX5_RCV_DBR = 0,
185 MLX5_SND_DBR = 1,
186};
187
188enum {
189 MLX5_FLAGS_INLINE = 1<<7,
190 MLX5_FLAGS_CHECK_FREE = 1<<5,
191};
192
193struct mlx5_wqe_fmr_seg {
194 __be32 flags;
195 __be32 mem_key;
196 __be64 buf_list;
197 __be64 start_addr;
198 __be64 reg_len;
199 __be32 offset;
200 __be32 page_size;
201 u32 reserved[2];
202};
203
204struct mlx5_wqe_ctrl_seg {
205 __be32 opmod_idx_opcode;
206 __be32 qpn_ds;
207
208 struct_group(trailer,
209
210 u8 signature;
211 u8 rsvd[2];
212 u8 fm_ce_se;
213 union {
214 __be32 general_id;
215 __be32 imm;
216 __be32 umr_mkey;
217 __be32 tis_tir_num;
218 };
219
220 ); /* end of trailer group */
221};
222
223#define MLX5_WQE_CTRL_DS_MASK 0x3f
224#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
225#define MLX5_WQE_CTRL_QPN_SHIFT 8
226#define MLX5_WQE_DS_UNITS 16
227#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
228#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
229#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
230
231enum {
232 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
233 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
234 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
235 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
236};
237
238enum {
239 MLX5_ETH_WQE_SVLAN = 1 << 0,
240 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
241 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
242 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
243 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
244 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30,
245 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
246};
247
248enum {
249 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
250 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
251 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
252 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
253};
254
255enum {
256 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
257 MLX5_ETH_WQE_FT_META_MACSEC = BIT(1),
258};
259
260struct mlx5_wqe_eth_seg {
261 u8 swp_outer_l4_offset;
262 u8 swp_outer_l3_offset;
263 u8 swp_inner_l4_offset;
264 u8 swp_inner_l3_offset;
265 u8 cs_flags;
266 u8 swp_flags;
267 __be16 mss;
268 __be32 flow_table_metadata;
269 union {
270 struct {
271 __be16 sz;
272 u8 start[2];
273 } inline_hdr;
274 struct {
275 __be16 type;
276 __be16 vlan_tci;
277 } insert;
278 __be32 trailer;
279 };
280};
281
282struct mlx5_wqe_xrc_seg {
283 __be32 xrc_srqn;
284 u8 rsvd[12];
285};
286
287struct mlx5_wqe_masked_atomic_seg {
288 __be64 swap_add;
289 __be64 compare;
290 __be64 swap_add_mask;
291 __be64 compare_mask;
292};
293
294struct mlx5_base_av {
295 union {
296 struct {
297 __be32 qkey;
298 __be32 reserved;
299 } qkey;
300 __be64 dc_key;
301 } key;
302 __be32 dqp_dct;
303 u8 stat_rate_sl;
304 u8 fl_mlid;
305 union {
306 __be16 rlid;
307 __be16 udp_sport;
308 };
309};
310
311struct mlx5_av {
312 union {
313 struct {
314 __be32 qkey;
315 __be32 reserved;
316 } qkey;
317 __be64 dc_key;
318 } key;
319 __be32 dqp_dct;
320 u8 stat_rate_sl;
321 u8 fl_mlid;
322 union {
323 __be16 rlid;
324 __be16 udp_sport;
325 };
326 u8 reserved0[4];
327 u8 rmac[6];
328 u8 tclass;
329 u8 hop_limit;
330 __be32 grh_gid_fl;
331 u8 rgid[16];
332};
333
334struct mlx5_ib_ah {
335 struct ib_ah ibah;
336 struct mlx5_av av;
337 u8 xmit_port;
338};
339
340static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
341{
342 return container_of(ibah, struct mlx5_ib_ah, ibah);
343}
344
345struct mlx5_wqe_datagram_seg {
346 struct mlx5_av av;
347};
348
349struct mlx5_wqe_raddr_seg {
350 __be64 raddr;
351 __be32 rkey;
352 u32 reserved;
353};
354
355struct mlx5_wqe_atomic_seg {
356 __be64 swap_add;
357 __be64 compare;
358};
359
360struct mlx5_wqe_data_seg {
361 __be32 byte_count;
362 __be32 lkey;
363 __be64 addr;
364};
365
366struct mlx5_wqe_umr_ctrl_seg {
367 u8 flags;
368 u8 rsvd0[3];
369 __be16 xlt_octowords;
370 union {
371 __be16 xlt_offset;
372 __be16 bsf_octowords;
373 };
374 __be64 mkey_mask;
375 __be32 xlt_offset_47_16;
376 u8 rsvd1[28];
377};
378
379struct mlx5_seg_set_psv {
380 __be32 psv_num;
381 __be16 syndrome;
382 __be16 status;
383 __be32 transient_sig;
384 __be32 ref_tag;
385};
386
387struct mlx5_seg_get_psv {
388 u8 rsvd[19];
389 u8 num_psv;
390 __be32 l_key;
391 __be64 va;
392 __be32 psv_index[4];
393};
394
395struct mlx5_seg_check_psv {
396 u8 rsvd0[2];
397 __be16 err_coalescing_op;
398 u8 rsvd1[2];
399 __be16 xport_err_op;
400 u8 rsvd2[2];
401 __be16 xport_err_mask;
402 u8 rsvd3[7];
403 u8 num_psv;
404 __be32 l_key;
405 __be64 va;
406 __be32 psv_index[4];
407};
408
409struct mlx5_rwqe_sig {
410 u8 rsvd0[4];
411 u8 signature;
412 u8 rsvd1[11];
413};
414
415struct mlx5_wqe_signature_seg {
416 u8 rsvd0[4];
417 u8 signature;
418 u8 rsvd1[11];
419};
420
421#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
422
423struct mlx5_wqe_inline_seg {
424 __be32 byte_count;
425 __be32 data[];
426};
427
428enum mlx5_sig_type {
429 MLX5_DIF_CRC = 0x1,
430 MLX5_DIF_IPCS = 0x2,
431};
432
433struct mlx5_bsf_inl {
434 __be16 vld_refresh;
435 __be16 dif_apptag;
436 __be32 dif_reftag;
437 u8 sig_type;
438 u8 rp_inv_seed;
439 u8 rsvd[3];
440 u8 dif_inc_ref_guard_check;
441 __be16 dif_app_bitmask_check;
442};
443
444struct mlx5_bsf {
445 struct mlx5_bsf_basic {
446 u8 bsf_size_sbs;
447 u8 check_byte_mask;
448 union {
449 u8 copy_byte_mask;
450 u8 bs_selector;
451 u8 rsvd_wflags;
452 } wire;
453 union {
454 u8 bs_selector;
455 u8 rsvd_mflags;
456 } mem;
457 __be32 raw_data_size;
458 __be32 w_bfs_psv;
459 __be32 m_bfs_psv;
460 } basic;
461 struct mlx5_bsf_ext {
462 __be32 t_init_gen_pro_size;
463 __be32 rsvd_epi_size;
464 __be32 w_tfs_psv;
465 __be32 m_tfs_psv;
466 } ext;
467 struct mlx5_bsf_inl w_inl;
468 struct mlx5_bsf_inl m_inl;
469};
470
471struct mlx5_mtt {
472 __be64 ptag;
473};
474
475struct mlx5_klm {
476 __be32 bcount;
477 __be32 key;
478 __be64 va;
479};
480
481struct mlx5_ksm {
482 __be32 reserved;
483 __be32 key;
484 __be64 va;
485};
486
487struct mlx5_stride_block_entry {
488 __be16 stride;
489 __be16 bcount;
490 __be32 key;
491 __be64 va;
492};
493
494struct mlx5_stride_block_ctrl_seg {
495 __be32 bcount_per_cycle;
496 __be32 op;
497 __be32 repeat_count;
498 u16 rsvd;
499 __be16 num_entries;
500};
501
502struct mlx5_core_qp {
503 struct mlx5_core_rsc_common common; /* must be first */
504 void (*event) (struct mlx5_core_qp *, int);
505 int qpn;
506 struct mlx5_rsc_debug *dbg;
507 int pid;
508 u16 uid;
509};
510
511struct mlx5_core_dct {
512 struct mlx5_core_qp mqp;
513 struct completion drained;
514};
515
516int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
517void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
518
519static inline const char *mlx5_qp_type_str(int type)
520{
521 switch (type) {
522 case MLX5_QP_ST_RC: return "RC";
523 case MLX5_QP_ST_UC: return "C";
524 case MLX5_QP_ST_UD: return "UD";
525 case MLX5_QP_ST_XRC: return "XRC";
526 case MLX5_QP_ST_MLX: return "MLX";
527 case MLX5_QP_ST_QP0: return "QP0";
528 case MLX5_QP_ST_QP1: return "QP1";
529 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
530 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
531 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
532 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
533 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
534 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
535 default: return "Invalid transport type";
536 }
537}
538
539static inline const char *mlx5_qp_state_str(int state)
540{
541 switch (state) {
542 case MLX5_QP_STATE_RST:
543 return "RST";
544 case MLX5_QP_STATE_INIT:
545 return "INIT";
546 case MLX5_QP_STATE_RTR:
547 return "RTR";
548 case MLX5_QP_STATE_RTS:
549 return "RTS";
550 case MLX5_QP_STATE_SQER:
551 return "SQER";
552 case MLX5_QP_STATE_SQD:
553 return "SQD";
554 case MLX5_QP_STATE_ERR:
555 return "ERR";
556 case MLX5_QP_STATE_SQ_DRAINING:
557 return "SQ_DRAINING";
558 case MLX5_QP_STATE_SUSPENDED:
559 return "SUSPENDED";
560 default: return "Invalid QP state";
561 }
562}
563
564static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
565{
566 return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
567 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
568 MLX5_TIMESTAMP_FORMAT_DEFAULT;
569}
570
571#endif /* MLX5_QP_H */