Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2/*
3 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
4 */
5
6#ifndef _MLX5_ESWITCH_
7#define _MLX5_ESWITCH_
8
9#include <linux/mlx5/driver.h>
10#include <net/devlink.h>
11
12#define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)
13
14enum {
15 MLX5_ESWITCH_LEGACY,
16 MLX5_ESWITCH_OFFLOADS
17};
18
19enum {
20 REP_ETH,
21 REP_IB,
22 NUM_REP_TYPES,
23};
24
25enum {
26 REP_UNREGISTERED,
27 REP_REGISTERED,
28 REP_LOADED,
29};
30
31enum mlx5_switchdev_event {
32 MLX5_SWITCHDEV_EVENT_PAIR,
33 MLX5_SWITCHDEV_EVENT_UNPAIR,
34};
35
36struct mlx5_eswitch_rep;
37struct mlx5_eswitch_rep_ops {
38 int (*load)(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep);
39 void (*unload)(struct mlx5_eswitch_rep *rep);
40 void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep);
41 int (*event)(struct mlx5_eswitch *esw,
42 struct mlx5_eswitch_rep *rep,
43 enum mlx5_switchdev_event event,
44 void *data);
45};
46
47struct mlx5_eswitch_rep_data {
48 void *priv;
49 atomic_t state;
50};
51
52struct mlx5_eswitch_rep {
53 struct mlx5_eswitch_rep_data rep_data[NUM_REP_TYPES];
54 u16 vport;
55 u16 vlan;
56 /* Only IB rep is using vport_index */
57 u16 vport_index;
58 u32 vlan_refcount;
59 struct mlx5_eswitch *esw;
60};
61
62void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
63 const struct mlx5_eswitch_rep_ops *ops,
64 u8 rep_type);
65void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);
66void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
67 u16 vport_num,
68 u8 rep_type);
69struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
70 u16 vport_num);
71void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
72struct mlx5_flow_handle *
73mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
74 struct mlx5_eswitch *from_esw,
75 struct mlx5_eswitch_rep *rep, u32 sqn);
76
77#ifdef CONFIG_MLX5_ESWITCH
78enum devlink_eswitch_encap_mode
79mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
80
81bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw);
82bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);
83
84/* Reg C0 usage:
85 * Reg C0 = < ESW_PFNUM_BITS(4) | ESW_VPORT BITS(12) | ESW_REG_C0_OBJ(16) >
86 *
87 * Highest 4 bits of the reg c0 is the PF_NUM (range 0-15), 12 bits of
88 * unique non-zero vport id (range 1-4095). The rest (lowest 16 bits) is left
89 * for user data objects managed by a common mapping context.
90 * PFNUM + VPORT comprise the SOURCE_PORT matching.
91 */
92#define ESW_VPORT_BITS 12
93#define ESW_PFNUM_BITS 4
94#define ESW_SOURCE_PORT_METADATA_BITS (ESW_PFNUM_BITS + ESW_VPORT_BITS)
95#define ESW_SOURCE_PORT_METADATA_OFFSET (32 - ESW_SOURCE_PORT_METADATA_BITS)
96#define ESW_REG_C0_USER_DATA_METADATA_BITS (32 - ESW_SOURCE_PORT_METADATA_BITS)
97#define ESW_REG_C0_USER_DATA_METADATA_MASK GENMASK(ESW_REG_C0_USER_DATA_METADATA_BITS - 1, 0)
98
99static inline u32 mlx5_eswitch_get_vport_metadata_mask(void)
100{
101 return GENMASK(31, 32 - ESW_SOURCE_PORT_METADATA_BITS);
102}
103
104u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
105 u16 vport_num);
106u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
107 u16 vport_num);
108
109/* Reg C1 usage:
110 * Reg C1 = < Reserved(1) | ESW_TUN_ID(12) | ESW_TUN_OPTS(11) | ESW_ZONE_ID(8) >
111 *
112 * Highest bit is reserved for other offloads as marker bit, next 12 bits of reg c1
113 * is the encapsulation tunnel id, next 11 bits is encapsulation tunnel options,
114 * and the lowest 8 bits are used for zone id.
115 *
116 * Zone id is used to restore CT flow when packet misses on chain.
117 *
118 * Tunnel id and options are used together to restore the tunnel info metadata
119 * on miss and to support inner header rewrite by means of implicit chain 0
120 * flows.
121 */
122#define ESW_RESERVED_BITS 1
123#define ESW_ZONE_ID_BITS 8
124#define ESW_TUN_OPTS_BITS 11
125#define ESW_TUN_ID_BITS 12
126#define ESW_TUN_OPTS_OFFSET ESW_ZONE_ID_BITS
127#define ESW_TUN_OFFSET ESW_TUN_OPTS_OFFSET
128#define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0)
129#define ESW_TUN_OPTS_MASK GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, ESW_TUN_OPTS_OFFSET)
130#define ESW_TUN_MASK GENMASK(31 - ESW_RESERVED_BITS, ESW_TUN_OFFSET)
131#define ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT 0 /* 0 is not a valid tunnel id */
132#define ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT
133/* 0x7FF is a reserved mapping */
134#define ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT GENMASK(ESW_TUN_OPTS_BITS - 1, 0)
135#define ESW_TUN_SLOW_TABLE_GOTO_VPORT ((ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT << ESW_TUN_OPTS_BITS) | \
136 ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT)
137#define ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK ESW_TUN_OPTS_MASK
138/* 0x7FE is a reserved mapping for bridge ingress push vlan mark */
139#define ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN (ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT - 1)
140#define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN ((ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN << \
141 ESW_TUN_OPTS_BITS) | \
142 ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN)
143#define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN_MARK \
144 GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, \
145 ESW_TUN_OPTS_OFFSET + 1)
146
147u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev);
148u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
149struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw);
150
151#else /* CONFIG_MLX5_ESWITCH */
152
153static inline u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev)
154{
155 return MLX5_ESWITCH_LEGACY;
156}
157
158static inline enum devlink_eswitch_encap_mode
159mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
160{
161 return DEVLINK_ESWITCH_ENCAP_MODE_NONE;
162}
163
164static inline bool
165mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
166{
167 return false;
168};
169
170static inline bool
171mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
172{
173 return false;
174};
175
176static inline u32
177mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, u16 vport_num)
178{
179 return 0;
180};
181
182static inline u32
183mlx5_eswitch_get_vport_metadata_mask(void)
184{
185 return 0;
186}
187
188static inline u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev)
189{
190 return 0;
191}
192
193static inline struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw)
194{
195 return NULL;
196}
197
198#endif /* CONFIG_MLX5_ESWITCH */
199
200static inline bool is_mdev_legacy_mode(struct mlx5_core_dev *dev)
201{
202 return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_LEGACY;
203}
204
205static inline bool is_mdev_switchdev_mode(struct mlx5_core_dev *dev)
206{
207 return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_OFFLOADS;
208}
209
210#endif