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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
5 *
6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
7 */
8
9#ifndef _DW_EDMA_H
10#define _DW_EDMA_H
11
12#include <linux/device.h>
13#include <linux/dmaengine.h>
14
15#define EDMA_MAX_WR_CH 8
16#define EDMA_MAX_RD_CH 8
17
18struct dw_edma;
19
20struct dw_edma_region {
21 phys_addr_t paddr;
22 void __iomem *vaddr;
23 size_t sz;
24};
25
26struct dw_edma_core_ops {
27 int (*irq_vector)(struct device *dev, unsigned int nr);
28};
29
30enum dw_edma_map_format {
31 EDMA_MF_EDMA_LEGACY = 0x0,
32 EDMA_MF_EDMA_UNROLL = 0x1,
33 EDMA_MF_HDMA_COMPAT = 0x5
34};
35
36/**
37 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
38 * @DW_EDMA_CHIP_LOCAL: eDMA is used locally by an endpoint
39 */
40enum dw_edma_chip_flags {
41 DW_EDMA_CHIP_LOCAL = BIT(0),
42};
43
44/**
45 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
46 * @dev: struct device of the eDMA controller
47 * @id: instance ID
48 * @nr_irqs: total number of DMA IRQs
49 * @ops DMA channel to IRQ number mapping
50 * @flags dw_edma_chip_flags
51 * @reg_base DMA register base address
52 * @ll_wr_cnt DMA write link list count
53 * @ll_rd_cnt DMA read link list count
54 * @rg_region DMA register region
55 * @ll_region_wr DMA descriptor link list memory for write channel
56 * @ll_region_rd DMA descriptor link list memory for read channel
57 * @dt_region_wr DMA data memory for write channel
58 * @dt_region_rd DMA data memory for read channel
59 * @mf DMA register map format
60 * @dw: struct dw_edma that is filled by dw_edma_probe()
61 */
62struct dw_edma_chip {
63 struct device *dev;
64 int id;
65 int nr_irqs;
66 const struct dw_edma_core_ops *ops;
67 u32 flags;
68
69 void __iomem *reg_base;
70
71 u16 ll_wr_cnt;
72 u16 ll_rd_cnt;
73 /* link list address */
74 struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH];
75 struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH];
76
77 /* data region */
78 struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH];
79 struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH];
80
81 enum dw_edma_map_format mf;
82
83 struct dw_edma *dw;
84};
85
86/* Export to the platform drivers */
87#if IS_ENABLED(CONFIG_DW_EDMA)
88int dw_edma_probe(struct dw_edma_chip *chip);
89int dw_edma_remove(struct dw_edma_chip *chip);
90#else
91static inline int dw_edma_probe(struct dw_edma_chip *chip)
92{
93 return -ENODEV;
94}
95
96static inline int dw_edma_remove(struct dw_edma_chip *chip)
97{
98 return 0;
99}
100#endif /* CONFIG_DW_EDMA */
101
102#endif /* _DW_EDMA_H */