tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MAX11410 SPI ADC driver
4 *
5 * Copyright 2022 Analog Devices Inc.
6 */
7#include <asm-generic/unaligned.h>
8#include <linux/bitfield.h>
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/regmap.h>
16#include <linux/regulator/consumer.h>
17#include <linux/spi/spi.h>
18
19#include <linux/iio/buffer.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/trigger.h>
22#include <linux/iio/trigger_consumer.h>
23#include <linux/iio/triggered_buffer.h>
24
25#define MAX11410_REG_CONV_START 0x01
26#define MAX11410_CONV_TYPE_SINGLE 0x00
27#define MAX11410_CONV_TYPE_CONTINUOUS 0x01
28#define MAX11410_REG_CAL_START 0x03
29#define MAX11410_CAL_START_SELF 0x00
30#define MAX11410_CAL_START_PGA 0x01
31#define MAX11410_REG_GPIO_CTRL(ch) ((ch) ? 0x05 : 0x04)
32#define MAX11410_GPIO_INTRB 0xC1
33#define MAX11410_REG_FILTER 0x08
34#define MAX11410_FILTER_RATE_MASK GENMASK(3, 0)
35#define MAX11410_FILTER_RATE_MAX 0x0F
36#define MAX11410_FILTER_LINEF_MASK GENMASK(5, 4)
37#define MAX11410_FILTER_50HZ BIT(5)
38#define MAX11410_FILTER_60HZ BIT(4)
39#define MAX11410_REG_CTRL 0x09
40#define MAX11410_CTRL_REFSEL_MASK GENMASK(2, 0)
41#define MAX11410_CTRL_VREFN_BUF_BIT BIT(3)
42#define MAX11410_CTRL_VREFP_BUF_BIT BIT(4)
43#define MAX11410_CTRL_FORMAT_BIT BIT(5)
44#define MAX11410_CTRL_UNIPOLAR_BIT BIT(6)
45#define MAX11410_REG_MUX_CTRL0 0x0B
46#define MAX11410_REG_PGA 0x0E
47#define MAX11410_PGA_GAIN_MASK GENMASK(2, 0)
48#define MAX11410_PGA_SIG_PATH_MASK GENMASK(5, 4)
49#define MAX11410_PGA_SIG_PATH_BUFFERED 0x00
50#define MAX11410_PGA_SIG_PATH_BYPASS 0x01
51#define MAX11410_PGA_SIG_PATH_PGA 0x02
52#define MAX11410_REG_DATA0 0x30
53#define MAX11410_REG_STATUS 0x38
54#define MAX11410_STATUS_CONV_READY_BIT BIT(0)
55#define MAX11410_STATUS_CAL_READY_BIT BIT(2)
56
57#define MAX11410_REFSEL_AVDD_AGND 0x03
58#define MAX11410_REFSEL_MAX 0x06
59#define MAX11410_SIG_PATH_MAX 0x02
60#define MAX11410_CHANNEL_INDEX_MAX 0x0A
61#define MAX11410_AINP_AVDD 0x0A
62#define MAX11410_AINN_GND 0x0A
63
64#define MAX11410_CONVERSION_TIMEOUT_MS 2000
65#define MAX11410_CALIB_TIMEOUT_MS 2000
66
67#define MAX11410_SCALE_AVAIL_SIZE 8
68
69enum max11410_filter {
70 MAX11410_FILTER_FIR5060,
71 MAX11410_FILTER_FIR50,
72 MAX11410_FILTER_FIR60,
73 MAX11410_FILTER_SINC4,
74};
75
76static const u8 max11410_sampling_len[] = {
77 [MAX11410_FILTER_FIR5060] = 5,
78 [MAX11410_FILTER_FIR50] = 6,
79 [MAX11410_FILTER_FIR60] = 6,
80 [MAX11410_FILTER_SINC4] = 10,
81};
82
83static const int max11410_sampling_rates[4][10][2] = {
84 [MAX11410_FILTER_FIR5060] = {
85 { 1, 100000 },
86 { 2, 100000 },
87 { 4, 200000 },
88 { 8, 400000 },
89 { 16, 800000 }
90 },
91 [MAX11410_FILTER_FIR50] = {
92 { 1, 300000 },
93 { 2, 700000 },
94 { 5, 300000 },
95 { 10, 700000 },
96 { 21, 300000 },
97 { 40 }
98 },
99 [MAX11410_FILTER_FIR60] = {
100 { 1, 300000 },
101 { 2, 700000 },
102 { 5, 300000 },
103 { 10, 700000 },
104 { 21, 300000 },
105 { 40 }
106 },
107 [MAX11410_FILTER_SINC4] = {
108 { 4 },
109 { 10 },
110 { 20 },
111 { 40 },
112 { 60 },
113 { 120 },
114 { 240 },
115 { 480 },
116 { 960 },
117 { 1920 }
118 }
119};
120
121struct max11410_channel_config {
122 u32 settling_time_us;
123 u32 *scale_avail;
124 u8 refsel;
125 u8 sig_path;
126 u8 gain;
127 bool bipolar;
128 bool buffered_vrefp;
129 bool buffered_vrefn;
130};
131
132struct max11410_state {
133 struct spi_device *spi_dev;
134 struct iio_trigger *trig;
135 struct completion completion;
136 struct mutex lock; /* Prevent changing channel config during sampling */
137 struct regmap *regmap;
138 struct regulator *avdd;
139 struct regulator *vrefp[3];
140 struct regulator *vrefn[3];
141 struct max11410_channel_config *channels;
142 int irq;
143 struct {
144 u32 data __aligned(IIO_DMA_MINALIGN);
145 s64 ts __aligned(8);
146 } scan;
147};
148
149static const struct iio_chan_spec chanspec_template = {
150 .type = IIO_VOLTAGE,
151 .indexed = 1,
152 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
153 BIT(IIO_CHAN_INFO_SCALE) |
154 BIT(IIO_CHAN_INFO_OFFSET),
155 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
156 .info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
157 .scan_type = {
158 .sign = 's',
159 .realbits = 24,
160 .storagebits = 32,
161 .endianness = IIO_LE,
162 },
163};
164
165static unsigned int max11410_reg_size(unsigned int reg)
166{
167 /* Registers from 0x00 to 0x10 are 1 byte, the rest are 3 bytes long. */
168 return reg <= 0x10 ? 1 : 3;
169}
170
171static int max11410_write_reg(struct max11410_state *st, unsigned int reg,
172 unsigned int val)
173{
174 /* This driver only needs to write 8-bit registers */
175 if (max11410_reg_size(reg) != 1)
176 return -EINVAL;
177
178 return regmap_write(st->regmap, reg, val);
179}
180
181static int max11410_read_reg(struct max11410_state *st, unsigned int reg,
182 int *val)
183{
184 int ret;
185
186 if (max11410_reg_size(reg) == 3) {
187 ret = regmap_bulk_read(st->regmap, reg, &st->scan.data, 3);
188 if (ret)
189 return ret;
190
191 *val = get_unaligned_be24(&st->scan.data);
192 return 0;
193 }
194
195 return regmap_read(st->regmap, reg, val);
196}
197
198static struct regulator *max11410_get_vrefp(struct max11410_state *st,
199 u8 refsel)
200{
201 refsel = refsel % 4;
202 if (refsel == 3)
203 return st->avdd;
204
205 return st->vrefp[refsel];
206}
207
208static struct regulator *max11410_get_vrefn(struct max11410_state *st,
209 u8 refsel)
210{
211 if (refsel > 2)
212 return NULL;
213
214 return st->vrefn[refsel];
215}
216
217static const struct regmap_config regmap_config = {
218 .reg_bits = 8,
219 .val_bits = 8,
220 .max_register = 0x39,
221};
222
223static ssize_t max11410_notch_en_show(struct device *dev,
224 struct device_attribute *devattr,
225 char *buf)
226{
227 struct iio_dev *indio_dev = dev_get_drvdata(dev);
228 struct max11410_state *state = iio_priv(indio_dev);
229 struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr);
230 unsigned int val;
231 int ret;
232
233 ret = max11410_read_reg(state, MAX11410_REG_FILTER, &val);
234 if (ret)
235 return ret;
236
237 switch (iio_attr->address) {
238 case 0:
239 val = !FIELD_GET(MAX11410_FILTER_50HZ, val);
240 break;
241 case 1:
242 val = !FIELD_GET(MAX11410_FILTER_60HZ, val);
243 break;
244 case 2:
245 val = FIELD_GET(MAX11410_FILTER_LINEF_MASK, val) == 3;
246 break;
247 default:
248 return -EINVAL;
249 }
250
251 return sysfs_emit(buf, "%d\n", val);
252}
253
254static ssize_t max11410_notch_en_store(struct device *dev,
255 struct device_attribute *devattr,
256 const char *buf, size_t count)
257{
258 struct iio_dev_attr *iio_attr = to_iio_dev_attr(devattr);
259 struct iio_dev *indio_dev = dev_get_drvdata(dev);
260 struct max11410_state *state = iio_priv(indio_dev);
261 unsigned int filter_bits;
262 bool enable;
263 int ret;
264
265 ret = kstrtobool(buf, &enable);
266 if (ret)
267 return ret;
268
269 switch (iio_attr->address) {
270 case 0:
271 filter_bits = MAX11410_FILTER_50HZ;
272 break;
273 case 1:
274 filter_bits = MAX11410_FILTER_60HZ;
275 break;
276 case 2:
277 default:
278 filter_bits = MAX11410_FILTER_50HZ | MAX11410_FILTER_60HZ;
279 enable = !enable;
280 break;
281 }
282
283 if (enable)
284 ret = regmap_clear_bits(state->regmap, MAX11410_REG_FILTER,
285 filter_bits);
286 else
287 ret = regmap_set_bits(state->regmap, MAX11410_REG_FILTER,
288 filter_bits);
289
290 if (ret)
291 return ret;
292
293 return count;
294}
295
296static ssize_t in_voltage_filter2_notch_center_show(struct device *dev,
297 struct device_attribute *devattr,
298 char *buf)
299{
300 struct iio_dev *indio_dev = dev_get_drvdata(dev);
301 struct max11410_state *state = iio_priv(indio_dev);
302 int ret, reg, rate, filter;
303
304 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®);
305 if (ret)
306 return ret;
307
308 rate = FIELD_GET(MAX11410_FILTER_RATE_MASK, reg);
309 rate = clamp_val(rate, 0,
310 max11410_sampling_len[MAX11410_FILTER_SINC4] - 1);
311 filter = max11410_sampling_rates[MAX11410_FILTER_SINC4][rate][0];
312
313 return sysfs_emit(buf, "%d\n", filter);
314}
315
316static IIO_CONST_ATTR(in_voltage_filter0_notch_center, "50");
317static IIO_CONST_ATTR(in_voltage_filter1_notch_center, "60");
318static IIO_DEVICE_ATTR_RO(in_voltage_filter2_notch_center, 2);
319
320static IIO_DEVICE_ATTR(in_voltage_filter0_notch_en, 0644,
321 max11410_notch_en_show, max11410_notch_en_store, 0);
322static IIO_DEVICE_ATTR(in_voltage_filter1_notch_en, 0644,
323 max11410_notch_en_show, max11410_notch_en_store, 1);
324static IIO_DEVICE_ATTR(in_voltage_filter2_notch_en, 0644,
325 max11410_notch_en_show, max11410_notch_en_store, 2);
326
327static struct attribute *max11410_attributes[] = {
328 &iio_const_attr_in_voltage_filter0_notch_center.dev_attr.attr,
329 &iio_const_attr_in_voltage_filter1_notch_center.dev_attr.attr,
330 &iio_dev_attr_in_voltage_filter2_notch_center.dev_attr.attr,
331 &iio_dev_attr_in_voltage_filter0_notch_en.dev_attr.attr,
332 &iio_dev_attr_in_voltage_filter1_notch_en.dev_attr.attr,
333 &iio_dev_attr_in_voltage_filter2_notch_en.dev_attr.attr,
334 NULL
335};
336
337static const struct attribute_group max11410_attribute_group = {
338 .attrs = max11410_attributes,
339};
340
341static int max11410_set_input_mux(struct max11410_state *st, u8 ainp, u8 ainn)
342{
343 if (ainp > MAX11410_CHANNEL_INDEX_MAX ||
344 ainn > MAX11410_CHANNEL_INDEX_MAX)
345 return -EINVAL;
346
347 return max11410_write_reg(st, MAX11410_REG_MUX_CTRL0,
348 (ainp << 4) | ainn);
349}
350
351static int max11410_configure_channel(struct max11410_state *st,
352 struct iio_chan_spec const *chan)
353{
354 struct max11410_channel_config cfg = st->channels[chan->address];
355 unsigned int regval;
356 int ret;
357
358 if (chan->differential)
359 ret = max11410_set_input_mux(st, chan->channel, chan->channel2);
360 else
361 ret = max11410_set_input_mux(st, chan->channel,
362 MAX11410_AINN_GND);
363
364 if (ret)
365 return ret;
366
367 regval = FIELD_PREP(MAX11410_CTRL_VREFP_BUF_BIT, cfg.buffered_vrefp) |
368 FIELD_PREP(MAX11410_CTRL_VREFN_BUF_BIT, cfg.buffered_vrefn) |
369 FIELD_PREP(MAX11410_CTRL_REFSEL_MASK, cfg.refsel) |
370 FIELD_PREP(MAX11410_CTRL_UNIPOLAR_BIT, cfg.bipolar ? 0 : 1);
371 ret = regmap_update_bits(st->regmap, MAX11410_REG_CTRL,
372 MAX11410_CTRL_REFSEL_MASK |
373 MAX11410_CTRL_VREFP_BUF_BIT |
374 MAX11410_CTRL_VREFN_BUF_BIT |
375 MAX11410_CTRL_UNIPOLAR_BIT, regval);
376 if (ret)
377 return ret;
378
379 regval = FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK, cfg.sig_path) |
380 FIELD_PREP(MAX11410_PGA_GAIN_MASK, cfg.gain);
381 ret = regmap_write(st->regmap, MAX11410_REG_PGA, regval);
382 if (ret)
383 return ret;
384
385 if (cfg.settling_time_us)
386 fsleep(cfg.settling_time_us);
387
388 return 0;
389}
390
391static int max11410_sample(struct max11410_state *st, int *sample_raw,
392 struct iio_chan_spec const *chan)
393{
394 int val, ret;
395
396 ret = max11410_configure_channel(st, chan);
397 if (ret)
398 return ret;
399
400 if (st->irq > 0)
401 reinit_completion(&st->completion);
402
403 /* Start Conversion */
404 ret = max11410_write_reg(st, MAX11410_REG_CONV_START,
405 MAX11410_CONV_TYPE_SINGLE);
406 if (ret)
407 return ret;
408
409 if (st->irq > 0) {
410 /* Wait for an interrupt. */
411 ret = wait_for_completion_timeout(&st->completion,
412 msecs_to_jiffies(MAX11410_CONVERSION_TIMEOUT_MS));
413 if (!ret)
414 return -ETIMEDOUT;
415 } else {
416 /* Wait for status register Conversion Ready flag */
417 ret = read_poll_timeout(max11410_read_reg, ret,
418 ret || (val & MAX11410_STATUS_CONV_READY_BIT),
419 5000, MAX11410_CONVERSION_TIMEOUT_MS * 1000,
420 true, st, MAX11410_REG_STATUS, &val);
421 if (ret)
422 return ret;
423 }
424
425 /* Read ADC Data */
426 return max11410_read_reg(st, MAX11410_REG_DATA0, sample_raw);
427}
428
429static int max11410_get_scale(struct max11410_state *state,
430 struct max11410_channel_config cfg)
431{
432 struct regulator *vrefp, *vrefn;
433 int scale;
434
435 vrefp = max11410_get_vrefp(state, cfg.refsel);
436
437 scale = regulator_get_voltage(vrefp) / 1000;
438 vrefn = max11410_get_vrefn(state, cfg.refsel);
439 if (vrefn)
440 scale -= regulator_get_voltage(vrefn) / 1000;
441
442 if (cfg.bipolar)
443 scale *= 2;
444
445 return scale >> cfg.gain;
446}
447
448static int max11410_read_raw(struct iio_dev *indio_dev,
449 struct iio_chan_spec const *chan,
450 int *val, int *val2, long info)
451{
452 struct max11410_state *state = iio_priv(indio_dev);
453 struct max11410_channel_config cfg = state->channels[chan->address];
454 int ret, reg_val, filter, rate;
455
456 switch (info) {
457 case IIO_CHAN_INFO_SCALE:
458 *val = max11410_get_scale(state, cfg);
459 *val2 = chan->scan_type.realbits;
460 return IIO_VAL_FRACTIONAL_LOG2;
461 case IIO_CHAN_INFO_OFFSET:
462 if (cfg.bipolar)
463 *val = -BIT(chan->scan_type.realbits - 1);
464 else
465 *val = 0;
466
467 return IIO_VAL_INT;
468 case IIO_CHAN_INFO_RAW:
469 ret = iio_device_claim_direct_mode(indio_dev);
470 if (ret)
471 return ret;
472
473 mutex_lock(&state->lock);
474
475 ret = max11410_sample(state, ®_val, chan);
476
477 mutex_unlock(&state->lock);
478
479 iio_device_release_direct_mode(indio_dev);
480
481 if (ret)
482 return ret;
483
484 *val = reg_val;
485
486 return IIO_VAL_INT;
487 case IIO_CHAN_INFO_SAMP_FREQ:
488 ret = regmap_read(state->regmap, MAX11410_REG_FILTER, ®_val);
489 if (ret)
490 return ret;
491
492 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);
493 rate = reg_val & MAX11410_FILTER_RATE_MASK;
494 if (rate >= max11410_sampling_len[filter])
495 rate = max11410_sampling_len[filter] - 1;
496
497 *val = max11410_sampling_rates[filter][rate][0];
498 *val2 = max11410_sampling_rates[filter][rate][1];
499
500 return IIO_VAL_INT_PLUS_MICRO;
501 }
502 return -EINVAL;
503}
504
505static int max11410_write_raw(struct iio_dev *indio_dev,
506 struct iio_chan_spec const *chan,
507 int val, int val2, long mask)
508{
509 struct max11410_state *st = iio_priv(indio_dev);
510 int i, ret, reg_val, filter, gain;
511 u32 *scale_avail;
512
513 switch (mask) {
514 case IIO_CHAN_INFO_SCALE:
515 scale_avail = st->channels[chan->address].scale_avail;
516 if (!scale_avail)
517 return -EOPNOTSUPP;
518
519 /* Accept values in range 0.000001 <= scale < 1.000000 */
520 if (val != 0 || val2 == 0)
521 return -EINVAL;
522
523 ret = iio_device_claim_direct_mode(indio_dev);
524 if (ret)
525 return ret;
526
527 /* Convert from INT_PLUS_MICRO to FRACTIONAL_LOG2 */
528 val2 = val2 * DIV_ROUND_CLOSEST(BIT(24), 1000000);
529 val2 = DIV_ROUND_CLOSEST(scale_avail[0], val2);
530 gain = order_base_2(val2);
531
532 st->channels[chan->address].gain = clamp_val(gain, 0, 7);
533
534 iio_device_release_direct_mode(indio_dev);
535
536 return 0;
537 case IIO_CHAN_INFO_SAMP_FREQ:
538 ret = iio_device_claim_direct_mode(indio_dev);
539 if (ret)
540 return ret;
541
542 mutex_lock(&st->lock);
543
544 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val);
545 if (ret)
546 goto out;
547
548 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);
549
550 for (i = 0; i < max11410_sampling_len[filter]; ++i) {
551 if (val == max11410_sampling_rates[filter][i][0] &&
552 val2 == max11410_sampling_rates[filter][i][1])
553 break;
554 }
555 if (i == max11410_sampling_len[filter]) {
556 ret = -EINVAL;
557 goto out;
558 }
559
560 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
561 MAX11410_FILTER_RATE_MASK, i);
562
563out:
564 mutex_unlock(&st->lock);
565 iio_device_release_direct_mode(indio_dev);
566
567 return ret;
568 default:
569 return -EINVAL;
570 }
571}
572
573static int max11410_read_avail(struct iio_dev *indio_dev,
574 struct iio_chan_spec const *chan,
575 const int **vals, int *type, int *length,
576 long info)
577{
578 struct max11410_state *st = iio_priv(indio_dev);
579 struct max11410_channel_config cfg;
580 int ret, reg_val, filter;
581
582 switch (info) {
583 case IIO_CHAN_INFO_SAMP_FREQ:
584 ret = regmap_read(st->regmap, MAX11410_REG_FILTER, ®_val);
585 if (ret)
586 return ret;
587
588 filter = FIELD_GET(MAX11410_FILTER_LINEF_MASK, reg_val);
589
590 *vals = (const int *)max11410_sampling_rates[filter];
591 *length = max11410_sampling_len[filter] * 2;
592 *type = IIO_VAL_INT_PLUS_MICRO;
593
594 return IIO_AVAIL_LIST;
595 case IIO_CHAN_INFO_SCALE:
596 cfg = st->channels[chan->address];
597
598 if (!cfg.scale_avail)
599 return -EINVAL;
600
601 *vals = cfg.scale_avail;
602 *length = MAX11410_SCALE_AVAIL_SIZE * 2;
603 *type = IIO_VAL_FRACTIONAL_LOG2;
604
605 return IIO_AVAIL_LIST;
606 }
607 return -EINVAL;
608}
609
610static const struct iio_info max11410_info = {
611 .read_raw = max11410_read_raw,
612 .write_raw = max11410_write_raw,
613 .read_avail = max11410_read_avail,
614 .attrs = &max11410_attribute_group,
615};
616
617static irqreturn_t max11410_trigger_handler(int irq, void *p)
618{
619 struct iio_poll_func *pf = p;
620 struct iio_dev *indio_dev = pf->indio_dev;
621 struct max11410_state *st = iio_priv(indio_dev);
622 int ret;
623
624 ret = max11410_read_reg(st, MAX11410_REG_DATA0, &st->scan.data);
625 if (ret) {
626 dev_err(&indio_dev->dev, "cannot read data\n");
627 goto out;
628 }
629
630 iio_push_to_buffers_with_timestamp(indio_dev, &st->scan,
631 iio_get_time_ns(indio_dev));
632
633out:
634 iio_trigger_notify_done(indio_dev->trig);
635
636 return IRQ_HANDLED;
637}
638
639static int max11410_buffer_postenable(struct iio_dev *indio_dev)
640{
641 struct max11410_state *st = iio_priv(indio_dev);
642 int scan_ch, ret;
643
644 scan_ch = ffs(*indio_dev->active_scan_mask) - 1;
645
646 ret = max11410_configure_channel(st, &indio_dev->channels[scan_ch]);
647 if (ret)
648 return ret;
649
650 /* Start continuous conversion. */
651 return max11410_write_reg(st, MAX11410_REG_CONV_START,
652 MAX11410_CONV_TYPE_CONTINUOUS);
653}
654
655static int max11410_buffer_predisable(struct iio_dev *indio_dev)
656{
657 struct max11410_state *st = iio_priv(indio_dev);
658
659 /* Stop continuous conversion. */
660 return max11410_write_reg(st, MAX11410_REG_CONV_START,
661 MAX11410_CONV_TYPE_SINGLE);
662}
663
664static const struct iio_buffer_setup_ops max11410_buffer_ops = {
665 .postenable = &max11410_buffer_postenable,
666 .predisable = &max11410_buffer_predisable,
667 .validate_scan_mask = &iio_validate_scan_mask_onehot,
668};
669
670static const struct iio_trigger_ops max11410_trigger_ops = {
671 .validate_device = iio_trigger_validate_own_device,
672};
673
674static irqreturn_t max11410_interrupt(int irq, void *dev_id)
675{
676 struct iio_dev *indio_dev = dev_id;
677 struct max11410_state *st = iio_priv(indio_dev);
678
679 if (iio_buffer_enabled(indio_dev))
680 iio_trigger_poll_chained(st->trig);
681 else
682 complete(&st->completion);
683
684 return IRQ_HANDLED;
685};
686
687static int max11410_parse_channels(struct max11410_state *st,
688 struct iio_dev *indio_dev)
689{
690 struct iio_chan_spec chanspec = chanspec_template;
691 struct device *dev = &st->spi_dev->dev;
692 struct max11410_channel_config *cfg;
693 struct iio_chan_spec *channels;
694 struct fwnode_handle *child;
695 u32 reference, sig_path;
696 const char *node_name;
697 u32 inputs[2], scale;
698 unsigned int num_ch;
699 int chan_idx = 0;
700 int ret, i;
701
702 num_ch = device_get_child_node_count(dev);
703 if (num_ch == 0)
704 return dev_err_probe(&indio_dev->dev, -ENODEV,
705 "FW has no channels defined\n");
706
707 /* Reserve space for soft timestamp channel */
708 num_ch++;
709 channels = devm_kcalloc(dev, num_ch, sizeof(*channels), GFP_KERNEL);
710 if (!channels)
711 return -ENOMEM;
712
713 st->channels = devm_kcalloc(dev, num_ch, sizeof(*st->channels),
714 GFP_KERNEL);
715 if (!st->channels)
716 return -ENOMEM;
717
718 device_for_each_child_node(dev, child) {
719 node_name = fwnode_get_name(child);
720 if (fwnode_property_present(child, "diff-channels")) {
721 ret = fwnode_property_read_u32_array(child,
722 "diff-channels",
723 inputs,
724 ARRAY_SIZE(inputs));
725
726 chanspec.differential = 1;
727 } else {
728 ret = fwnode_property_read_u32(child, "reg", &inputs[0]);
729
730 inputs[1] = 0;
731 chanspec.differential = 0;
732 }
733 if (ret) {
734 fwnode_handle_put(child);
735 return ret;
736 }
737
738 if (inputs[0] > MAX11410_CHANNEL_INDEX_MAX ||
739 inputs[1] > MAX11410_CHANNEL_INDEX_MAX) {
740 fwnode_handle_put(child);
741 return dev_err_probe(&indio_dev->dev, -EINVAL,
742 "Invalid channel index for %s, should be less than %d\n",
743 node_name,
744 MAX11410_CHANNEL_INDEX_MAX + 1);
745 }
746
747 cfg = &st->channels[chan_idx];
748
749 reference = MAX11410_REFSEL_AVDD_AGND;
750 fwnode_property_read_u32(child, "adi,reference", &reference);
751 if (reference > MAX11410_REFSEL_MAX) {
752 fwnode_handle_put(child);
753 return dev_err_probe(&indio_dev->dev, -EINVAL,
754 "Invalid adi,reference value for %s, should be less than %d.\n",
755 node_name, MAX11410_REFSEL_MAX + 1);
756 }
757
758 if (!max11410_get_vrefp(st, reference) ||
759 (!max11410_get_vrefn(st, reference) && reference <= 2)) {
760 fwnode_handle_put(child);
761 return dev_err_probe(&indio_dev->dev, -EINVAL,
762 "Invalid VREF configuration for %s, either specify corresponding VREF regulators or change adi,reference property.\n",
763 node_name);
764 }
765
766 sig_path = MAX11410_PGA_SIG_PATH_BUFFERED;
767 fwnode_property_read_u32(child, "adi,input-mode", &sig_path);
768 if (sig_path > MAX11410_SIG_PATH_MAX) {
769 fwnode_handle_put(child);
770 return dev_err_probe(&indio_dev->dev, -EINVAL,
771 "Invalid adi,input-mode value for %s, should be less than %d.\n",
772 node_name, MAX11410_SIG_PATH_MAX + 1);
773 }
774
775 fwnode_property_read_u32(child, "settling-time-us",
776 &cfg->settling_time_us);
777 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
778 cfg->buffered_vrefp = fwnode_property_read_bool(child, "adi,buffered-vrefp");
779 cfg->buffered_vrefn = fwnode_property_read_bool(child, "adi,buffered-vrefn");
780 cfg->refsel = reference;
781 cfg->sig_path = sig_path;
782 cfg->gain = 0;
783
784 /* Enable scale_available property if input mode is PGA */
785 if (sig_path == MAX11410_PGA_SIG_PATH_PGA) {
786 __set_bit(IIO_CHAN_INFO_SCALE,
787 &chanspec.info_mask_separate_available);
788 cfg->scale_avail = devm_kcalloc(dev, MAX11410_SCALE_AVAIL_SIZE * 2,
789 sizeof(*cfg->scale_avail),
790 GFP_KERNEL);
791 if (!cfg->scale_avail) {
792 fwnode_handle_put(child);
793 return -ENOMEM;
794 }
795
796 scale = max11410_get_scale(st, *cfg);
797 for (i = 0; i < MAX11410_SCALE_AVAIL_SIZE; i++) {
798 cfg->scale_avail[2 * i] = scale >> i;
799 cfg->scale_avail[2 * i + 1] = chanspec.scan_type.realbits;
800 }
801 } else {
802 __clear_bit(IIO_CHAN_INFO_SCALE,
803 &chanspec.info_mask_separate_available);
804 }
805
806 chanspec.address = chan_idx;
807 chanspec.scan_index = chan_idx;
808 chanspec.channel = inputs[0];
809 chanspec.channel2 = inputs[1];
810
811 channels[chan_idx] = chanspec;
812 chan_idx++;
813 }
814
815 channels[chan_idx] = (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(chan_idx);
816
817 indio_dev->num_channels = chan_idx + 1;
818 indio_dev->channels = channels;
819
820 return 0;
821}
822
823static void max11410_disable_reg(void *reg)
824{
825 regulator_disable(reg);
826}
827
828static int max11410_init_vref(struct device *dev,
829 struct regulator **vref,
830 const char *id)
831{
832 struct regulator *reg;
833 int ret;
834
835 reg = devm_regulator_get_optional(dev, id);
836 if (PTR_ERR(reg) == -ENODEV) {
837 *vref = NULL;
838 return 0;
839 } else if (IS_ERR(reg)) {
840 return PTR_ERR(reg);
841 }
842 ret = regulator_enable(reg);
843 if (ret)
844 return dev_err_probe(dev, ret,
845 "Failed to enable regulator %s\n", id);
846
847 *vref = reg;
848 return devm_add_action_or_reset(dev, max11410_disable_reg, reg);
849}
850
851static int max11410_calibrate(struct max11410_state *st, u32 cal_type)
852{
853 int ret, val;
854
855 ret = max11410_write_reg(st, MAX11410_REG_CAL_START, cal_type);
856 if (ret)
857 return ret;
858
859 /* Wait for status register Calibration Ready flag */
860 return read_poll_timeout(max11410_read_reg, ret,
861 ret || (val & MAX11410_STATUS_CAL_READY_BIT),
862 50000, MAX11410_CALIB_TIMEOUT_MS * 1000, true,
863 st, MAX11410_REG_STATUS, &val);
864}
865
866static int max11410_self_calibrate(struct max11410_state *st)
867{
868 int ret, i;
869
870 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
871 MAX11410_FILTER_RATE_MASK,
872 FIELD_PREP(MAX11410_FILTER_RATE_MASK,
873 MAX11410_FILTER_RATE_MAX));
874 if (ret)
875 return ret;
876
877 ret = max11410_calibrate(st, MAX11410_CAL_START_SELF);
878 if (ret)
879 return ret;
880
881 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
882 MAX11410_PGA_SIG_PATH_MASK,
883 FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK,
884 MAX11410_PGA_SIG_PATH_PGA));
885 if (ret)
886 return ret;
887
888 /* PGA calibrations */
889 for (i = 1; i < 8; ++i) {
890 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
891 MAX11410_PGA_GAIN_MASK, i);
892 if (ret)
893 return ret;
894
895 ret = max11410_calibrate(st, MAX11410_CAL_START_PGA);
896 if (ret)
897 return ret;
898 }
899
900 /* Cleanup */
901 ret = regmap_write_bits(st->regmap, MAX11410_REG_PGA,
902 MAX11410_PGA_GAIN_MASK, 0);
903 if (ret)
904 return ret;
905
906 ret = regmap_write_bits(st->regmap, MAX11410_REG_FILTER,
907 MAX11410_FILTER_RATE_MASK, 0);
908 if (ret)
909 return ret;
910
911 return regmap_write_bits(st->regmap, MAX11410_REG_PGA,
912 MAX11410_PGA_SIG_PATH_MASK,
913 FIELD_PREP(MAX11410_PGA_SIG_PATH_MASK,
914 MAX11410_PGA_SIG_PATH_BUFFERED));
915}
916
917static int max11410_probe(struct spi_device *spi)
918{
919 const char *vrefp_regs[] = { "vref0p", "vref1p", "vref2p" };
920 const char *vrefn_regs[] = { "vref0n", "vref1n", "vref2n" };
921 struct device *dev = &spi->dev;
922 struct max11410_state *st;
923 struct iio_dev *indio_dev;
924 int ret, irqs[2];
925 int i;
926
927 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
928 if (!indio_dev)
929 return -ENOMEM;
930
931 st = iio_priv(indio_dev);
932 st->spi_dev = spi;
933 init_completion(&st->completion);
934 mutex_init(&st->lock);
935
936 indio_dev->name = "max11410";
937 indio_dev->modes = INDIO_DIRECT_MODE;
938 indio_dev->info = &max11410_info;
939
940 st->regmap = devm_regmap_init_spi(spi, ®map_config);
941 if (IS_ERR(st->regmap))
942 return dev_err_probe(dev, PTR_ERR(st->regmap),
943 "regmap initialization failed\n");
944
945 ret = max11410_init_vref(dev, &st->avdd, "avdd");
946 if (ret)
947 return ret;
948
949 for (i = 0; i < ARRAY_SIZE(vrefp_regs); i++) {
950 ret = max11410_init_vref(dev, &st->vrefp[i], vrefp_regs[i]);
951 if (ret)
952 return ret;
953
954 ret = max11410_init_vref(dev, &st->vrefn[i], vrefn_regs[i]);
955 if (ret)
956 return ret;
957 }
958
959 /*
960 * Regulators must be configured before parsing channels for
961 * validating "adi,reference" property of each channel.
962 */
963 ret = max11410_parse_channels(st, indio_dev);
964 if (ret)
965 return ret;
966
967 irqs[0] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio0");
968 irqs[1] = fwnode_irq_get_byname(dev_fwnode(dev), "gpio1");
969
970 if (irqs[0] > 0) {
971 st->irq = irqs[0];
972 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(0),
973 MAX11410_GPIO_INTRB);
974 } else if (irqs[1] > 0) {
975 st->irq = irqs[1];
976 ret = regmap_write(st->regmap, MAX11410_REG_GPIO_CTRL(1),
977 MAX11410_GPIO_INTRB);
978 } else if (spi->irq > 0) {
979 return dev_err_probe(dev, -ENODEV,
980 "no interrupt name specified");
981 }
982
983 if (ret)
984 return ret;
985
986 ret = regmap_set_bits(st->regmap, MAX11410_REG_CTRL,
987 MAX11410_CTRL_FORMAT_BIT);
988 if (ret)
989 return ret;
990
991 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
992 &max11410_trigger_handler,
993 &max11410_buffer_ops);
994 if (ret)
995 return ret;
996
997 if (st->irq > 0) {
998 st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
999 indio_dev->name,
1000 iio_device_id(indio_dev));
1001 if (!st->trig)
1002 return -ENOMEM;
1003
1004 st->trig->ops = &max11410_trigger_ops;
1005 ret = devm_iio_trigger_register(dev, st->trig);
1006 if (ret)
1007 return ret;
1008
1009 ret = devm_request_threaded_irq(dev, st->irq, NULL,
1010 &max11410_interrupt,
1011 IRQF_ONESHOT, "max11410",
1012 indio_dev);
1013 if (ret)
1014 return ret;
1015 }
1016
1017 ret = max11410_self_calibrate(st);
1018 if (ret)
1019 return dev_err_probe(dev, ret,
1020 "cannot perform device self calibration\n");
1021
1022 return devm_iio_device_register(dev, indio_dev);
1023}
1024
1025static const struct of_device_id max11410_spi_of_id[] = {
1026 { .compatible = "adi,max11410" },
1027 { }
1028};
1029MODULE_DEVICE_TABLE(of, max11410_spi_of_id);
1030
1031static const struct spi_device_id max11410_id[] = {
1032 { "max11410" },
1033 { }
1034};
1035MODULE_DEVICE_TABLE(spi, max11410_id);
1036
1037static struct spi_driver max11410_driver = {
1038 .driver = {
1039 .name = "max11410",
1040 .of_match_table = max11410_spi_of_id,
1041 },
1042 .probe = max11410_probe,
1043 .id_table = max11410_id,
1044};
1045module_spi_driver(max11410_driver);
1046
1047MODULE_AUTHOR("David Jung <David.Jung@analog.com>");
1048MODULE_AUTHOR("Ibrahim Tilki <Ibrahim.Tilki@analog.com>");
1049MODULE_DESCRIPTION("Analog Devices MAX11410 ADC");
1050MODULE_LICENSE("GPL");