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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm QMP USB3 DP PHY controller (SC7180)
9
10description:
11 The QMP PHY controller supports physical layer functionality for a number of
12 controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
13
14 Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see
15 qcom,sc8280xp-qmp-usb43dp-phy.yaml.
16
17maintainers:
18 - Wesley Cheng <quic_wcheng@quicinc.com>
19
20properties:
21 compatible:
22 enum:
23 - qcom,sc7180-qmp-usb3-dp-phy
24 - qcom,sc7280-qmp-usb3-dp-phy
25 - qcom,sc8180x-qmp-usb3-dp-phy
26 - qcom,sdm845-qmp-usb3-dp-phy
27 - qcom,sm8250-qmp-usb3-dp-phy
28 reg:
29 items:
30 - description: Address and length of PHY's USB serdes block.
31 - description: Address and length of the DP_COM control block.
32 - description: Address and length of PHY's DP serdes block.
33
34 reg-names:
35 items:
36 - const: usb
37 - const: dp_com
38 - const: dp
39
40 "#address-cells":
41 enum: [ 1, 2 ]
42
43 "#size-cells":
44 enum: [ 1, 2 ]
45
46 ranges: true
47
48 clocks:
49 items:
50 - description: Phy aux clock.
51 - description: Phy config clock.
52 - description: 19.2 MHz ref clk.
53 - description: Phy common block aux clock.
54
55 clock-names:
56 items:
57 - const: aux
58 - const: cfg_ahb
59 - const: ref
60 - const: com_aux
61
62 power-domains:
63 maxItems: 1
64
65 resets:
66 items:
67 - description: reset of phy block.
68 - description: phy common block reset.
69
70 reset-names:
71 items:
72 - const: phy
73 - const: common
74
75 vdda-phy-supply:
76 description:
77 Phandle to a regulator supply to PHY core block.
78
79 vdda-pll-supply:
80 description:
81 Phandle to 1.8V regulator supply to PHY refclk pll block.
82
83 vddp-ref-clk-supply:
84 description:
85 Phandle to a regulator supply to any specific refclk pll block.
86
87#Required nodes:
88patternProperties:
89 "^usb3-phy@[0-9a-f]+$":
90 type: object
91 additionalProperties: false
92 description:
93 The USB3 PHY.
94
95 properties:
96 reg:
97 items:
98 - description: Address and length of TX.
99 - description: Address and length of RX.
100 - description: Address and length of PCS.
101 - description: Address and length of TX2.
102 - description: Address and length of RX2.
103 - description: Address and length of pcs_misc.
104
105 clocks:
106 items:
107 - description: pipe clock
108
109 clock-names:
110 deprecated: true
111 items:
112 - const: pipe0
113
114 clock-output-names:
115 items:
116 - const: usb3_phy_pipe_clk_src
117
118 '#clock-cells':
119 const: 0
120
121 '#phy-cells':
122 const: 0
123
124 required:
125 - reg
126 - clocks
127 - '#clock-cells'
128 - '#phy-cells'
129
130 "^dp-phy@[0-9a-f]+$":
131 type: object
132 additionalProperties: false
133 description:
134 The DP PHY.
135
136 properties:
137 reg:
138 items:
139 - description: Address and length of TX.
140 - description: Address and length of RX.
141 - description: Address and length of PCS.
142 - description: Address and length of TX2.
143 - description: Address and length of RX2.
144
145 '#clock-cells':
146 const: 1
147
148 '#phy-cells':
149 const: 0
150
151 required:
152 - reg
153 - '#clock-cells'
154 - '#phy-cells'
155
156required:
157 - compatible
158 - reg
159 - "#address-cells"
160 - "#size-cells"
161 - ranges
162 - clocks
163 - clock-names
164 - resets
165 - reset-names
166 - vdda-phy-supply
167 - vdda-pll-supply
168
169additionalProperties: false
170
171examples:
172 - |
173 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
174 usb_1_qmpphy: phy-wrapper@88e9000 {
175 compatible = "qcom,sdm845-qmp-usb3-dp-phy";
176 reg = <0x088e9000 0x18c>,
177 <0x088e8000 0x10>,
178 <0x088ea000 0x40>;
179 reg-names = "usb", "dp_com", "dp";
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges = <0x0 0x088e9000 0x2000>;
183
184 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
185 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
186 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
187 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
188 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
189
190 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
191 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
192 reset-names = "phy", "common";
193
194 vdda-phy-supply = <&vdda_usb2_ss_1p2>;
195 vdda-pll-supply = <&vdda_usb2_ss_core>;
196
197 usb3-phy@200 {
198 reg = <0x200 0x128>,
199 <0x400 0x200>,
200 <0xc00 0x218>,
201 <0x600 0x128>,
202 <0x800 0x200>,
203 <0xa00 0x100>;
204 #clock-cells = <0>;
205 #phy-cells = <0>;
206 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
207 clock-output-names = "usb3_phy_pipe_clk_src";
208 };
209
210 dp-phy@88ea200 {
211 reg = <0xa200 0x200>,
212 <0xa400 0x200>,
213 <0xaa00 0x200>,
214 <0xa600 0x200>,
215 <0xa800 0x200>;
216 #clock-cells = <1>;
217 #phy-cells = <0>;
218 };
219 };