tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver
4 *
5 * Copyright (c) 2021, Linaro Ltd.
6 *
7 */
8
9#include <dt-bindings/interconnect/qcom,qcm2290.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/interconnect-provider.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/of_platform.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20
21#include "icc-rpm.h"
22#include "smd-rpm.h"
23
24enum {
25 QCM2290_MASTER_APPSS_PROC = 1,
26 QCM2290_MASTER_SNOC_BIMC_RT,
27 QCM2290_MASTER_SNOC_BIMC_NRT,
28 QCM2290_MASTER_SNOC_BIMC,
29 QCM2290_MASTER_TCU_0,
30 QCM2290_MASTER_GFX3D,
31 QCM2290_MASTER_SNOC_CNOC,
32 QCM2290_MASTER_QDSS_DAP,
33 QCM2290_MASTER_CRYPTO_CORE0,
34 QCM2290_MASTER_SNOC_CFG,
35 QCM2290_MASTER_TIC,
36 QCM2290_MASTER_ANOC_SNOC,
37 QCM2290_MASTER_BIMC_SNOC,
38 QCM2290_MASTER_PIMEM,
39 QCM2290_MASTER_QDSS_BAM,
40 QCM2290_MASTER_QUP_0,
41 QCM2290_MASTER_IPA,
42 QCM2290_MASTER_QDSS_ETR,
43 QCM2290_MASTER_SDCC_1,
44 QCM2290_MASTER_SDCC_2,
45 QCM2290_MASTER_QPIC,
46 QCM2290_MASTER_USB3_0,
47 QCM2290_MASTER_QUP_CORE_0,
48 QCM2290_MASTER_CAMNOC_SF,
49 QCM2290_MASTER_VIDEO_P0,
50 QCM2290_MASTER_VIDEO_PROC,
51 QCM2290_MASTER_CAMNOC_HF,
52 QCM2290_MASTER_MDP0,
53
54 QCM2290_SLAVE_EBI1,
55 QCM2290_SLAVE_BIMC_SNOC,
56 QCM2290_SLAVE_BIMC_CFG,
57 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
58 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
59 QCM2290_SLAVE_CAMERA_CFG,
60 QCM2290_SLAVE_CLK_CTL,
61 QCM2290_SLAVE_CRYPTO_0_CFG,
62 QCM2290_SLAVE_DISPLAY_CFG,
63 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
64 QCM2290_SLAVE_GPU_CFG,
65 QCM2290_SLAVE_HWKM,
66 QCM2290_SLAVE_IMEM_CFG,
67 QCM2290_SLAVE_IPA_CFG,
68 QCM2290_SLAVE_LPASS,
69 QCM2290_SLAVE_MESSAGE_RAM,
70 QCM2290_SLAVE_PDM,
71 QCM2290_SLAVE_PIMEM_CFG,
72 QCM2290_SLAVE_PKA_WRAPPER,
73 QCM2290_SLAVE_PMIC_ARB,
74 QCM2290_SLAVE_PRNG,
75 QCM2290_SLAVE_QDSS_CFG,
76 QCM2290_SLAVE_QM_CFG,
77 QCM2290_SLAVE_QM_MPU_CFG,
78 QCM2290_SLAVE_QPIC,
79 QCM2290_SLAVE_QUP_0,
80 QCM2290_SLAVE_SDCC_1,
81 QCM2290_SLAVE_SDCC_2,
82 QCM2290_SLAVE_SNOC_CFG,
83 QCM2290_SLAVE_TCSR,
84 QCM2290_SLAVE_USB3,
85 QCM2290_SLAVE_VENUS_CFG,
86 QCM2290_SLAVE_VENUS_THROTTLE_CFG,
87 QCM2290_SLAVE_VSENSE_CTRL_CFG,
88 QCM2290_SLAVE_SERVICE_CNOC,
89 QCM2290_SLAVE_APPSS,
90 QCM2290_SLAVE_SNOC_CNOC,
91 QCM2290_SLAVE_IMEM,
92 QCM2290_SLAVE_PIMEM,
93 QCM2290_SLAVE_SNOC_BIMC,
94 QCM2290_SLAVE_SERVICE_SNOC,
95 QCM2290_SLAVE_QDSS_STM,
96 QCM2290_SLAVE_TCU,
97 QCM2290_SLAVE_ANOC_SNOC,
98 QCM2290_SLAVE_QUP_CORE_0,
99 QCM2290_SLAVE_SNOC_BIMC_NRT,
100 QCM2290_SLAVE_SNOC_BIMC_RT,
101};
102
103/* Master nodes */
104static const u16 mas_appss_proc_links[] = {
105 QCM2290_SLAVE_EBI1,
106 QCM2290_SLAVE_BIMC_SNOC,
107};
108
109static struct qcom_icc_node mas_appss_proc = {
110 .id = QCM2290_MASTER_APPSS_PROC,
111 .name = "mas_apps_proc",
112 .buswidth = 16,
113 .qos.ap_owned = true,
114 .qos.qos_port = 0,
115 .qos.qos_mode = NOC_QOS_MODE_FIXED,
116 .qos.prio_level = 0,
117 .qos.areq_prio = 0,
118 .mas_rpm_id = 0,
119 .slv_rpm_id = -1,
120 .num_links = ARRAY_SIZE(mas_appss_proc_links),
121 .links = mas_appss_proc_links,
122};
123
124static const u16 mas_snoc_bimc_rt_links[] = {
125 QCM2290_SLAVE_EBI1,
126};
127
128static struct qcom_icc_node mas_snoc_bimc_rt = {
129 .id = QCM2290_MASTER_SNOC_BIMC_RT,
130 .name = "mas_snoc_bimc_rt",
131 .buswidth = 16,
132 .qos.ap_owned = true,
133 .qos.qos_port = 2,
134 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
135 .mas_rpm_id = 163,
136 .slv_rpm_id = -1,
137 .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links),
138 .links = mas_snoc_bimc_rt_links,
139};
140
141static const u16 mas_snoc_bimc_nrt_links[] = {
142 QCM2290_SLAVE_EBI1,
143};
144
145static struct qcom_icc_node mas_snoc_bimc_nrt = {
146 .id = QCM2290_MASTER_SNOC_BIMC_NRT,
147 .name = "mas_snoc_bimc_nrt",
148 .buswidth = 16,
149 .qos.ap_owned = true,
150 .qos.qos_port = 2,
151 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
152 .mas_rpm_id = 163,
153 .slv_rpm_id = -1,
154 .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links),
155 .links = mas_snoc_bimc_nrt_links,
156};
157
158static const u16 mas_snoc_bimc_links[] = {
159 QCM2290_SLAVE_EBI1,
160};
161
162static struct qcom_icc_node mas_snoc_bimc = {
163 .id = QCM2290_MASTER_SNOC_BIMC,
164 .name = "mas_snoc_bimc",
165 .buswidth = 16,
166 .qos.ap_owned = true,
167 .qos.qos_port = 2,
168 .qos.qos_mode = NOC_QOS_MODE_BYPASS,
169 .mas_rpm_id = 164,
170 .slv_rpm_id = -1,
171 .num_links = ARRAY_SIZE(mas_snoc_bimc_links),
172 .links = mas_snoc_bimc_links,
173};
174
175static const u16 mas_tcu_0_links[] = {
176 QCM2290_SLAVE_EBI1,
177 QCM2290_SLAVE_BIMC_SNOC,
178};
179
180static struct qcom_icc_node mas_tcu_0 = {
181 .id = QCM2290_MASTER_TCU_0,
182 .name = "mas_tcu_0",
183 .buswidth = 8,
184 .qos.ap_owned = true,
185 .qos.qos_port = 4,
186 .qos.qos_mode = NOC_QOS_MODE_FIXED,
187 .qos.prio_level = 6,
188 .qos.areq_prio = 6,
189 .mas_rpm_id = 102,
190 .slv_rpm_id = -1,
191 .num_links = ARRAY_SIZE(mas_tcu_0_links),
192 .links = mas_tcu_0_links,
193};
194
195static const u16 mas_snoc_cnoc_links[] = {
196 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
197 QCM2290_SLAVE_SDCC_2,
198 QCM2290_SLAVE_SDCC_1,
199 QCM2290_SLAVE_QM_CFG,
200 QCM2290_SLAVE_BIMC_CFG,
201 QCM2290_SLAVE_USB3,
202 QCM2290_SLAVE_QM_MPU_CFG,
203 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
204 QCM2290_SLAVE_QDSS_CFG,
205 QCM2290_SLAVE_PDM,
206 QCM2290_SLAVE_IPA_CFG,
207 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
208 QCM2290_SLAVE_TCSR,
209 QCM2290_SLAVE_MESSAGE_RAM,
210 QCM2290_SLAVE_PMIC_ARB,
211 QCM2290_SLAVE_LPASS,
212 QCM2290_SLAVE_DISPLAY_CFG,
213 QCM2290_SLAVE_VENUS_CFG,
214 QCM2290_SLAVE_GPU_CFG,
215 QCM2290_SLAVE_IMEM_CFG,
216 QCM2290_SLAVE_SNOC_CFG,
217 QCM2290_SLAVE_SERVICE_CNOC,
218 QCM2290_SLAVE_VENUS_THROTTLE_CFG,
219 QCM2290_SLAVE_PKA_WRAPPER,
220 QCM2290_SLAVE_HWKM,
221 QCM2290_SLAVE_PRNG,
222 QCM2290_SLAVE_VSENSE_CTRL_CFG,
223 QCM2290_SLAVE_CRYPTO_0_CFG,
224 QCM2290_SLAVE_PIMEM_CFG,
225 QCM2290_SLAVE_QUP_0,
226 QCM2290_SLAVE_CAMERA_CFG,
227 QCM2290_SLAVE_CLK_CTL,
228 QCM2290_SLAVE_QPIC,
229};
230
231static struct qcom_icc_node mas_snoc_cnoc = {
232 .id = QCM2290_MASTER_SNOC_CNOC,
233 .name = "mas_snoc_cnoc",
234 .buswidth = 8,
235 .qos.ap_owned = true,
236 .qos.qos_mode = NOC_QOS_MODE_INVALID,
237 .mas_rpm_id = 52,
238 .slv_rpm_id = -1,
239 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links),
240 .links = mas_snoc_cnoc_links,
241};
242
243static const u16 mas_qdss_dap_links[] = {
244 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
245 QCM2290_SLAVE_SDCC_2,
246 QCM2290_SLAVE_SDCC_1,
247 QCM2290_SLAVE_QM_CFG,
248 QCM2290_SLAVE_BIMC_CFG,
249 QCM2290_SLAVE_USB3,
250 QCM2290_SLAVE_QM_MPU_CFG,
251 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
252 QCM2290_SLAVE_QDSS_CFG,
253 QCM2290_SLAVE_PDM,
254 QCM2290_SLAVE_IPA_CFG,
255 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
256 QCM2290_SLAVE_TCSR,
257 QCM2290_SLAVE_MESSAGE_RAM,
258 QCM2290_SLAVE_PMIC_ARB,
259 QCM2290_SLAVE_LPASS,
260 QCM2290_SLAVE_DISPLAY_CFG,
261 QCM2290_SLAVE_VENUS_CFG,
262 QCM2290_SLAVE_GPU_CFG,
263 QCM2290_SLAVE_IMEM_CFG,
264 QCM2290_SLAVE_SNOC_CFG,
265 QCM2290_SLAVE_SERVICE_CNOC,
266 QCM2290_SLAVE_VENUS_THROTTLE_CFG,
267 QCM2290_SLAVE_PKA_WRAPPER,
268 QCM2290_SLAVE_HWKM,
269 QCM2290_SLAVE_PRNG,
270 QCM2290_SLAVE_VSENSE_CTRL_CFG,
271 QCM2290_SLAVE_CRYPTO_0_CFG,
272 QCM2290_SLAVE_PIMEM_CFG,
273 QCM2290_SLAVE_QUP_0,
274 QCM2290_SLAVE_CAMERA_CFG,
275 QCM2290_SLAVE_CLK_CTL,
276 QCM2290_SLAVE_QPIC,
277};
278
279static struct qcom_icc_node mas_qdss_dap = {
280 .id = QCM2290_MASTER_QDSS_DAP,
281 .name = "mas_qdss_dap",
282 .buswidth = 8,
283 .qos.ap_owned = true,
284 .qos.qos_mode = NOC_QOS_MODE_INVALID,
285 .mas_rpm_id = 49,
286 .slv_rpm_id = -1,
287 .num_links = ARRAY_SIZE(mas_qdss_dap_links),
288 .links = mas_qdss_dap_links,
289};
290
291static const u16 mas_crypto_core0_links[] = {
292 QCM2290_SLAVE_ANOC_SNOC
293};
294
295static struct qcom_icc_node mas_crypto_core0 = {
296 .id = QCM2290_MASTER_CRYPTO_CORE0,
297 .name = "mas_crypto_core0",
298 .buswidth = 8,
299 .qos.ap_owned = true,
300 .qos.qos_port = 22,
301 .qos.qos_mode = NOC_QOS_MODE_FIXED,
302 .qos.areq_prio = 2,
303 .mas_rpm_id = 23,
304 .slv_rpm_id = -1,
305 .num_links = ARRAY_SIZE(mas_crypto_core0_links),
306 .links = mas_crypto_core0_links,
307};
308
309static const u16 mas_qup_core_0_links[] = {
310 QCM2290_SLAVE_QUP_CORE_0,
311};
312
313static struct qcom_icc_node mas_qup_core_0 = {
314 .id = QCM2290_MASTER_QUP_CORE_0,
315 .name = "mas_qup_core_0",
316 .buswidth = 4,
317 .mas_rpm_id = 170,
318 .slv_rpm_id = -1,
319 .num_links = ARRAY_SIZE(mas_qup_core_0_links),
320 .links = mas_qup_core_0_links,
321};
322
323static const u16 mas_camnoc_sf_links[] = {
324 QCM2290_SLAVE_SNOC_BIMC_NRT,
325};
326
327static struct qcom_icc_node mas_camnoc_sf = {
328 .id = QCM2290_MASTER_CAMNOC_SF,
329 .name = "mas_camnoc_sf",
330 .buswidth = 32,
331 .qos.ap_owned = true,
332 .qos.qos_port = 4,
333 .qos.qos_mode = NOC_QOS_MODE_FIXED,
334 .qos.areq_prio = 3,
335 .mas_rpm_id = 172,
336 .slv_rpm_id = -1,
337 .num_links = ARRAY_SIZE(mas_camnoc_sf_links),
338 .links = mas_camnoc_sf_links,
339};
340
341static const u16 mas_camnoc_hf_links[] = {
342 QCM2290_SLAVE_SNOC_BIMC_RT,
343};
344
345static struct qcom_icc_node mas_camnoc_hf = {
346 .id = QCM2290_MASTER_CAMNOC_HF,
347 .name = "mas_camnoc_hf",
348 .buswidth = 32,
349 .qos.ap_owned = true,
350 .qos.qos_port = 10,
351 .qos.qos_mode = NOC_QOS_MODE_FIXED,
352 .qos.areq_prio = 3,
353 .qos.urg_fwd_en = true,
354 .mas_rpm_id = 173,
355 .slv_rpm_id = -1,
356 .num_links = ARRAY_SIZE(mas_camnoc_hf_links),
357 .links = mas_camnoc_hf_links,
358};
359
360static const u16 mas_mdp0_links[] = {
361 QCM2290_SLAVE_SNOC_BIMC_RT,
362};
363
364static struct qcom_icc_node mas_mdp0 = {
365 .id = QCM2290_MASTER_MDP0,
366 .name = "mas_mdp0",
367 .buswidth = 16,
368 .qos.ap_owned = true,
369 .qos.qos_port = 5,
370 .qos.qos_mode = NOC_QOS_MODE_FIXED,
371 .qos.areq_prio = 3,
372 .qos.urg_fwd_en = true,
373 .mas_rpm_id = 8,
374 .slv_rpm_id = -1,
375 .num_links = ARRAY_SIZE(mas_mdp0_links),
376 .links = mas_mdp0_links,
377};
378
379static const u16 mas_video_p0_links[] = {
380 QCM2290_SLAVE_SNOC_BIMC_NRT,
381};
382
383static struct qcom_icc_node mas_video_p0 = {
384 .id = QCM2290_MASTER_VIDEO_P0,
385 .name = "mas_video_p0",
386 .buswidth = 16,
387 .qos.ap_owned = true,
388 .qos.qos_port = 9,
389 .qos.qos_mode = NOC_QOS_MODE_FIXED,
390 .qos.areq_prio = 3,
391 .qos.urg_fwd_en = true,
392 .mas_rpm_id = 9,
393 .slv_rpm_id = -1,
394 .num_links = ARRAY_SIZE(mas_video_p0_links),
395 .links = mas_video_p0_links,
396};
397
398static const u16 mas_video_proc_links[] = {
399 QCM2290_SLAVE_SNOC_BIMC_NRT,
400};
401
402static struct qcom_icc_node mas_video_proc = {
403 .id = QCM2290_MASTER_VIDEO_PROC,
404 .name = "mas_video_proc",
405 .buswidth = 8,
406 .qos.ap_owned = true,
407 .qos.qos_port = 13,
408 .qos.qos_mode = NOC_QOS_MODE_FIXED,
409 .qos.areq_prio = 4,
410 .mas_rpm_id = 168,
411 .slv_rpm_id = -1,
412 .num_links = ARRAY_SIZE(mas_video_proc_links),
413 .links = mas_video_proc_links,
414};
415
416static const u16 mas_snoc_cfg_links[] = {
417 QCM2290_SLAVE_SERVICE_SNOC,
418};
419
420static struct qcom_icc_node mas_snoc_cfg = {
421 .id = QCM2290_MASTER_SNOC_CFG,
422 .name = "mas_snoc_cfg",
423 .buswidth = 4,
424 .qos.ap_owned = true,
425 .qos.qos_mode = NOC_QOS_MODE_INVALID,
426 .mas_rpm_id = 20,
427 .slv_rpm_id = -1,
428 .num_links = ARRAY_SIZE(mas_snoc_cfg_links),
429 .links = mas_snoc_cfg_links,
430};
431
432static const u16 mas_tic_links[] = {
433 QCM2290_SLAVE_PIMEM,
434 QCM2290_SLAVE_IMEM,
435 QCM2290_SLAVE_APPSS,
436 QCM2290_SLAVE_SNOC_BIMC,
437 QCM2290_SLAVE_SNOC_CNOC,
438 QCM2290_SLAVE_TCU,
439 QCM2290_SLAVE_QDSS_STM,
440};
441
442static struct qcom_icc_node mas_tic = {
443 .id = QCM2290_MASTER_TIC,
444 .name = "mas_tic",
445 .buswidth = 4,
446 .qos.ap_owned = true,
447 .qos.qos_port = 8,
448 .qos.qos_mode = NOC_QOS_MODE_FIXED,
449 .qos.areq_prio = 2,
450 .mas_rpm_id = 51,
451 .slv_rpm_id = -1,
452 .num_links = ARRAY_SIZE(mas_tic_links),
453 .links = mas_tic_links,
454};
455
456static const u16 mas_anoc_snoc_links[] = {
457 QCM2290_SLAVE_PIMEM,
458 QCM2290_SLAVE_IMEM,
459 QCM2290_SLAVE_APPSS,
460 QCM2290_SLAVE_SNOC_BIMC,
461 QCM2290_SLAVE_SNOC_CNOC,
462 QCM2290_SLAVE_TCU,
463 QCM2290_SLAVE_QDSS_STM,
464};
465
466static struct qcom_icc_node mas_anoc_snoc = {
467 .id = QCM2290_MASTER_ANOC_SNOC,
468 .name = "mas_anoc_snoc",
469 .buswidth = 16,
470 .mas_rpm_id = 110,
471 .slv_rpm_id = -1,
472 .num_links = ARRAY_SIZE(mas_anoc_snoc_links),
473 .links = mas_anoc_snoc_links,
474};
475
476static const u16 mas_bimc_snoc_links[] = {
477 QCM2290_SLAVE_PIMEM,
478 QCM2290_SLAVE_IMEM,
479 QCM2290_SLAVE_APPSS,
480 QCM2290_SLAVE_SNOC_CNOC,
481 QCM2290_SLAVE_TCU,
482 QCM2290_SLAVE_QDSS_STM,
483};
484
485static struct qcom_icc_node mas_bimc_snoc = {
486 .id = QCM2290_MASTER_BIMC_SNOC,
487 .name = "mas_bimc_snoc",
488 .buswidth = 8,
489 .mas_rpm_id = 21,
490 .slv_rpm_id = -1,
491 .num_links = ARRAY_SIZE(mas_bimc_snoc_links),
492 .links = mas_bimc_snoc_links,
493};
494
495static const u16 mas_pimem_links[] = {
496 QCM2290_SLAVE_IMEM,
497 QCM2290_SLAVE_SNOC_BIMC,
498};
499
500static struct qcom_icc_node mas_pimem = {
501 .id = QCM2290_MASTER_PIMEM,
502 .name = "mas_pimem",
503 .buswidth = 8,
504 .qos.ap_owned = true,
505 .qos.qos_port = 20,
506 .qos.qos_mode = NOC_QOS_MODE_FIXED,
507 .qos.areq_prio = 2,
508 .mas_rpm_id = 113,
509 .slv_rpm_id = -1,
510 .num_links = ARRAY_SIZE(mas_pimem_links),
511 .links = mas_pimem_links,
512};
513
514static const u16 mas_qdss_bam_links[] = {
515 QCM2290_SLAVE_ANOC_SNOC,
516};
517
518static struct qcom_icc_node mas_qdss_bam = {
519 .id = QCM2290_MASTER_QDSS_BAM,
520 .name = "mas_qdss_bam",
521 .buswidth = 4,
522 .qos.ap_owned = true,
523 .qos.qos_port = 2,
524 .qos.qos_mode = NOC_QOS_MODE_FIXED,
525 .qos.areq_prio = 2,
526 .mas_rpm_id = 19,
527 .slv_rpm_id = -1,
528 .num_links = ARRAY_SIZE(mas_qdss_bam_links),
529 .links = mas_qdss_bam_links,
530};
531
532static const u16 mas_qup_0_links[] = {
533 QCM2290_SLAVE_ANOC_SNOC,
534};
535
536static struct qcom_icc_node mas_qup_0 = {
537 .id = QCM2290_MASTER_QUP_0,
538 .name = "mas_qup_0",
539 .buswidth = 4,
540 .qos.ap_owned = true,
541 .qos.qos_port = 0,
542 .qos.qos_mode = NOC_QOS_MODE_FIXED,
543 .qos.areq_prio = 2,
544 .mas_rpm_id = 166,
545 .slv_rpm_id = -1,
546 .num_links = ARRAY_SIZE(mas_qup_0_links),
547 .links = mas_qup_0_links,
548};
549
550static const u16 mas_ipa_links[] = {
551 QCM2290_SLAVE_ANOC_SNOC,
552};
553
554static struct qcom_icc_node mas_ipa = {
555 .id = QCM2290_MASTER_IPA,
556 .name = "mas_ipa",
557 .buswidth = 8,
558 .qos.ap_owned = true,
559 .qos.qos_port = 3,
560 .qos.qos_mode = NOC_QOS_MODE_FIXED,
561 .qos.areq_prio = 2,
562 .mas_rpm_id = 59,
563 .slv_rpm_id = -1,
564 .num_links = ARRAY_SIZE(mas_ipa_links),
565 .links = mas_ipa_links,
566};
567
568static const u16 mas_qdss_etr_links[] = {
569 QCM2290_SLAVE_ANOC_SNOC,
570};
571
572static struct qcom_icc_node mas_qdss_etr = {
573 .id = QCM2290_MASTER_QDSS_ETR,
574 .name = "mas_qdss_etr",
575 .buswidth = 8,
576 .qos.ap_owned = true,
577 .qos.qos_port = 12,
578 .qos.qos_mode = NOC_QOS_MODE_FIXED,
579 .qos.areq_prio = 2,
580 .mas_rpm_id = 31,
581 .slv_rpm_id = -1,
582 .num_links = ARRAY_SIZE(mas_qdss_etr_links),
583 .links = mas_qdss_etr_links,
584};
585
586static const u16 mas_sdcc_1_links[] = {
587 QCM2290_SLAVE_ANOC_SNOC,
588};
589
590static struct qcom_icc_node mas_sdcc_1 = {
591 .id = QCM2290_MASTER_SDCC_1,
592 .name = "mas_sdcc_1",
593 .buswidth = 8,
594 .qos.ap_owned = true,
595 .qos.qos_port = 17,
596 .qos.qos_mode = NOC_QOS_MODE_FIXED,
597 .qos.areq_prio = 2,
598 .mas_rpm_id = 33,
599 .slv_rpm_id = -1,
600 .num_links = ARRAY_SIZE(mas_sdcc_1_links),
601 .links = mas_sdcc_1_links,
602};
603
604static const u16 mas_sdcc_2_links[] = {
605 QCM2290_SLAVE_ANOC_SNOC,
606};
607
608static struct qcom_icc_node mas_sdcc_2 = {
609 .id = QCM2290_MASTER_SDCC_2,
610 .name = "mas_sdcc_2",
611 .buswidth = 8,
612 .qos.ap_owned = true,
613 .qos.qos_port = 23,
614 .qos.qos_mode = NOC_QOS_MODE_FIXED,
615 .qos.areq_prio = 2,
616 .mas_rpm_id = 35,
617 .slv_rpm_id = -1,
618 .num_links = ARRAY_SIZE(mas_sdcc_2_links),
619 .links = mas_sdcc_2_links,
620};
621
622static const u16 mas_qpic_links[] = {
623 QCM2290_SLAVE_ANOC_SNOC,
624};
625
626static struct qcom_icc_node mas_qpic = {
627 .id = QCM2290_MASTER_QPIC,
628 .name = "mas_qpic",
629 .buswidth = 4,
630 .qos.ap_owned = true,
631 .qos.qos_port = 1,
632 .qos.qos_mode = NOC_QOS_MODE_FIXED,
633 .qos.areq_prio = 2,
634 .mas_rpm_id = 58,
635 .slv_rpm_id = -1,
636 .num_links = ARRAY_SIZE(mas_qpic_links),
637 .links = mas_qpic_links,
638};
639
640static const u16 mas_usb3_0_links[] = {
641 QCM2290_SLAVE_ANOC_SNOC,
642};
643
644static struct qcom_icc_node mas_usb3_0 = {
645 .id = QCM2290_MASTER_USB3_0,
646 .name = "mas_usb3_0",
647 .buswidth = 8,
648 .qos.ap_owned = true,
649 .qos.qos_port = 24,
650 .qos.qos_mode = NOC_QOS_MODE_FIXED,
651 .qos.areq_prio = 2,
652 .mas_rpm_id = 32,
653 .slv_rpm_id = -1,
654 .num_links = ARRAY_SIZE(mas_usb3_0_links),
655 .links = mas_usb3_0_links,
656};
657
658static const u16 mas_gfx3d_links[] = {
659 QCM2290_SLAVE_EBI1,
660};
661
662static struct qcom_icc_node mas_gfx3d = {
663 .id = QCM2290_MASTER_GFX3D,
664 .name = "mas_gfx3d",
665 .buswidth = 32,
666 .qos.ap_owned = true,
667 .qos.qos_port = 1,
668 .qos.qos_mode = NOC_QOS_MODE_FIXED,
669 .qos.prio_level = 0,
670 .qos.areq_prio = 0,
671 .mas_rpm_id = 6,
672 .slv_rpm_id = -1,
673 .num_links = ARRAY_SIZE(mas_gfx3d_links),
674 .links = mas_gfx3d_links,
675};
676
677/* Slave nodes */
678static struct qcom_icc_node slv_ebi1 = {
679 .name = "slv_ebi1",
680 .id = QCM2290_SLAVE_EBI1,
681 .buswidth = 8,
682 .mas_rpm_id = -1,
683 .slv_rpm_id = 0,
684};
685
686static const u16 slv_bimc_snoc_links[] = {
687 QCM2290_MASTER_BIMC_SNOC,
688};
689
690static struct qcom_icc_node slv_bimc_snoc = {
691 .name = "slv_bimc_snoc",
692 .id = QCM2290_SLAVE_BIMC_SNOC,
693 .buswidth = 8,
694 .mas_rpm_id = -1,
695 .slv_rpm_id = 2,
696 .num_links = ARRAY_SIZE(slv_bimc_snoc_links),
697 .links = slv_bimc_snoc_links,
698};
699
700static struct qcom_icc_node slv_bimc_cfg = {
701 .name = "slv_bimc_cfg",
702 .id = QCM2290_SLAVE_BIMC_CFG,
703 .buswidth = 4,
704 .qos.ap_owned = true,
705 .qos.qos_mode = NOC_QOS_MODE_INVALID,
706 .mas_rpm_id = -1,
707 .slv_rpm_id = 56,
708};
709
710static struct qcom_icc_node slv_camera_nrt_throttle_cfg = {
711 .name = "slv_camera_nrt_throttle_cfg",
712 .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG,
713 .buswidth = 4,
714 .qos.ap_owned = true,
715 .qos.qos_mode = NOC_QOS_MODE_INVALID,
716 .mas_rpm_id = -1,
717 .slv_rpm_id = 271,
718};
719
720static struct qcom_icc_node slv_camera_rt_throttle_cfg = {
721 .name = "slv_camera_rt_throttle_cfg",
722 .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG,
723 .buswidth = 4,
724 .qos.ap_owned = true,
725 .qos.qos_mode = NOC_QOS_MODE_INVALID,
726 .mas_rpm_id = -1,
727 .slv_rpm_id = 279,
728};
729
730static struct qcom_icc_node slv_camera_cfg = {
731 .name = "slv_camera_cfg",
732 .id = QCM2290_SLAVE_CAMERA_CFG,
733 .buswidth = 4,
734 .qos.ap_owned = true,
735 .qos.qos_mode = NOC_QOS_MODE_INVALID,
736 .mas_rpm_id = -1,
737 .slv_rpm_id = 3,
738};
739
740static struct qcom_icc_node slv_clk_ctl = {
741 .name = "slv_clk_ctl",
742 .id = QCM2290_SLAVE_CLK_CTL,
743 .buswidth = 4,
744 .qos.ap_owned = true,
745 .qos.qos_mode = NOC_QOS_MODE_INVALID,
746 .mas_rpm_id = -1,
747 .slv_rpm_id = 47,
748};
749
750static struct qcom_icc_node slv_crypto_0_cfg = {
751 .name = "slv_crypto_0_cfg",
752 .id = QCM2290_SLAVE_CRYPTO_0_CFG,
753 .buswidth = 4,
754 .qos.ap_owned = true,
755 .qos.qos_mode = NOC_QOS_MODE_INVALID,
756 .mas_rpm_id = -1,
757 .slv_rpm_id = 52,
758};
759
760static struct qcom_icc_node slv_display_cfg = {
761 .name = "slv_display_cfg",
762 .id = QCM2290_SLAVE_DISPLAY_CFG,
763 .buswidth = 4,
764 .qos.ap_owned = true,
765 .qos.qos_mode = NOC_QOS_MODE_INVALID,
766 .mas_rpm_id = -1,
767 .slv_rpm_id = 4,
768};
769
770static struct qcom_icc_node slv_display_throttle_cfg = {
771 .name = "slv_display_throttle_cfg",
772 .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG,
773 .buswidth = 4,
774 .qos.ap_owned = true,
775 .qos.qos_mode = NOC_QOS_MODE_INVALID,
776 .mas_rpm_id = -1,
777 .slv_rpm_id = 156,
778};
779
780static struct qcom_icc_node slv_gpu_cfg = {
781 .name = "slv_gpu_cfg",
782 .id = QCM2290_SLAVE_GPU_CFG,
783 .buswidth = 8,
784 .qos.ap_owned = true,
785 .qos.qos_mode = NOC_QOS_MODE_INVALID,
786 .mas_rpm_id = -1,
787 .slv_rpm_id = 275,
788};
789
790static struct qcom_icc_node slv_hwkm = {
791 .name = "slv_hwkm",
792 .id = QCM2290_SLAVE_HWKM,
793 .buswidth = 4,
794 .qos.ap_owned = true,
795 .qos.qos_mode = NOC_QOS_MODE_INVALID,
796 .mas_rpm_id = -1,
797 .slv_rpm_id = 280,
798};
799
800static struct qcom_icc_node slv_imem_cfg = {
801 .name = "slv_imem_cfg",
802 .id = QCM2290_SLAVE_IMEM_CFG,
803 .buswidth = 4,
804 .qos.ap_owned = true,
805 .qos.qos_mode = NOC_QOS_MODE_INVALID,
806 .mas_rpm_id = -1,
807 .slv_rpm_id = 54,
808};
809
810static struct qcom_icc_node slv_ipa_cfg = {
811 .name = "slv_ipa_cfg",
812 .id = QCM2290_SLAVE_IPA_CFG,
813 .buswidth = 4,
814 .qos.ap_owned = true,
815 .qos.qos_mode = NOC_QOS_MODE_INVALID,
816 .mas_rpm_id = -1,
817 .slv_rpm_id = 183,
818};
819
820static struct qcom_icc_node slv_lpass = {
821 .name = "slv_lpass",
822 .id = QCM2290_SLAVE_LPASS,
823 .buswidth = 4,
824 .qos.ap_owned = true,
825 .qos.qos_mode = NOC_QOS_MODE_INVALID,
826 .mas_rpm_id = -1,
827 .slv_rpm_id = 21,
828};
829
830static struct qcom_icc_node slv_message_ram = {
831 .name = "slv_message_ram",
832 .id = QCM2290_SLAVE_MESSAGE_RAM,
833 .buswidth = 4,
834 .qos.ap_owned = true,
835 .qos.qos_mode = NOC_QOS_MODE_INVALID,
836 .mas_rpm_id = -1,
837 .slv_rpm_id = 55,
838};
839
840static struct qcom_icc_node slv_pdm = {
841 .name = "slv_pdm",
842 .id = QCM2290_SLAVE_PDM,
843 .buswidth = 4,
844 .qos.ap_owned = true,
845 .qos.qos_mode = NOC_QOS_MODE_INVALID,
846 .mas_rpm_id = -1,
847 .slv_rpm_id = 41,
848};
849
850static struct qcom_icc_node slv_pimem_cfg = {
851 .name = "slv_pimem_cfg",
852 .id = QCM2290_SLAVE_PIMEM_CFG,
853 .buswidth = 4,
854 .qos.ap_owned = true,
855 .qos.qos_mode = NOC_QOS_MODE_INVALID,
856 .mas_rpm_id = -1,
857 .slv_rpm_id = 167,
858};
859
860static struct qcom_icc_node slv_pka_wrapper = {
861 .name = "slv_pka_wrapper",
862 .id = QCM2290_SLAVE_PKA_WRAPPER,
863 .buswidth = 4,
864 .qos.ap_owned = true,
865 .qos.qos_mode = NOC_QOS_MODE_INVALID,
866 .mas_rpm_id = -1,
867 .slv_rpm_id = 281,
868};
869
870static struct qcom_icc_node slv_pmic_arb = {
871 .name = "slv_pmic_arb",
872 .id = QCM2290_SLAVE_PMIC_ARB,
873 .buswidth = 4,
874 .qos.ap_owned = true,
875 .qos.qos_mode = NOC_QOS_MODE_INVALID,
876 .mas_rpm_id = -1,
877 .slv_rpm_id = 59,
878};
879
880static struct qcom_icc_node slv_prng = {
881 .name = "slv_prng",
882 .id = QCM2290_SLAVE_PRNG,
883 .buswidth = 4,
884 .qos.ap_owned = true,
885 .qos.qos_mode = NOC_QOS_MODE_INVALID,
886 .mas_rpm_id = -1,
887 .slv_rpm_id = 44,
888};
889
890static struct qcom_icc_node slv_qdss_cfg = {
891 .name = "slv_qdss_cfg",
892 .id = QCM2290_SLAVE_QDSS_CFG,
893 .buswidth = 4,
894 .qos.ap_owned = true,
895 .qos.qos_mode = NOC_QOS_MODE_INVALID,
896 .mas_rpm_id = -1,
897 .slv_rpm_id = 63,
898};
899
900static struct qcom_icc_node slv_qm_cfg = {
901 .name = "slv_qm_cfg",
902 .id = QCM2290_SLAVE_QM_CFG,
903 .buswidth = 4,
904 .qos.ap_owned = true,
905 .qos.qos_mode = NOC_QOS_MODE_INVALID,
906 .mas_rpm_id = -1,
907 .slv_rpm_id = 212,
908};
909
910static struct qcom_icc_node slv_qm_mpu_cfg = {
911 .name = "slv_qm_mpu_cfg",
912 .id = QCM2290_SLAVE_QM_MPU_CFG,
913 .buswidth = 4,
914 .qos.ap_owned = true,
915 .qos.qos_mode = NOC_QOS_MODE_INVALID,
916 .mas_rpm_id = -1,
917 .slv_rpm_id = 231,
918};
919
920static struct qcom_icc_node slv_qpic = {
921 .name = "slv_qpic",
922 .id = QCM2290_SLAVE_QPIC,
923 .buswidth = 4,
924 .qos.ap_owned = true,
925 .qos.qos_mode = NOC_QOS_MODE_INVALID,
926 .mas_rpm_id = -1,
927 .slv_rpm_id = 80,
928};
929
930static struct qcom_icc_node slv_qup_0 = {
931 .name = "slv_qup_0",
932 .id = QCM2290_SLAVE_QUP_0,
933 .buswidth = 4,
934 .qos.ap_owned = true,
935 .qos.qos_mode = NOC_QOS_MODE_INVALID,
936 .mas_rpm_id = -1,
937 .slv_rpm_id = 261,
938};
939
940static struct qcom_icc_node slv_sdcc_1 = {
941 .name = "slv_sdcc_1",
942 .id = QCM2290_SLAVE_SDCC_1,
943 .buswidth = 4,
944 .qos.ap_owned = true,
945 .qos.qos_mode = NOC_QOS_MODE_INVALID,
946 .mas_rpm_id = -1,
947 .slv_rpm_id = 31,
948};
949
950static struct qcom_icc_node slv_sdcc_2 = {
951 .name = "slv_sdcc_2",
952 .id = QCM2290_SLAVE_SDCC_2,
953 .buswidth = 4,
954 .qos.ap_owned = true,
955 .qos.qos_mode = NOC_QOS_MODE_INVALID,
956 .mas_rpm_id = -1,
957 .slv_rpm_id = 33,
958};
959
960static const u16 slv_snoc_cfg_links[] = {
961 QCM2290_MASTER_SNOC_CFG,
962};
963
964static struct qcom_icc_node slv_snoc_cfg = {
965 .name = "slv_snoc_cfg",
966 .id = QCM2290_SLAVE_SNOC_CFG,
967 .buswidth = 4,
968 .qos.ap_owned = true,
969 .qos.qos_mode = NOC_QOS_MODE_INVALID,
970 .mas_rpm_id = -1,
971 .slv_rpm_id = 70,
972 .num_links = ARRAY_SIZE(slv_snoc_cfg_links),
973 .links = slv_snoc_cfg_links,
974};
975
976static struct qcom_icc_node slv_tcsr = {
977 .name = "slv_tcsr",
978 .id = QCM2290_SLAVE_TCSR,
979 .buswidth = 4,
980 .qos.ap_owned = true,
981 .qos.qos_mode = NOC_QOS_MODE_INVALID,
982 .mas_rpm_id = -1,
983 .slv_rpm_id = 50,
984};
985
986static struct qcom_icc_node slv_usb3 = {
987 .name = "slv_usb3",
988 .id = QCM2290_SLAVE_USB3,
989 .buswidth = 4,
990 .qos.ap_owned = true,
991 .qos.qos_mode = NOC_QOS_MODE_INVALID,
992 .mas_rpm_id = -1,
993 .slv_rpm_id = 22,
994};
995
996static struct qcom_icc_node slv_venus_cfg = {
997 .name = "slv_venus_cfg",
998 .id = QCM2290_SLAVE_VENUS_CFG,
999 .buswidth = 4,
1000 .qos.ap_owned = true,
1001 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1002 .mas_rpm_id = -1,
1003 .slv_rpm_id = 10,
1004};
1005
1006static struct qcom_icc_node slv_venus_throttle_cfg = {
1007 .name = "slv_venus_throttle_cfg",
1008 .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG,
1009 .buswidth = 4,
1010 .qos.ap_owned = true,
1011 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1012 .mas_rpm_id = -1,
1013 .slv_rpm_id = 178,
1014};
1015
1016static struct qcom_icc_node slv_vsense_ctrl_cfg = {
1017 .name = "slv_vsense_ctrl_cfg",
1018 .id = QCM2290_SLAVE_VSENSE_CTRL_CFG,
1019 .buswidth = 4,
1020 .qos.ap_owned = true,
1021 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1022 .mas_rpm_id = -1,
1023 .slv_rpm_id = 263,
1024};
1025
1026static struct qcom_icc_node slv_service_cnoc = {
1027 .name = "slv_service_cnoc",
1028 .id = QCM2290_SLAVE_SERVICE_CNOC,
1029 .buswidth = 4,
1030 .qos.ap_owned = true,
1031 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1032 .mas_rpm_id = -1,
1033 .slv_rpm_id = 76,
1034};
1035
1036static struct qcom_icc_node slv_qup_core_0 = {
1037 .name = "slv_qup_core_0",
1038 .id = QCM2290_SLAVE_QUP_CORE_0,
1039 .buswidth = 4,
1040 .qos.ap_owned = true,
1041 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1042 .mas_rpm_id = -1,
1043 .slv_rpm_id = 264,
1044};
1045
1046static const u16 slv_snoc_bimc_nrt_links[] = {
1047 QCM2290_MASTER_SNOC_BIMC_NRT,
1048};
1049
1050static struct qcom_icc_node slv_snoc_bimc_nrt = {
1051 .name = "slv_snoc_bimc_nrt",
1052 .id = QCM2290_SLAVE_SNOC_BIMC_NRT,
1053 .buswidth = 16,
1054 .qos.ap_owned = true,
1055 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1056 .mas_rpm_id = -1,
1057 .slv_rpm_id = 259,
1058 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links),
1059 .links = slv_snoc_bimc_nrt_links,
1060};
1061
1062static const u16 slv_snoc_bimc_rt_links[] = {
1063 QCM2290_MASTER_SNOC_BIMC_RT,
1064};
1065
1066static struct qcom_icc_node slv_snoc_bimc_rt = {
1067 .name = "slv_snoc_bimc_rt",
1068 .id = QCM2290_SLAVE_SNOC_BIMC_RT,
1069 .buswidth = 16,
1070 .qos.ap_owned = true,
1071 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1072 .mas_rpm_id = -1,
1073 .slv_rpm_id = 260,
1074 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links),
1075 .links = slv_snoc_bimc_rt_links,
1076};
1077
1078static struct qcom_icc_node slv_appss = {
1079 .name = "slv_appss",
1080 .id = QCM2290_SLAVE_APPSS,
1081 .buswidth = 8,
1082 .qos.ap_owned = true,
1083 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1084 .mas_rpm_id = -1,
1085 .slv_rpm_id = 20,
1086};
1087
1088static const u16 slv_snoc_cnoc_links[] = {
1089 QCM2290_MASTER_SNOC_CNOC,
1090};
1091
1092static struct qcom_icc_node slv_snoc_cnoc = {
1093 .name = "slv_snoc_cnoc",
1094 .id = QCM2290_SLAVE_SNOC_CNOC,
1095 .buswidth = 8,
1096 .mas_rpm_id = -1,
1097 .slv_rpm_id = 25,
1098 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links),
1099 .links = slv_snoc_cnoc_links,
1100};
1101
1102static struct qcom_icc_node slv_imem = {
1103 .name = "slv_imem",
1104 .id = QCM2290_SLAVE_IMEM,
1105 .buswidth = 8,
1106 .mas_rpm_id = -1,
1107 .slv_rpm_id = 26,
1108};
1109
1110static struct qcom_icc_node slv_pimem = {
1111 .name = "slv_pimem",
1112 .id = QCM2290_SLAVE_PIMEM,
1113 .buswidth = 8,
1114 .qos.ap_owned = true,
1115 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1116 .mas_rpm_id = -1,
1117 .slv_rpm_id = 166,
1118};
1119
1120static const u16 slv_snoc_bimc_links[] = {
1121 QCM2290_MASTER_SNOC_BIMC,
1122};
1123
1124static struct qcom_icc_node slv_snoc_bimc = {
1125 .name = "slv_snoc_bimc",
1126 .id = QCM2290_SLAVE_SNOC_BIMC,
1127 .buswidth = 16,
1128 .mas_rpm_id = -1,
1129 .slv_rpm_id = 24,
1130 .num_links = ARRAY_SIZE(slv_snoc_bimc_links),
1131 .links = slv_snoc_bimc_links,
1132};
1133
1134static struct qcom_icc_node slv_service_snoc = {
1135 .name = "slv_service_snoc",
1136 .id = QCM2290_SLAVE_SERVICE_SNOC,
1137 .buswidth = 4,
1138 .qos.ap_owned = true,
1139 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1140 .mas_rpm_id = -1,
1141 .slv_rpm_id = 29,
1142};
1143
1144static struct qcom_icc_node slv_qdss_stm = {
1145 .name = "slv_qdss_stm",
1146 .id = QCM2290_SLAVE_QDSS_STM,
1147 .buswidth = 4,
1148 .mas_rpm_id = -1,
1149 .slv_rpm_id = 30,
1150};
1151
1152static struct qcom_icc_node slv_tcu = {
1153 .name = "slv_tcu",
1154 .id = QCM2290_SLAVE_TCU,
1155 .buswidth = 8,
1156 .qos.ap_owned = true,
1157 .qos.qos_mode = NOC_QOS_MODE_INVALID,
1158 .mas_rpm_id = -1,
1159 .slv_rpm_id = 133,
1160};
1161
1162static const u16 slv_anoc_snoc_links[] = {
1163 QCM2290_MASTER_ANOC_SNOC,
1164};
1165
1166static struct qcom_icc_node slv_anoc_snoc = {
1167 .name = "slv_anoc_snoc",
1168 .id = QCM2290_SLAVE_ANOC_SNOC,
1169 .buswidth = 16,
1170 .mas_rpm_id = -1,
1171 .slv_rpm_id = 141,
1172 .num_links = ARRAY_SIZE(slv_anoc_snoc_links),
1173 .links = slv_anoc_snoc_links,
1174};
1175
1176/* NoC descriptors */
1177static struct qcom_icc_node * const qcm2290_bimc_nodes[] = {
1178 [MASTER_APPSS_PROC] = &mas_appss_proc,
1179 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt,
1180 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt,
1181 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
1182 [MASTER_TCU_0] = &mas_tcu_0,
1183 [MASTER_GFX3D] = &mas_gfx3d,
1184 [SLAVE_EBI1] = &slv_ebi1,
1185 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
1186};
1187
1188static const struct regmap_config qcm2290_bimc_regmap_config = {
1189 .reg_bits = 32,
1190 .reg_stride = 4,
1191 .val_bits = 32,
1192 .max_register = 0x80000,
1193 .fast_io = true,
1194};
1195
1196static const struct qcom_icc_desc qcm2290_bimc = {
1197 .type = QCOM_ICC_BIMC,
1198 .nodes = qcm2290_bimc_nodes,
1199 .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes),
1200 .regmap_cfg = &qcm2290_bimc_regmap_config,
1201 /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */
1202 .qos_offset = 0x8000,
1203};
1204
1205static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = {
1206 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
1207 [MASTER_QDSS_DAP] = &mas_qdss_dap,
1208 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
1209 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg,
1210 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg,
1211 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
1212 [SLAVE_CLK_CTL] = &slv_clk_ctl,
1213 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
1214 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
1215 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
1216 [SLAVE_GPU_CFG] = &slv_gpu_cfg,
1217 [SLAVE_HWKM] = &slv_hwkm,
1218 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
1219 [SLAVE_IPA_CFG] = &slv_ipa_cfg,
1220 [SLAVE_LPASS] = &slv_lpass,
1221 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
1222 [SLAVE_PDM] = &slv_pdm,
1223 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
1224 [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper,
1225 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
1226 [SLAVE_PRNG] = &slv_prng,
1227 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
1228 [SLAVE_QM_CFG] = &slv_qm_cfg,
1229 [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg,
1230 [SLAVE_QPIC] = &slv_qpic,
1231 [SLAVE_QUP_0] = &slv_qup_0,
1232 [SLAVE_SDCC_1] = &slv_sdcc_1,
1233 [SLAVE_SDCC_2] = &slv_sdcc_2,
1234 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
1235 [SLAVE_TCSR] = &slv_tcsr,
1236 [SLAVE_USB3] = &slv_usb3,
1237 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
1238 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
1239 [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg,
1240 [SLAVE_SERVICE_CNOC] = &slv_service_cnoc,
1241};
1242
1243static const struct regmap_config qcm2290_cnoc_regmap_config = {
1244 .reg_bits = 32,
1245 .reg_stride = 4,
1246 .val_bits = 32,
1247 .max_register = 0x8200,
1248 .fast_io = true,
1249};
1250
1251static const struct qcom_icc_desc qcm2290_cnoc = {
1252 .type = QCOM_ICC_NOC,
1253 .nodes = qcm2290_cnoc_nodes,
1254 .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes),
1255 .regmap_cfg = &qcm2290_cnoc_regmap_config,
1256};
1257
1258static struct qcom_icc_node * const qcm2290_snoc_nodes[] = {
1259 [MASTER_CRYPTO_CORE0] = &mas_crypto_core0,
1260 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
1261 [MASTER_TIC] = &mas_tic,
1262 [MASTER_ANOC_SNOC] = &mas_anoc_snoc,
1263 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
1264 [MASTER_PIMEM] = &mas_pimem,
1265 [MASTER_QDSS_BAM] = &mas_qdss_bam,
1266 [MASTER_QUP_0] = &mas_qup_0,
1267 [MASTER_IPA] = &mas_ipa,
1268 [MASTER_QDSS_ETR] = &mas_qdss_etr,
1269 [MASTER_SDCC_1] = &mas_sdcc_1,
1270 [MASTER_SDCC_2] = &mas_sdcc_2,
1271 [MASTER_QPIC] = &mas_qpic,
1272 [MASTER_USB3_0] = &mas_usb3_0,
1273 [SLAVE_APPSS] = &slv_appss,
1274 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
1275 [SLAVE_IMEM] = &slv_imem,
1276 [SLAVE_PIMEM] = &slv_pimem,
1277 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
1278 [SLAVE_SERVICE_SNOC] = &slv_service_snoc,
1279 [SLAVE_QDSS_STM] = &slv_qdss_stm,
1280 [SLAVE_TCU] = &slv_tcu,
1281 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc,
1282};
1283
1284static const struct regmap_config qcm2290_snoc_regmap_config = {
1285 .reg_bits = 32,
1286 .reg_stride = 4,
1287 .val_bits = 32,
1288 .max_register = 0x60200,
1289 .fast_io = true,
1290};
1291
1292static const struct qcom_icc_desc qcm2290_snoc = {
1293 .type = QCOM_ICC_QNOC,
1294 .nodes = qcm2290_snoc_nodes,
1295 .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes),
1296 .regmap_cfg = &qcm2290_snoc_regmap_config,
1297 /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */
1298 .qos_offset = 0x15000,
1299};
1300
1301static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = {
1302 [MASTER_QUP_CORE_0] = &mas_qup_core_0,
1303 [SLAVE_QUP_CORE_0] = &slv_qup_core_0
1304};
1305
1306static const struct qcom_icc_desc qcm2290_qup_virt = {
1307 .type = QCOM_ICC_QNOC,
1308 .nodes = qcm2290_qup_virt_nodes,
1309 .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes),
1310};
1311
1312static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = {
1313 [MASTER_CAMNOC_SF] = &mas_camnoc_sf,
1314 [MASTER_VIDEO_P0] = &mas_video_p0,
1315 [MASTER_VIDEO_PROC] = &mas_video_proc,
1316 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt,
1317};
1318
1319static const struct qcom_icc_desc qcm2290_mmnrt_virt = {
1320 .type = QCOM_ICC_QNOC,
1321 .nodes = qcm2290_mmnrt_virt_nodes,
1322 .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes),
1323 .regmap_cfg = &qcm2290_snoc_regmap_config,
1324 .qos_offset = 0x15000,
1325};
1326
1327static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = {
1328 [MASTER_CAMNOC_HF] = &mas_camnoc_hf,
1329 [MASTER_MDP0] = &mas_mdp0,
1330 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt,
1331};
1332
1333static const struct qcom_icc_desc qcm2290_mmrt_virt = {
1334 .type = QCOM_ICC_QNOC,
1335 .nodes = qcm2290_mmrt_virt_nodes,
1336 .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes),
1337 .regmap_cfg = &qcm2290_snoc_regmap_config,
1338 .qos_offset = 0x15000,
1339};
1340
1341static const struct of_device_id qcm2290_noc_of_match[] = {
1342 { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc },
1343 { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc },
1344 { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc },
1345 { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt },
1346 { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt },
1347 { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt },
1348 { },
1349};
1350MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match);
1351
1352static struct platform_driver qcm2290_noc_driver = {
1353 .probe = qnoc_probe,
1354 .remove = qnoc_remove,
1355 .driver = {
1356 .name = "qnoc-qcm2290",
1357 .of_match_table = qcm2290_noc_of_match,
1358 },
1359};
1360module_platform_driver(qcm2290_noc_driver);
1361
1362MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver");
1363MODULE_LICENSE("GPL v2");