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1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef _ASM_X86_APIC_H
3#define _ASM_X86_APIC_H
4
5#include <linux/cpumask.h>
6
7#include <asm/alternative.h>
8#include <asm/cpufeature.h>
9#include <asm/apicdef.h>
10#include <linux/atomic.h>
11#include <asm/fixmap.h>
12#include <asm/mpspec.h>
13#include <asm/msr.h>
14#include <asm/hardirq.h>
15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
18/*
19 * Debugging macros
20 */
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25/* Macros for apic_extnmi which controls external NMI masking */
26#define APIC_EXTNMI_BSP 0 /* Default */
27#define APIC_EXTNMI_ALL 1
28#define APIC_EXTNMI_NONE 2
29
30/*
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
35 */
36#define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43extern void generic_apic_probe(void);
44#else
45static inline void generic_apic_probe(void)
46{
47}
48#endif
49
50#ifdef CONFIG_X86_LOCAL_APIC
51
52extern int apic_verbosity;
53extern int local_apic_timer_c2_ok;
54
55extern int disable_apic;
56extern unsigned int lapic_timer_period;
57
58extern enum apic_intr_mode_id apic_intr_mode;
59enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65};
66
67#ifdef CONFIG_SMP
68extern void __inquire_remote_apic(int apicid);
69#else /* CONFIG_SMP */
70static inline void __inquire_remote_apic(int apicid)
71{
72}
73#endif /* CONFIG_SMP */
74
75static inline void default_inquire_remote_apic(int apicid)
76{
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79}
80
81/*
82 * With 82489DX we can't rely on apic feature bit
83 * retrieved via cpuid but still have to deal with
84 * such an apic chip so we assume that SMP configuration
85 * is found from MP table (64bit case uses ACPI mostly
86 * which set smp presence flag as well so we are safe
87 * to use this helper too).
88 */
89static inline bool apic_from_smp_config(void)
90{
91 return smp_found_config && !disable_apic;
92}
93
94/*
95 * Basic functions accessing APICs.
96 */
97#ifdef CONFIG_PARAVIRT
98#include <asm/paravirt.h>
99#endif
100
101static inline void native_apic_mem_write(u32 reg, u32 v)
102{
103 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
104
105 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
106 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
107 ASM_OUTPUT2("0" (v), "m" (*addr)));
108}
109
110static inline u32 native_apic_mem_read(u32 reg)
111{
112 return *((volatile u32 *)(APIC_BASE + reg));
113}
114
115extern void native_apic_wait_icr_idle(void);
116extern u32 native_safe_apic_wait_icr_idle(void);
117extern void native_apic_icr_write(u32 low, u32 id);
118extern u64 native_apic_icr_read(void);
119
120static inline bool apic_is_x2apic_enabled(void)
121{
122 u64 msr;
123
124 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
125 return false;
126 return msr & X2APIC_ENABLE;
127}
128
129extern void enable_IR_x2apic(void);
130
131extern int get_physical_broadcast(void);
132
133extern int lapic_get_maxlvt(void);
134extern void clear_local_APIC(void);
135extern void disconnect_bsp_APIC(int virt_wire_setup);
136extern void disable_local_APIC(void);
137extern void apic_soft_disable(void);
138extern void lapic_shutdown(void);
139extern void sync_Arb_IDs(void);
140extern void init_bsp_APIC(void);
141extern void apic_intr_mode_select(void);
142extern void apic_intr_mode_init(void);
143extern void init_apic_mappings(void);
144void register_lapic_address(unsigned long address);
145extern void setup_boot_APIC_clock(void);
146extern void setup_secondary_APIC_clock(void);
147extern void lapic_update_tsc_freq(void);
148
149#ifdef CONFIG_X86_64
150static inline int apic_force_enable(unsigned long addr)
151{
152 return -1;
153}
154#else
155extern int apic_force_enable(unsigned long addr);
156#endif
157
158extern void apic_ap_setup(void);
159
160/*
161 * On 32bit this is mach-xxx local
162 */
163#ifdef CONFIG_X86_64
164extern int apic_is_clustered_box(void);
165#else
166static inline int apic_is_clustered_box(void)
167{
168 return 0;
169}
170#endif
171
172extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
173extern void lapic_assign_system_vectors(void);
174extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
175extern void lapic_update_legacy_vectors(void);
176extern void lapic_online(void);
177extern void lapic_offline(void);
178extern bool apic_needs_pit(void);
179
180extern void apic_send_IPI_allbutself(unsigned int vector);
181
182#else /* !CONFIG_X86_LOCAL_APIC */
183static inline void lapic_shutdown(void) { }
184#define local_apic_timer_c2_ok 1
185static inline void init_apic_mappings(void) { }
186static inline void disable_local_APIC(void) { }
187# define setup_boot_APIC_clock x86_init_noop
188# define setup_secondary_APIC_clock x86_init_noop
189static inline void lapic_update_tsc_freq(void) { }
190static inline void init_bsp_APIC(void) { }
191static inline void apic_intr_mode_select(void) { }
192static inline void apic_intr_mode_init(void) { }
193static inline void lapic_assign_system_vectors(void) { }
194static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
195static inline bool apic_needs_pit(void) { return true; }
196#endif /* !CONFIG_X86_LOCAL_APIC */
197
198#ifdef CONFIG_X86_X2APIC
199static inline void native_apic_msr_write(u32 reg, u32 v)
200{
201 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
202 reg == APIC_LVR)
203 return;
204
205 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
206}
207
208static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
209{
210 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
211}
212
213static inline u32 native_apic_msr_read(u32 reg)
214{
215 u64 msr;
216
217 if (reg == APIC_DFR)
218 return -1;
219
220 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
221 return (u32)msr;
222}
223
224static inline void native_x2apic_wait_icr_idle(void)
225{
226 /* no need to wait for icr idle in x2apic */
227 return;
228}
229
230static inline u32 native_safe_x2apic_wait_icr_idle(void)
231{
232 /* no need to wait for icr idle in x2apic */
233 return 0;
234}
235
236static inline void native_x2apic_icr_write(u32 low, u32 id)
237{
238 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
239}
240
241static inline u64 native_x2apic_icr_read(void)
242{
243 unsigned long val;
244
245 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
246 return val;
247}
248
249extern int x2apic_mode;
250extern int x2apic_phys;
251extern void __init x2apic_set_max_apicid(u32 apicid);
252extern void x2apic_setup(void);
253static inline int x2apic_enabled(void)
254{
255 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
256}
257
258#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
259#else /* !CONFIG_X86_X2APIC */
260static inline void x2apic_setup(void) { }
261static inline int x2apic_enabled(void) { return 0; }
262
263#define x2apic_mode (0)
264#define x2apic_supported() (0)
265#endif /* !CONFIG_X86_X2APIC */
266extern void __init check_x2apic(void);
267
268struct irq_data;
269
270/*
271 * Copyright 2004 James Cleverdon, IBM.
272 *
273 * Generic APIC sub-arch data struct.
274 *
275 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
276 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
277 * James Cleverdon.
278 */
279struct apic {
280 /* Hotpath functions first */
281 void (*eoi_write)(u32 reg, u32 v);
282 void (*native_eoi_write)(u32 reg, u32 v);
283 void (*write)(u32 reg, u32 v);
284 u32 (*read)(u32 reg);
285
286 /* IPI related functions */
287 void (*wait_icr_idle)(void);
288 u32 (*safe_wait_icr_idle)(void);
289
290 void (*send_IPI)(int cpu, int vector);
291 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
292 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
293 void (*send_IPI_allbutself)(int vector);
294 void (*send_IPI_all)(int vector);
295 void (*send_IPI_self)(int vector);
296
297 u32 disable_esr;
298
299 enum apic_delivery_modes delivery_mode;
300 bool dest_mode_logical;
301
302 u32 (*calc_dest_apicid)(unsigned int cpu);
303
304 /* ICR related functions */
305 u64 (*icr_read)(void);
306 void (*icr_write)(u32 low, u32 high);
307
308 /* Probe, setup and smpboot functions */
309 int (*probe)(void);
310 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
311 int (*apic_id_valid)(u32 apicid);
312 int (*apic_id_registered)(void);
313
314 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
315 void (*init_apic_ldr)(void);
316 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
317 void (*setup_apic_routing)(void);
318 int (*cpu_present_to_apicid)(int mps_cpu);
319 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
320 int (*check_phys_apicid_present)(int phys_apicid);
321 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
322
323 u32 (*get_apic_id)(unsigned long x);
324 u32 (*set_apic_id)(unsigned int id);
325
326 /* wakeup_secondary_cpu */
327 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
328 /* wakeup secondary CPU using 64-bit wakeup point */
329 int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
330
331 void (*inquire_remote_apic)(int apicid);
332
333#ifdef CONFIG_X86_32
334 /*
335 * Called very early during boot from get_smp_config(). It should
336 * return the logical apicid. x86_[bios]_cpu_to_apicid is
337 * initialized before this function is called.
338 *
339 * If logical apicid can't be determined that early, the function
340 * may return BAD_APICID. Logical apicid will be configured after
341 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
342 * won't be applied properly during early boot in this case.
343 */
344 int (*x86_32_early_logical_apicid)(int cpu);
345#endif
346 char *name;
347};
348
349/*
350 * Pointer to the local APIC driver in use on this system (there's
351 * always just one such driver in use - the kernel decides via an
352 * early probing process which one it picks - and then sticks to it):
353 */
354extern struct apic *apic;
355
356/*
357 * APIC drivers are probed based on how they are listed in the .apicdrivers
358 * section. So the order is important and enforced by the ordering
359 * of different apic driver files in the Makefile.
360 *
361 * For the files having two apic drivers, we use apic_drivers()
362 * to enforce the order with in them.
363 */
364#define apic_driver(sym) \
365 static const struct apic *__apicdrivers_##sym __used \
366 __aligned(sizeof(struct apic *)) \
367 __section(".apicdrivers") = { &sym }
368
369#define apic_drivers(sym1, sym2) \
370 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
371 __aligned(sizeof(struct apic *)) \
372 __section(".apicdrivers") = { &sym1, &sym2 }
373
374extern struct apic *__apicdrivers[], *__apicdrivers_end[];
375
376/*
377 * APIC functionality to boot other CPUs - only used on SMP:
378 */
379#ifdef CONFIG_SMP
380extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
381extern int lapic_can_unplug_cpu(void);
382#endif
383
384#ifdef CONFIG_X86_LOCAL_APIC
385
386static inline u32 apic_read(u32 reg)
387{
388 return apic->read(reg);
389}
390
391static inline void apic_write(u32 reg, u32 val)
392{
393 apic->write(reg, val);
394}
395
396static inline void apic_eoi(void)
397{
398 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
399}
400
401static inline u64 apic_icr_read(void)
402{
403 return apic->icr_read();
404}
405
406static inline void apic_icr_write(u32 low, u32 high)
407{
408 apic->icr_write(low, high);
409}
410
411static inline void apic_wait_icr_idle(void)
412{
413 apic->wait_icr_idle();
414}
415
416static inline u32 safe_apic_wait_icr_idle(void)
417{
418 return apic->safe_wait_icr_idle();
419}
420
421extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
422
423#else /* CONFIG_X86_LOCAL_APIC */
424
425static inline u32 apic_read(u32 reg) { return 0; }
426static inline void apic_write(u32 reg, u32 val) { }
427static inline void apic_eoi(void) { }
428static inline u64 apic_icr_read(void) { return 0; }
429static inline void apic_icr_write(u32 low, u32 high) { }
430static inline void apic_wait_icr_idle(void) { }
431static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
432static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
433
434#endif /* CONFIG_X86_LOCAL_APIC */
435
436extern void apic_ack_irq(struct irq_data *data);
437
438static inline void ack_APIC_irq(void)
439{
440 /*
441 * ack_APIC_irq() actually gets compiled as a single instruction
442 * ... yummie.
443 */
444 apic_eoi();
445}
446
447
448static inline bool lapic_vector_set_in_irr(unsigned int vector)
449{
450 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
451
452 return !!(irr & (1U << (vector % 32)));
453}
454
455static inline unsigned default_get_apic_id(unsigned long x)
456{
457 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
458
459 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
460 return (x >> 24) & 0xFF;
461 else
462 return (x >> 24) & 0x0F;
463}
464
465/*
466 * Warm reset vector position:
467 */
468#define TRAMPOLINE_PHYS_LOW 0x467
469#define TRAMPOLINE_PHYS_HIGH 0x469
470
471extern void generic_bigsmp_probe(void);
472
473#ifdef CONFIG_X86_LOCAL_APIC
474
475#include <asm/smp.h>
476
477#define APIC_DFR_VALUE (APIC_DFR_FLAT)
478
479DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
480
481extern struct apic apic_noop;
482
483static inline unsigned int read_apic_id(void)
484{
485 unsigned int reg = apic_read(APIC_ID);
486
487 return apic->get_apic_id(reg);
488}
489
490#ifdef CONFIG_X86_64
491typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
492extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler);
493#endif
494
495extern int default_apic_id_valid(u32 apicid);
496extern int default_acpi_madt_oem_check(char *, char *);
497extern void default_setup_apic_routing(void);
498
499extern u32 apic_default_calc_apicid(unsigned int cpu);
500extern u32 apic_flat_calc_apicid(unsigned int cpu);
501
502extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
503extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
504extern int default_cpu_present_to_apicid(int mps_cpu);
505extern int default_check_phys_apicid_present(int phys_apicid);
506
507#endif /* CONFIG_X86_LOCAL_APIC */
508
509#ifdef CONFIG_SMP
510bool apic_id_is_primary_thread(unsigned int id);
511void apic_smt_update(void);
512#else
513static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
514static inline void apic_smt_update(void) { }
515#endif
516
517struct msi_msg;
518struct irq_cfg;
519
520extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
521 bool dmar);
522
523extern void ioapic_zap_locks(void);
524
525#endif /* _ASM_X86_APIC_H */