tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4
5$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Adreno or Snapdragon GPUs
9
10maintainers:
11 - Rob Clark <robdclark@gmail.com>
12
13properties:
14 compatible:
15 oneOf:
16 - description: |
17 The driver is parsing the compat string for Adreno to
18 figure out the gpu-id and patch level.
19 items:
20 - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
21 - const: qcom,adreno
22 - description: |
23 The driver is parsing the compat string for Imageon to
24 figure out the gpu-id and patch level.
25 items:
26 - pattern: '^amd,imageon-200\.[0-1]$'
27 - const: amd,imageon
28
29 clocks: true
30
31 clock-names: true
32
33 reg:
34 minItems: 1
35 maxItems: 3
36
37 reg-names:
38 minItems: 1
39 items:
40 - const: kgsl_3d0_reg_memory
41 - const: cx_mem
42 - const: cx_dbgc
43
44 interrupts:
45 maxItems: 1
46
47 interrupt-names:
48 maxItems: 1
49
50 interconnects:
51 minItems: 1
52 maxItems: 2
53
54 interconnect-names:
55 minItems: 1
56 items:
57 - const: gfx-mem
58 - const: ocmem
59
60 iommus:
61 minItems: 1
62 maxItems: 64
63
64 sram:
65 $ref: /schemas/types.yaml#/definitions/phandle-array
66 minItems: 1
67 maxItems: 4
68 items:
69 maxItems: 1
70 description: |
71 phandles to one or more reserved on-chip SRAM regions.
72 phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
73 a4xx Snapdragon SoCs. See
74 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
75
76 operating-points-v2: true
77 opp-table:
78 type: object
79
80 power-domains:
81 maxItems: 1
82
83 zap-shader:
84 type: object
85 additionalProperties: false
86 description: |
87 For a5xx and a6xx devices this node contains a memory-region that
88 points to reserved memory to store the zap shader that can be used to
89 help bring the GPU out of secure mode.
90 properties:
91 memory-region:
92 $ref: /schemas/types.yaml#/definitions/phandle
93
94 firmware-name:
95 description: |
96 Default name of the firmware to load to the remote processor.
97
98 "#cooling-cells":
99 const: 2
100
101 nvmem-cell-names:
102 maxItems: 1
103
104 nvmem-cells:
105 description: efuse registers
106 maxItems: 1
107
108 qcom,gmu:
109 $ref: /schemas/types.yaml#/definitions/phandle
110 description: |
111 For GMU attached devices a phandle to the GMU device that will
112 control the power for the GPU.
113
114
115required:
116 - compatible
117 - reg
118 - interrupts
119
120additionalProperties: false
121
122allOf:
123 - if:
124 properties:
125 compatible:
126 contains:
127 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'
128
129 then:
130 properties:
131 clocks:
132 minItems: 2
133 maxItems: 7
134
135 clock-names:
136 items:
137 anyOf:
138 - const: core
139 description: GPU Core clock
140 - const: iface
141 description: GPU Interface clock
142 - const: mem
143 description: GPU Memory clock
144 - const: mem_iface
145 description: GPU Memory Interface clock
146 - const: alt_mem_iface
147 description: GPU Alternative Memory Interface clock
148 - const: gfx3d
149 description: GPU 3D engine clock
150 - const: rbbmtimer
151 description: GPU RBBM Timer for Adreno 5xx series
152 minItems: 2
153 maxItems: 7
154
155 required:
156 - clocks
157 - clock-names
158 - if:
159 properties:
160 compatible:
161 contains:
162 pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
163
164 then: # Since Adreno 6xx series clocks should be defined in GMU
165 properties:
166 clocks: false
167 clock-names: false
168
169examples:
170 - |
171
172 // Example a3xx/4xx:
173
174 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
175 #include <dt-bindings/clock/qcom,rpmcc.h>
176 #include <dt-bindings/interrupt-controller/irq.h>
177 #include <dt-bindings/interrupt-controller/arm-gic.h>
178
179 gpu: gpu@fdb00000 {
180 compatible = "qcom,adreno-330.2", "qcom,adreno";
181
182 reg = <0xfdb00000 0x10000>;
183 reg-names = "kgsl_3d0_reg_memory";
184
185 clock-names = "core", "iface", "mem_iface";
186 clocks = <&mmcc OXILI_GFX3D_CLK>,
187 <&mmcc OXILICX_AHB_CLK>,
188 <&mmcc OXILICX_AXI_CLK>;
189
190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
191 interrupt-names = "kgsl_3d0_irq";
192
193 sram = <&gpu_sram>;
194 power-domains = <&mmcc OXILICX_GDSC>;
195 operating-points-v2 = <&gpu_opp_table>;
196 iommus = <&gpu_iommu 0>;
197 #cooling-cells = <2>;
198 };
199
200 ocmem@fdd00000 {
201 compatible = "qcom,msm8974-ocmem";
202
203 reg = <0xfdd00000 0x2000>,
204 <0xfec00000 0x180000>;
205 reg-names = "ctrl", "mem";
206
207 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
208 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
209 clock-names = "core", "iface";
210
211 #address-cells = <1>;
212 #size-cells = <1>;
213 ranges = <0 0xfec00000 0x100000>;
214
215 gpu_sram: gpu-sram@0 {
216 reg = <0x0 0x100000>;
217 };
218 };
219 - |
220
221 // Example a6xx (with GMU):
222
223 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
224 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
225 #include <dt-bindings/power/qcom-rpmpd.h>
226 #include <dt-bindings/interrupt-controller/irq.h>
227 #include <dt-bindings/interrupt-controller/arm-gic.h>
228 #include <dt-bindings/interconnect/qcom,sdm845.h>
229
230 reserved-memory {
231 #address-cells = <2>;
232 #size-cells = <2>;
233
234 zap_shader_region: gpu@8f200000 {
235 compatible = "shared-dma-pool";
236 reg = <0x0 0x90b00000 0x0 0xa00000>;
237 no-map;
238 };
239 };
240
241 gpu@5000000 {
242 compatible = "qcom,adreno-630.2", "qcom,adreno";
243
244 reg = <0x5000000 0x40000>, <0x509e000 0x10>;
245 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
246
247 #cooling-cells = <2>;
248
249 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
250
251 iommus = <&adreno_smmu 0>;
252
253 operating-points-v2 = <&gpu_opp_table>;
254
255 interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
256 interconnect-names = "gfx-mem";
257
258 qcom,gmu = <&gmu>;
259
260 gpu_opp_table: opp-table {
261 compatible = "operating-points-v2";
262
263 opp-430000000 {
264 opp-hz = /bits/ 64 <430000000>;
265 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
266 opp-peak-kBps = <5412000>;
267 };
268
269 opp-355000000 {
270 opp-hz = /bits/ 64 <355000000>;
271 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
272 opp-peak-kBps = <3072000>;
273 };
274
275 opp-267000000 {
276 opp-hz = /bits/ 64 <267000000>;
277 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
278 opp-peak-kBps = <3072000>;
279 };
280
281 opp-180000000 {
282 opp-hz = /bits/ 64 <180000000>;
283 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
284 opp-peak-kBps = <1804000>;
285 };
286 };
287
288 zap-shader {
289 memory-region = <&zap_shader_region>;
290 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
291 };
292 };