tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm CoreSight Trace Memory Controller
8
9maintainers:
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15description: |
16 CoreSight components are compliant with the ARM CoreSight architecture
17 specification and can be connected in various topologies to suit a particular
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
20 through the intermediate links connecting the source to the currently selected
21 sink.
22
23 Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
26
27# Need a custom select here or 'arm,primecell' will match on lots of nodes
28select:
29 properties:
30 compatible:
31 contains:
32 const: arm,coresight-tmc
33 required:
34 - compatible
35
36allOf:
37 - $ref: /schemas/arm/primecell.yaml#
38
39properties:
40 compatible:
41 items:
42 - const: arm,coresight-tmc
43 - const: arm,primecell
44
45 reg:
46 maxItems: 1
47
48 clocks:
49 minItems: 1
50 maxItems: 2
51
52 clock-names:
53 minItems: 1
54 items:
55 - const: apb_pclk
56 - const: atclk
57
58 iommus:
59 maxItems: 1
60
61 power-domains:
62 maxItems: 1
63
64 arm,buffer-size:
65 $ref: /schemas/types.yaml#/definitions/uint32
66 deprecated: true
67 description:
68 Size of contiguous buffer space for TMC ETR (embedded trace router). The
69 buffer size can be configured dynamically via buffer_size property in
70 sysfs instead.
71
72 arm,scatter-gather:
73 type: boolean
74 description:
75 Indicates that the TMC-ETR can safely use the SG mode on this system.
76
77 arm,max-burst-size:
78 description:
79 The maximum burst size initiated by TMC on the AXI master interface. The
80 burst size can be in the range [0..15], the setting supports one data
81 transfer per burst up to a maximum of 16 data transfers per burst.
82 $ref: /schemas/types.yaml#/definitions/uint32
83 maximum: 15
84
85 in-ports:
86 $ref: /schemas/graph.yaml#/properties/ports
87 additionalProperties: false
88
89 properties:
90 port:
91 description: Input connection from the CoreSight Trace bus.
92 $ref: /schemas/graph.yaml#/properties/port
93
94 out-ports:
95 $ref: /schemas/graph.yaml#/properties/ports
96 additionalProperties: false
97
98 properties:
99 port:
100 description: AXI or ATB Master output connection. Used for ETR
101 and ETF configurations.
102 $ref: /schemas/graph.yaml#/properties/port
103
104required:
105 - compatible
106 - reg
107 - clocks
108 - clock-names
109 - in-ports
110
111unevaluatedProperties: false
112
113examples:
114 - |
115 etr@20070000 {
116 compatible = "arm,coresight-tmc", "arm,primecell";
117 reg = <0x20070000 0x1000>;
118
119 clocks = <&oscclk6a>;
120 clock-names = "apb_pclk";
121 in-ports {
122 port {
123 etr_in_port: endpoint {
124 remote-endpoint = <&replicator2_out_port0>;
125 };
126 };
127 };
128
129 out-ports {
130 port {
131 etr_out_port: endpoint {
132 remote-endpoint = <&catu_in_port>;
133 };
134 };
135 };
136 };
137...