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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - core support
8 */
9#ifndef __LINUX_SOC_SAMSUNG_S3C_CPUFREQ_CORE_H
10#define __LINUX_SOC_SAMSUNG_S3C_CPUFREQ_CORE_H
11
12#include <linux/soc/samsung/s3c-cpu-freq.h>
13
14struct seq_file;
15
16#define MAX_BANKS (8)
17#define S3C2412_MAX_IO (8)
18
19/**
20 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
21 * @bankcon: The cached version of settings in this structure.
22 * @tacp:
23 * @tacs: Time from address valid to nCS asserted.
24 * @tcos: Time from nCS asserted to nOE or nWE asserted.
25 * @tacc: Time that nOE or nWE is asserted.
26 * @tcoh: Time nCS is held after nOE or nWE are released.
27 * @tcah: Time address is held for after
28 * @nwait_en: Whether nWAIT is enabled for this bank.
29 *
30 * This structure represents the IO timings for a S3C2410 style IO bank
31 * used by the CPU frequency support if it needs to change the settings
32 * of the IO.
33 */
34struct s3c2410_iobank_timing {
35 unsigned long bankcon;
36 unsigned int tacp;
37 unsigned int tacs;
38 unsigned int tcos;
39 unsigned int tacc;
40 unsigned int tcoh; /* nCS hold after nOE/nWE */
41 unsigned int tcah; /* Address hold after nCS */
42 unsigned char nwait_en; /* nWait enabled for bank. */
43};
44
45/**
46 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
47 * @idcy: The idle cycle time between transactions.
48 * @wstrd: nCS release to end of read cycle.
49 * @wstwr: nCS release to end of write cycle.
50 * @wstoen: nCS assertion to nOE assertion time.
51 * @wstwen: nCS assertion to nWE assertion time.
52 * @wstbrd: Burst ready delay.
53 * @smbidcyr: Register cache for smbidcyr value.
54 * @smbwstrd: Register cache for smbwstrd value.
55 * @smbwstwr: Register cache for smbwstwr value.
56 * @smbwstoen: Register cache for smbwstoen value.
57 * @smbwstwen: Register cache for smbwstwen value.
58 * @smbwstbrd: Register cache for smbwstbrd value.
59 *
60 * Timing information for a IO bank on an S3C2412 or similar system which
61 * uses a PL093 block.
62 */
63struct s3c2412_iobank_timing {
64 unsigned int idcy;
65 unsigned int wstrd;
66 unsigned int wstwr;
67 unsigned int wstoen;
68 unsigned int wstwen;
69 unsigned int wstbrd;
70
71 /* register cache */
72 unsigned char smbidcyr;
73 unsigned char smbwstrd;
74 unsigned char smbwstwr;
75 unsigned char smbwstoen;
76 unsigned char smbwstwen;
77 unsigned char smbwstbrd;
78};
79
80union s3c_iobank {
81 struct s3c2410_iobank_timing *io_2410;
82 struct s3c2412_iobank_timing *io_2412;
83};
84
85/**
86 * struct s3c_iotimings - Chip IO timings holder
87 * @bank: The timings for each IO bank.
88 */
89struct s3c_iotimings {
90 union s3c_iobank bank[MAX_BANKS];
91};
92
93/**
94 * struct s3c_plltab - PLL table information.
95 * @vals: List of PLL values.
96 * @size: Size of the PLL table @vals.
97 */
98struct s3c_plltab {
99 struct s3c_pllval *vals;
100 int size;
101};
102
103/**
104 * struct s3c_cpufreq_config - current cpu frequency configuration
105 * @freq: The current settings for the core clocks.
106 * @max: Maxium settings, derived from core, board and user settings.
107 * @pll: The PLL table entry for the current PLL settings.
108 * @divs: The divisor settings for the core clocks.
109 * @info: The current core driver information.
110 * @board: The information for the board we are running on.
111 * @lock_pll: Set if the PLL settings cannot be changed.
112 *
113 * This is for the core drivers that need to know information about
114 * the current settings and values. It should not be needed by any
115 * device drivers.
116*/
117struct s3c_cpufreq_config {
118 struct s3c_freq freq;
119 struct s3c_freq max;
120 struct clk *mpll;
121 struct cpufreq_frequency_table pll;
122 struct s3c_clkdivs divs;
123 struct s3c_cpufreq_info *info; /* for core, not drivers */
124 struct s3c_cpufreq_board *board;
125
126 unsigned int lock_pll:1;
127};
128
129/**
130 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
131 * @name: The name of this implementation.
132 * @max: The maximum frequencies for the system.
133 * @latency: Transition latency to give to cpufreq.
134 * @locktime_m: The lock-time in uS for the MPLL.
135 * @locktime_u: The lock-time in uS for the UPLL.
136 * @locttime_bits: The number of bits each LOCKTIME field.
137 * @need_pll: Set if this driver needs to change the PLL values to achieve
138 * any frequency changes. This is really only need by devices like the
139 * S3C2410 where there is no or limited divider between the PLL and the
140 * ARMCLK.
141 * @get_iotiming: Get the current IO timing data, mainly for use at start.
142 * @set_iotiming: Update the IO timings from the cached copies calculated
143 * from the @calc_iotiming entry when changing the frequency.
144 * @calc_iotiming: Calculate and update the cached copies of the IO timings
145 * from the newly calculated frequencies.
146 * @calc_freqtable: Calculate (fill in) the given frequency table from the
147 * current frequency configuration. If the table passed in is NULL,
148 * then the return is the number of elements to be filled for allocation
149 * of the table.
150 * @set_refresh: Set the memory refresh configuration.
151 * @set_fvco: Set the PLL frequencies.
152 * @set_divs: Update the clock divisors.
153 * @calc_divs: Calculate the clock divisors.
154 */
155struct s3c_cpufreq_info {
156 const char *name;
157 struct s3c_freq max;
158
159 unsigned int latency;
160
161 unsigned int locktime_m;
162 unsigned int locktime_u;
163 unsigned char locktime_bits;
164
165 unsigned int need_pll:1;
166
167 /* driver routines */
168
169 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
170 struct s3c_iotimings *timings);
171
172 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
173 struct s3c_iotimings *timings);
174
175 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
176 struct s3c_iotimings *timings);
177
178 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
179 struct cpufreq_frequency_table *t,
180 size_t table_size);
181
182 void (*debug_io_show)(struct seq_file *seq,
183 struct s3c_cpufreq_config *cfg,
184 union s3c_iobank *iob);
185
186 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
187 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
188 void (*set_divs)(struct s3c_cpufreq_config *cfg);
189 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
190};
191
192extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
193
194extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
195 unsigned int plls_no);
196
197/* exports and utilities for debugfs */
198extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
199extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
200
201#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
202#define s3c_cpufreq_debugfs_call(x) x
203#else
204#define s3c_cpufreq_debugfs_call(x) NULL
205#endif
206
207/* Useful utility functions. */
208
209extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
210
211/* S3C2410 and compatible exported functions */
212
213extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
214extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
215
216#ifdef CONFIG_S3C2410_IOTIMING
217extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
218 struct s3c_cpufreq_config *cfg,
219 union s3c_iobank *iob);
220
221extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
222 struct s3c_iotimings *iot);
223
224extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
225 struct s3c_iotimings *timings);
226
227extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
228 struct s3c_iotimings *iot);
229#else
230#define s3c2410_iotiming_debugfs NULL
231#define s3c2410_iotiming_calc NULL
232#define s3c2410_iotiming_get NULL
233#define s3c2410_iotiming_set NULL
234#endif /* CONFIG_S3C2410_IOTIMING */
235
236/* S3C2412 compatible routines */
237
238#ifdef CONFIG_S3C2412_IOTIMING
239extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
240 struct s3c_cpufreq_config *cfg,
241 union s3c_iobank *iob);
242
243extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
244 struct s3c_iotimings *timings);
245
246extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
247 struct s3c_iotimings *iot);
248
249extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
250 struct s3c_iotimings *iot);
251extern void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
252#else
253#define s3c2412_iotiming_debugfs NULL
254#define s3c2412_iotiming_calc NULL
255#define s3c2412_iotiming_get NULL
256#define s3c2412_iotiming_set NULL
257#endif /* CONFIG_S3C2412_IOTIMING */
258
259#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
260#define s3c_freq_dbg(x...) printk(KERN_INFO x)
261#else
262#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
263#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
264
265#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
266#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
267#else
268#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
269#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
270
271static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
272 int index, size_t table_size,
273 unsigned int freq)
274{
275 if (index < 0)
276 return index;
277
278 if (table) {
279 if (index >= table_size)
280 return -ENOMEM;
281
282 s3c_freq_dbg("%s: { %d = %u kHz }\n",
283 __func__, index, freq);
284
285 table[index].driver_data = index;
286 table[index].frequency = freq;
287 }
288
289 return index + 1;
290}
291
292u32 s3c2440_read_camdivn(void);
293void s3c2440_write_camdivn(u32 camdiv);
294u32 s3c24xx_read_clkdivn(void);
295void s3c24xx_write_clkdivn(u32 clkdiv);
296u32 s3c24xx_read_mpllcon(void);
297void s3c24xx_write_locktime(u32 locktime);
298
299#endif