tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SC7280 TLMM block
8
9maintainers:
10 - Bjorn Andersson <andersson@kernel.org>
11
12description:
13 Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC.
14
15properties:
16 compatible:
17 const: qcom,sc7280-pinctrl
18
19 reg:
20 maxItems: 1
21
22 interrupts:
23 description: Specifies the TLMM summary IRQ
24 maxItems: 1
25
26 interrupt-controller: true
27
28 '#interrupt-cells':
29 description:
30 Specifies the PIN numbers and Flags, as defined in defined in
31 include/dt-bindings/interrupt-controller/irq.h
32 const: 2
33
34 gpio-controller: true
35
36 '#gpio-cells':
37 description: Specifying the pin number and flags, as defined in
38 include/dt-bindings/gpio/gpio.h
39 const: 2
40
41 gpio-ranges:
42 maxItems: 1
43
44 gpio-line-names:
45 maxItems: 175
46
47 wakeup-parent: true
48
49patternProperties:
50 "-state$":
51 oneOf:
52 - $ref: "#/$defs/qcom-sc7280-tlmm-state"
53 - patternProperties:
54 "-pins$":
55 $ref: "#/$defs/qcom-sc7280-tlmm-state"
56 additionalProperties: false
57
58$defs:
59 qcom-sc7280-tlmm-state:
60 type: object
61 description:
62 Pinctrl node's client devices use subnodes for desired pin configuration.
63 Client device subnodes use below standard properties.
64 $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
65
66 properties:
67 pins:
68 description:
69 List of gpio pins affected by the properties specified in this
70 subnode.
71 items:
72 oneOf:
73 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$"
74 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
75 sdc2_cmd, sdc2_data, ufs_reset ]
76 minItems: 1
77 maxItems: 16
78
79 function:
80 description:
81 Specify the alternative function to be configured for the specified
82 pins.
83
84 enum: [ atest_char, atest_char0, atest_char1, atest_char2,
85 atest_char3, atest_usb0, atest_usb00, atest_usb01,
86 atest_usb02, atest_usb03, atest_usb1, atest_usb10,
87 atest_usb11, atest_usb12, atest_usb13, audio_ref,
88 cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
89 cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1,
90 cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0,
91 cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot,
92 dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
93 gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus,
94 mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3,
95 mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck,
96 mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
97 mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0,
98 mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2,
99 mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7,
100 mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2,
101 pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag,
102 pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc,
103 qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss,
104 qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs,
105 qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07,
106 qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17,
107 sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write,
108 sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1,
109 tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset,
110 uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac,
111 usb_phy, vfr_0, vfr_1, vsense_trigger ]
112
113 bias-pull-down: true
114 bias-pull-up: true
115 bias-bus-hold: true
116 bias-disable: true
117 drive-strength: true
118 input-enable: true
119 output-high: true
120 output-low: true
121
122 required:
123 - pins
124
125 additionalProperties: false
126
127allOf:
128 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
129
130required:
131 - compatible
132 - reg
133 - interrupts
134 - interrupt-controller
135 - '#interrupt-cells'
136 - gpio-controller
137 - '#gpio-cells'
138 - gpio-ranges
139
140additionalProperties: false
141
142examples:
143 - |
144 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 tlmm: pinctrl@f000000 {
146 compatible = "qcom,sc7280-pinctrl";
147 reg = <0xf000000 0x1000000>;
148 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
149 gpio-controller;
150 #gpio-cells = <2>;
151 interrupt-controller;
152 #interrupt-cells = <2>;
153 gpio-ranges = <&tlmm 0 0 175>;
154 wakeup-parent = <&pdc>;
155
156 qup_uart5_default: qup-uart5-state {
157 pins = "gpio46", "gpio47";
158 function = "qup13";
159 drive-strength = <2>;
160 bias-disable;
161 };
162 };