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1# SPDX-License-Identifier: GPL-2.0-only
2# Copyright 2019-2020, The Linux Foundation, All Rights Reserved
3%YAML 1.2
4---
5
6$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
7$schema: "http://devicetree.org/meta-schemas/core.yaml#"
8
9title: GMU attached to certain Adreno GPUs
10
11maintainers:
12 - Rob Clark <robdclark@gmail.com>
13
14description: |
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
17 management and support to improve power efficiency and reduce the load on
18 the CPU.
19
20properties:
21 compatible:
22 items:
23 - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
24 - const: qcom,adreno-gmu
25
26 reg:
27 minItems: 3
28 maxItems: 4
29
30 reg-names:
31 minItems: 3
32 maxItems: 4
33
34 clocks:
35 minItems: 4
36 maxItems: 7
37
38 clock-names:
39 minItems: 4
40 maxItems: 7
41
42 interrupts:
43 items:
44 - description: GMU HFI interrupt
45 - description: GMU interrupt
46
47
48 interrupt-names:
49 items:
50 - const: hfi
51 - const: gmu
52
53 power-domains:
54 items:
55 - description: CX power domain
56 - description: GX power domain
57
58 power-domain-names:
59 items:
60 - const: cx
61 - const: gx
62
63 iommus:
64 maxItems: 1
65
66 operating-points-v2: true
67
68 opp-table:
69 type: object
70
71required:
72 - compatible
73 - reg
74 - reg-names
75 - clocks
76 - clock-names
77 - interrupts
78 - interrupt-names
79 - power-domains
80 - power-domain-names
81 - iommus
82 - operating-points-v2
83
84additionalProperties: false
85
86allOf:
87 - if:
88 properties:
89 compatible:
90 contains:
91 enum:
92 - qcom,adreno-gmu-618.0
93 - qcom,adreno-gmu-630.2
94 then:
95 properties:
96 reg:
97 items:
98 - description: Core GMU registers
99 - description: GMU PDC registers
100 - description: GMU PDC sequence registers
101 reg-names:
102 items:
103 - const: gmu
104 - const: gmu_pdc
105 - const: gmu_pdc_seq
106 clocks:
107 items:
108 - description: GMU clock
109 - description: GPU CX clock
110 - description: GPU AXI clock
111 - description: GPU MEMNOC clock
112 clock-names:
113 items:
114 - const: gmu
115 - const: cxo
116 - const: axi
117 - const: memnoc
118
119 - if:
120 properties:
121 compatible:
122 contains:
123 enum:
124 - qcom,adreno-gmu-635.0
125 then:
126 properties:
127 reg:
128 items:
129 - description: Core GMU registers
130 - description: Resource controller registers
131 - description: GMU PDC registers
132 reg-names:
133 items:
134 - const: gmu
135 - const: rscc
136 - const: gmu_pdc
137 clocks:
138 items:
139 - description: GMU clock
140 - description: GPU CX clock
141 - description: GPU AXI clock
142 - description: GPU MEMNOC clock
143 - description: GPU AHB clock
144 - description: GPU HUB CX clock
145 - description: GPU SMMU vote clock
146 clock-names:
147 items:
148 - const: gmu
149 - const: cxo
150 - const: axi
151 - const: memnoc
152 - const: ahb
153 - const: hub
154 - const: smmu_vote
155
156 - if:
157 properties:
158 compatible:
159 contains:
160 enum:
161 - qcom,adreno-gmu-640.1
162 then:
163 properties:
164 reg:
165 items:
166 - description: Core GMU registers
167 - description: GMU PDC registers
168 - description: GMU PDC sequence registers
169 reg-names:
170 items:
171 - const: gmu
172 - const: gmu_pdc
173 - const: gmu_pdc_seq
174
175 - if:
176 properties:
177 compatible:
178 contains:
179 enum:
180 - qcom,adreno-gmu-650.2
181 then:
182 properties:
183 reg:
184 items:
185 - description: Core GMU registers
186 - description: Resource controller registers
187 - description: GMU PDC registers
188 - description: GMU PDC sequence registers
189 reg-names:
190 items:
191 - const: gmu
192 - const: rscc
193 - const: gmu_pdc
194 - const: gmu_pdc_seq
195
196 - if:
197 properties:
198 compatible:
199 contains:
200 enum:
201 - qcom,adreno-gmu-640.1
202 - qcom,adreno-gmu-650.2
203 then:
204 properties:
205 clocks:
206 items:
207 - description: GPU AHB clock
208 - description: GMU clock
209 - description: GPU CX clock
210 - description: GPU AXI clock
211 - description: GPU MEMNOC clock
212 clock-names:
213 items:
214 - const: ahb
215 - const: gmu
216 - const: cxo
217 - const: axi
218 - const: memnoc
219
220examples:
221 - |
222 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
223 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
224 #include <dt-bindings/interrupt-controller/irq.h>
225 #include <dt-bindings/interrupt-controller/arm-gic.h>
226
227 gmu: gmu@506a000 {
228 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
229
230 reg = <0x506a000 0x30000>,
231 <0xb280000 0x10000>,
232 <0xb480000 0x10000>;
233 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
234
235 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
236 <&gpucc GPU_CC_CXO_CLK>,
237 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
238 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
239 clock-names = "gmu", "cxo", "axi", "memnoc";
240
241 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-names = "hfi", "gmu";
244
245 power-domains = <&gpucc GPU_CX_GDSC>,
246 <&gpucc GPU_GX_GDSC>;
247 power-domain-names = "cx", "gx";
248
249 iommus = <&adreno_smmu 5>;
250 operating-points-v2 = <&gmu_opp_table>;
251 };