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1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare PCIe interface
8
9maintainers:
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
12
13description: |
14 Synopsys DesignWare PCIe host controller
15
16# Please create a separate DT-schema for your DWC PCIe Root Port controller
17# and make sure it's assigned with the vendor-specific compatible string.
18select:
19 properties:
20 compatible:
21 const: snps,dw-pcie
22 required:
23 - compatible
24
25allOf:
26 - $ref: /schemas/pci/pci-bus.yaml#
27 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
28
29properties:
30 reg:
31 description:
32 At least DBI reg-space and peripheral devices CFG-space outbound window
33 are required for the normal controller work. iATU memory IO region is
34 also required if the space is unrolled (IP-core version >= 4.80a).
35 minItems: 2
36 maxItems: 5
37
38 reg-names:
39 minItems: 2
40 maxItems: 5
41 items:
42 oneOf:
43 - description:
44 Basic DWC PCIe controller configuration-space accessible over
45 the DBI interface. This memory space is either activated with
46 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
48 via the PL viewports on the DWC PCIe controllers older than
49 v4.80a.
50 const: dbi
51 - description:
52 Shadow DWC PCIe config-space registers. This space is selected
53 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
54 the PCI-SIG PCIe CFG-space with the shadow registers for some
55 PCI Header space, PCI Standard and Extended Structures. It's
56 mainly relevant for the end-point controller configuration,
57 but still there are some shadow registers available for the
58 Root Port mode too.
59 const: dbi2
60 - description:
61 External Local Bus registers. It's an application-dependent
62 registers normally defined by the platform engineers. The space
63 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
64 be accessed over some platform-specific means (for instance
65 as a part of a system controller).
66 enum: [ elbi, app ]
67 - description:
68 iATU/eDMA registers common for all device functions. It's an
69 unrolled memory space with the internal Address Translation
70 Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
71 and CS2 = 1. For IP-core releases prior v4.80a, these registers
72 have been programmed via an indirect addressing scheme using a
73 set of viewport CSRs mapped into the PL space. Note iATU is
74 normally mapped to the 0x0 address of this region, while eDMA
75 is available at 0x80000 base address.
76 const: atu
77 - description:
78 Platform-specific eDMA registers. Some platforms may have eDMA
79 CSRs mapped in a non-standard base address. The registers offset
80 can be changed or the MS/LS-bits of the address can be attached
81 in an additional RTL block before the MEM-IO transactions reach
82 the DW PCIe slave interface.
83 const: dma
84 - description:
85 PHY/PCS configuration registers. Some platforms can have the
86 PCS and PHY CSRs accessible over a dedicated memory mapped
87 region, but mainly these registers are indirectly accessible
88 either by means of the embedded PHY viewport schema or by some
89 platform-specific method.
90 const: phy
91 - description:
92 Outbound iATU-capable memory-region which will be used to access
93 the peripheral PCIe devices configuration space.
94 const: config
95 - description:
96 Vendor-specific CSR names. Consider using the generic names above
97 for new bindings.
98 oneOf:
99 - description: See native 'elbi/app' CSR region for details.
100 enum: [ apb, mgmt, link, ulreg, appl ]
101 - description: See native 'atu' CSR region for details.
102 enum: [ atu_dma ]
103 - description: Syscon-related CSR regions.
104 enum: [ smu, mpu ]
105 - description: Tegra234 aperture
106 enum: [ ecam ]
107 allOf:
108 - contains:
109 const: dbi
110 - contains:
111 const: config
112
113 interrupts:
114 description:
115 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
116 signal is supposed to be specified for the host controller.
117 minItems: 1
118 maxItems: 26
119
120 interrupt-names:
121 minItems: 1
122 maxItems: 26
123 items:
124 oneOf:
125 - description:
126 Controller request to read or write virtual product data
127 from/to the VPD capability registers.
128 const: vpd
129 - description:
130 Link Equalization Request flag is set in the Link Status 2
131 register (applicable if the corresponding IRQ is enabled in
132 the Link Control 3 register).
133 const: l_eq
134 - description:
135 Indicates that the eDMA Tx/Rx transfer is complete or that an
136 error has occurred on the corresponding channel. eDMA can have
137 eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
138 to 16 IRQ signals all together. Write eDMA channels shall go
139 first in the ordered row as per default edma_int[*] bus setup.
140 pattern: '^dma([0-9]|1[0-5])?$'
141 - description:
142 PCIe protocol correctable error or a Data Path protection
143 correctable error is detected by the automotive/safety
144 feature.
145 const: sft_ce
146 - description:
147 Indicates that the internal safety mechanism has detected an
148 uncorrectable error.
149 const: sft_ue
150 - description:
151 Application-specific IRQ raised depending on the vendor-specific
152 events basis.
153 const: app
154 - description:
155 DSP AXI MSI Interrupt detected. It gets de-asserted when there is
156 no more MSI interrupt pending. The interrupt is relevant to the
157 iMSI-RX - Integrated MSI Receiver (AXI bridge).
158 const: msi
159 - description:
160 Legacy A/B/C/D interrupt signal. Basically it's triggered by
161 receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message
162 from the downstream device.
163 pattern: "^int(a|b|c|d)$"
164 - description:
165 Error condition detected and a flag is set in the Root Error Status
166 register of the AER capability. It's asserted when the RC
167 internally generated an error or an error message is received by
168 the RC.
169 const: aer
170 - description:
171 PME message is received by the port. That means having the PME
172 status bit set in the Root Status register (the event is
173 supposed to be unmasked in the Root Control register).
174 const: pme
175 - description:
176 Hot-plug event is detected. That is a bit has been set in the
177 Slot Status register and the corresponding event is enabled in
178 the Slot Control register.
179 const: hp
180 - description:
181 Link Autonomous Bandwidth Status flag has been set in the Link
182 Status register (the event is supposed to be unmasked in the
183 Link Control register).
184 const: bw_au
185 - description:
186 Bandwidth Management Status flag has been set in the Link
187 Status register (the event is supposed to be unmasked in the
188 Link Control register).
189 const: bw_mg
190 - description:
191 Vendor-specific IRQ names. Consider using the generic names above
192 for new bindings.
193 oneOf:
194 - description: See native "app" IRQ for details
195 enum: [ intr ]
196 allOf:
197 - contains:
198 const: msi
199
200additionalProperties: true
201
202required:
203 - compatible
204 - reg
205 - reg-names
206
207examples:
208 - |
209 pcie@dfc00000 {
210 compatible = "snps,dw-pcie";
211 device_type = "pci";
212 reg = <0xdfc00000 0x0001000>, /* IP registers */
213 <0xd0000000 0x0002000>; /* Configuration space */
214 reg-names = "dbi", "config";
215 #address-cells = <3>;
216 #size-cells = <2>;
217 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
218 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
219 bus-range = <0x0 0xff>;
220
221 interrupts = <25>, <24>;
222 interrupt-names = "msi", "hp";
223 #interrupt-cells = <1>;
224
225 reset-gpios = <&port0 0 1>;
226
227 phys = <&pcie_phy>;
228 phy-names = "pcie";
229
230 num-lanes = <1>;
231 max-link-speed = <3>;
232 };