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1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MTK_MMSYS_H
4#define __SOC_MEDIATEK_MTK_MMSYS_H
5
6#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
7#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
8#define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
9#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
10#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
11#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
12#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
13#define DISP_REG_CONFIG_DSIE_SEL_IN 0x0a4
14#define DISP_REG_CONFIG_DSIO_SEL_IN 0x0a8
15#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
16#define DISP_REG_CONFIG_DISP_RDMA2_SOUT 0x0b8
17#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
18#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
19#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
20
21#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030
22#define DISP_REG_CONFIG_OUT_SEL 0x04c
23#define DISP_REG_CONFIG_DSI_SEL 0x050
24#define DISP_REG_CONFIG_DPI_SEL 0x064
25
26#define OVL0_MOUT_EN_COLOR0 0x1
27#define OD_MOUT_EN_RDMA0 0x1
28#define OD1_MOUT_EN_RDMA1 BIT(16)
29#define UFOE_MOUT_EN_DSI0 0x1
30#define COLOR0_SEL_IN_OVL0 0x1
31#define OVL1_MOUT_EN_COLOR1 0x1
32#define GAMMA_MOUT_EN_RDMA1 0x1
33#define RDMA0_SOUT_DPI0 0x2
34#define RDMA0_SOUT_DPI1 0x3
35#define RDMA0_SOUT_DSI1 0x1
36#define RDMA0_SOUT_DSI2 0x4
37#define RDMA0_SOUT_DSI3 0x5
38#define RDMA0_SOUT_MASK 0x7
39#define RDMA1_SOUT_DPI0 0x2
40#define RDMA1_SOUT_DPI1 0x3
41#define RDMA1_SOUT_DSI1 0x1
42#define RDMA1_SOUT_DSI2 0x4
43#define RDMA1_SOUT_DSI3 0x5
44#define RDMA1_SOUT_MASK 0x7
45#define RDMA2_SOUT_DPI0 0x2
46#define RDMA2_SOUT_DPI1 0x3
47#define RDMA2_SOUT_DSI1 0x1
48#define RDMA2_SOUT_DSI2 0x4
49#define RDMA2_SOUT_DSI3 0x5
50#define RDMA2_SOUT_MASK 0x7
51#define DPI0_SEL_IN_RDMA1 0x1
52#define DPI0_SEL_IN_RDMA2 0x3
53#define DPI0_SEL_IN_MASK 0x3
54#define DPI1_SEL_IN_RDMA1 (0x1 << 8)
55#define DPI1_SEL_IN_RDMA2 (0x3 << 8)
56#define DPI1_SEL_IN_MASK (0x3 << 8)
57#define DSI0_SEL_IN_RDMA1 0x1
58#define DSI0_SEL_IN_RDMA2 0x4
59#define DSI0_SEL_IN_MASK 0x7
60#define DSI1_SEL_IN_RDMA1 0x1
61#define DSI1_SEL_IN_RDMA2 0x4
62#define DSI1_SEL_IN_MASK 0x7
63#define DSI2_SEL_IN_RDMA1 (0x1 << 16)
64#define DSI2_SEL_IN_RDMA2 (0x4 << 16)
65#define DSI2_SEL_IN_MASK (0x7 << 16)
66#define DSI3_SEL_IN_RDMA1 (0x1 << 16)
67#define DSI3_SEL_IN_RDMA2 (0x4 << 16)
68#define DSI3_SEL_IN_MASK (0x7 << 16)
69#define COLOR1_SEL_IN_OVL1 0x1
70
71#define OVL_MOUT_EN_RDMA 0x1
72#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8
73#define BLS_TO_DPI_RDMA1_TO_DSI 0x2
74#define BLS_RDMA1_DSI_DPI_MASK 0xf
75#define DSI_SEL_IN_BLS 0x0
76#define DPI_SEL_IN_BLS 0x0
77#define DPI_SEL_IN_MASK 0x1
78#define DSI_SEL_IN_RDMA 0x1
79#define DSI_SEL_IN_MASK 0x1
80
81struct mtk_mmsys_routes {
82 u32 from_comp;
83 u32 to_comp;
84 u32 addr;
85 u32 mask;
86 u32 val;
87};
88
89struct mtk_mmsys_driver_data {
90 const char *clk_driver;
91 const struct mtk_mmsys_routes *routes;
92 const unsigned int num_routes;
93 const u16 sw0_rst_offset;
94};
95
96/*
97 * Routes in mt8173, mt2701, mt2712 are different. That means
98 * in the same register address, it controls different input/output
99 * selection for each SoC. But, right now, they use the same table as
100 * default routes meet their requirements. But we don't have the complete
101 * route information for these three SoC, so just keep them in the same
102 * table. After we've more information, we could separate mt2701, mt2712
103 * to an independent table.
104 */
105static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
106 {
107 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
108 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
109 BLS_TO_DSI_RDMA1_TO_DPI1
110 }, {
111 DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
112 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
113 DSI_SEL_IN_BLS
114 }, {
115 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
116 DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
117 BLS_TO_DPI_RDMA1_TO_DSI
118 }, {
119 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
120 DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
121 DSI_SEL_IN_RDMA
122 }, {
123 DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
124 DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
125 DPI_SEL_IN_BLS
126 }, {
127 DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
128 DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
129 GAMMA_MOUT_EN_RDMA1
130 }, {
131 DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
132 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
133 OD_MOUT_EN_RDMA0
134 }, {
135 DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
136 DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
137 OD1_MOUT_EN_RDMA1
138 }, {
139 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
140 DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
141 OVL0_MOUT_EN_COLOR0
142 }, {
143 DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
144 DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
145 COLOR0_SEL_IN_OVL0
146 }, {
147 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
148 DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
149 OVL_MOUT_EN_RDMA
150 }, {
151 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
152 DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
153 OVL1_MOUT_EN_COLOR1
154 }, {
155 DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
156 DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
157 COLOR1_SEL_IN_OVL1
158 }, {
159 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
160 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
161 RDMA0_SOUT_DPI0
162 }, {
163 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
164 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
165 RDMA0_SOUT_DPI1
166 }, {
167 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
168 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
169 RDMA0_SOUT_DSI1
170 }, {
171 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
172 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
173 RDMA0_SOUT_DSI2
174 }, {
175 DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
176 DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
177 RDMA0_SOUT_DSI3
178 }, {
179 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
180 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
181 RDMA1_SOUT_DPI0
182 }, {
183 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
184 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
185 DPI0_SEL_IN_RDMA1
186 }, {
187 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
188 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
189 RDMA1_SOUT_DPI1
190 }, {
191 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
192 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
193 DPI1_SEL_IN_RDMA1
194 }, {
195 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
196 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
197 DSI0_SEL_IN_RDMA1
198 }, {
199 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
200 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
201 RDMA1_SOUT_DSI1
202 }, {
203 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
204 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
205 DSI1_SEL_IN_RDMA1
206 }, {
207 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
208 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
209 RDMA1_SOUT_DSI2
210 }, {
211 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
212 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
213 DSI2_SEL_IN_RDMA1
214 }, {
215 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
216 DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
217 RDMA1_SOUT_DSI3
218 }, {
219 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
220 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
221 DSI3_SEL_IN_RDMA1
222 }, {
223 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
224 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
225 RDMA2_SOUT_DPI0
226 }, {
227 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
228 DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
229 DPI0_SEL_IN_RDMA2
230 }, {
231 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
232 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
233 RDMA2_SOUT_DPI1
234 }, {
235 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
236 DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
237 DPI1_SEL_IN_RDMA2
238 }, {
239 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
240 DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
241 DSI0_SEL_IN_RDMA2
242 }, {
243 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
244 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
245 RDMA2_SOUT_DSI1
246 }, {
247 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
248 DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
249 DSI1_SEL_IN_RDMA2
250 }, {
251 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
252 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
253 RDMA2_SOUT_DSI2
254 }, {
255 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
256 DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
257 DSI2_SEL_IN_RDMA2
258 }, {
259 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
260 DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
261 RDMA2_SOUT_DSI3
262 }, {
263 DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
264 DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
265 DSI3_SEL_IN_RDMA2
266 }, {
267 DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
268 DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
269 UFOE_MOUT_EN_DSI0
270 }
271};
272
273#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */