tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2020 Intel Corporation.
3
4#include <asm/unaligned.h>
5#include <linux/acpi.h>
6#include <linux/delay.h>
7#include <linux/i2c.h>
8#include <linux/module.h>
9#include <linux/pm_runtime.h>
10#include <linux/nvmem-provider.h>
11#include <linux/regmap.h>
12#include <media/v4l2-ctrls.h>
13#include <media/v4l2-device.h>
14#include <media/v4l2-fwnode.h>
15
16#define OV2740_LINK_FREQ_360MHZ 360000000ULL
17#define OV2740_SCLK 72000000LL
18#define OV2740_MCLK 19200000
19#define OV2740_DATA_LANES 2
20#define OV2740_RGB_DEPTH 10
21
22#define OV2740_REG_CHIP_ID 0x300a
23#define OV2740_CHIP_ID 0x2740
24
25#define OV2740_REG_MODE_SELECT 0x0100
26#define OV2740_MODE_STANDBY 0x00
27#define OV2740_MODE_STREAMING 0x01
28
29/* vertical-timings from sensor */
30#define OV2740_REG_VTS 0x380e
31#define OV2740_VTS_DEF 0x088a
32#define OV2740_VTS_MIN 0x0460
33#define OV2740_VTS_MAX 0x7fff
34
35/* horizontal-timings from sensor */
36#define OV2740_REG_HTS 0x380c
37
38/* Exposure controls from sensor */
39#define OV2740_REG_EXPOSURE 0x3500
40#define OV2740_EXPOSURE_MIN 4
41#define OV2740_EXPOSURE_MAX_MARGIN 8
42#define OV2740_EXPOSURE_STEP 1
43
44/* Analog gain controls from sensor */
45#define OV2740_REG_ANALOG_GAIN 0x3508
46#define OV2740_ANAL_GAIN_MIN 128
47#define OV2740_ANAL_GAIN_MAX 1983
48#define OV2740_ANAL_GAIN_STEP 1
49
50/* Digital gain controls from sensor */
51#define OV2740_REG_MWB_R_GAIN 0x500a
52#define OV2740_REG_MWB_G_GAIN 0x500c
53#define OV2740_REG_MWB_B_GAIN 0x500e
54#define OV2740_DGTL_GAIN_MIN 1024
55#define OV2740_DGTL_GAIN_MAX 4095
56#define OV2740_DGTL_GAIN_STEP 1
57#define OV2740_DGTL_GAIN_DEFAULT 1024
58
59/* Test Pattern Control */
60#define OV2740_REG_TEST_PATTERN 0x5040
61#define OV2740_TEST_PATTERN_ENABLE BIT(7)
62#define OV2740_TEST_PATTERN_BAR_SHIFT 2
63
64/* Group Access */
65#define OV2740_REG_GROUP_ACCESS 0x3208
66#define OV2740_GROUP_HOLD_START 0x0
67#define OV2740_GROUP_HOLD_END 0x10
68#define OV2740_GROUP_HOLD_LAUNCH 0xa0
69
70/* ISP CTRL00 */
71#define OV2740_REG_ISP_CTRL00 0x5000
72/* ISP CTRL01 */
73#define OV2740_REG_ISP_CTRL01 0x5001
74/* Customer Addresses: 0x7010 - 0x710F */
75#define CUSTOMER_USE_OTP_SIZE 0x100
76/* OTP registers from sensor */
77#define OV2740_REG_OTP_CUSTOMER 0x7010
78
79struct nvm_data {
80 struct nvmem_device *nvmem;
81 struct regmap *regmap;
82 char *nvm_buffer;
83};
84
85enum {
86 OV2740_LINK_FREQ_360MHZ_INDEX,
87};
88
89struct ov2740_reg {
90 u16 address;
91 u8 val;
92};
93
94struct ov2740_reg_list {
95 u32 num_of_regs;
96 const struct ov2740_reg *regs;
97};
98
99struct ov2740_link_freq_config {
100 const struct ov2740_reg_list reg_list;
101};
102
103struct ov2740_mode {
104 /* Frame width in pixels */
105 u32 width;
106
107 /* Frame height in pixels */
108 u32 height;
109
110 /* Horizontal timining size */
111 u32 hts;
112
113 /* Default vertical timining size */
114 u32 vts_def;
115
116 /* Min vertical timining size */
117 u32 vts_min;
118
119 /* Link frequency needed for this resolution */
120 u32 link_freq_index;
121
122 /* Sensor register settings for this resolution */
123 const struct ov2740_reg_list reg_list;
124};
125
126static const struct ov2740_reg mipi_data_rate_720mbps[] = {
127 {0x0103, 0x01},
128 {0x0302, 0x4b},
129 {0x030d, 0x4b},
130 {0x030e, 0x02},
131 {0x030a, 0x01},
132 {0x0312, 0x11},
133};
134
135static const struct ov2740_reg mode_1932x1092_regs[] = {
136 {0x3000, 0x00},
137 {0x3018, 0x32},
138 {0x3031, 0x0a},
139 {0x3080, 0x08},
140 {0x3083, 0xB4},
141 {0x3103, 0x00},
142 {0x3104, 0x01},
143 {0x3106, 0x01},
144 {0x3500, 0x00},
145 {0x3501, 0x44},
146 {0x3502, 0x40},
147 {0x3503, 0x88},
148 {0x3507, 0x00},
149 {0x3508, 0x00},
150 {0x3509, 0x80},
151 {0x350c, 0x00},
152 {0x350d, 0x80},
153 {0x3510, 0x00},
154 {0x3511, 0x00},
155 {0x3512, 0x20},
156 {0x3632, 0x00},
157 {0x3633, 0x10},
158 {0x3634, 0x10},
159 {0x3635, 0x10},
160 {0x3645, 0x13},
161 {0x3646, 0x81},
162 {0x3636, 0x10},
163 {0x3651, 0x0a},
164 {0x3656, 0x02},
165 {0x3659, 0x04},
166 {0x365a, 0xda},
167 {0x365b, 0xa2},
168 {0x365c, 0x04},
169 {0x365d, 0x1d},
170 {0x365e, 0x1a},
171 {0x3662, 0xd7},
172 {0x3667, 0x78},
173 {0x3669, 0x0a},
174 {0x366a, 0x92},
175 {0x3700, 0x54},
176 {0x3702, 0x10},
177 {0x3706, 0x42},
178 {0x3709, 0x30},
179 {0x370b, 0xc2},
180 {0x3714, 0x63},
181 {0x3715, 0x01},
182 {0x3716, 0x00},
183 {0x371a, 0x3e},
184 {0x3732, 0x0e},
185 {0x3733, 0x10},
186 {0x375f, 0x0e},
187 {0x3768, 0x30},
188 {0x3769, 0x44},
189 {0x376a, 0x22},
190 {0x377b, 0x20},
191 {0x377c, 0x00},
192 {0x377d, 0x0c},
193 {0x3798, 0x00},
194 {0x37a1, 0x55},
195 {0x37a8, 0x6d},
196 {0x37c2, 0x04},
197 {0x37c5, 0x00},
198 {0x37c8, 0x00},
199 {0x3800, 0x00},
200 {0x3801, 0x00},
201 {0x3802, 0x00},
202 {0x3803, 0x00},
203 {0x3804, 0x07},
204 {0x3805, 0x8f},
205 {0x3806, 0x04},
206 {0x3807, 0x47},
207 {0x3808, 0x07},
208 {0x3809, 0x88},
209 {0x380a, 0x04},
210 {0x380b, 0x40},
211 {0x380c, 0x04},
212 {0x380d, 0x38},
213 {0x380e, 0x04},
214 {0x380f, 0x60},
215 {0x3810, 0x00},
216 {0x3811, 0x04},
217 {0x3812, 0x00},
218 {0x3813, 0x04},
219 {0x3814, 0x01},
220 {0x3815, 0x01},
221 {0x3820, 0x80},
222 {0x3821, 0x46},
223 {0x3822, 0x84},
224 {0x3829, 0x00},
225 {0x382a, 0x01},
226 {0x382b, 0x01},
227 {0x3830, 0x04},
228 {0x3836, 0x01},
229 {0x3837, 0x08},
230 {0x3839, 0x01},
231 {0x383a, 0x00},
232 {0x383b, 0x08},
233 {0x383c, 0x00},
234 {0x3f0b, 0x00},
235 {0x4001, 0x20},
236 {0x4009, 0x07},
237 {0x4003, 0x10},
238 {0x4010, 0xe0},
239 {0x4016, 0x00},
240 {0x4017, 0x10},
241 {0x4044, 0x02},
242 {0x4304, 0x08},
243 {0x4307, 0x30},
244 {0x4320, 0x80},
245 {0x4322, 0x00},
246 {0x4323, 0x00},
247 {0x4324, 0x00},
248 {0x4325, 0x00},
249 {0x4326, 0x00},
250 {0x4327, 0x00},
251 {0x4328, 0x00},
252 {0x4329, 0x00},
253 {0x432c, 0x03},
254 {0x432d, 0x81},
255 {0x4501, 0x84},
256 {0x4502, 0x40},
257 {0x4503, 0x18},
258 {0x4504, 0x04},
259 {0x4508, 0x02},
260 {0x4601, 0x10},
261 {0x4800, 0x00},
262 {0x4816, 0x52},
263 {0x4837, 0x16},
264 {0x5000, 0x7f},
265 {0x5001, 0x00},
266 {0x5005, 0x38},
267 {0x501e, 0x0d},
268 {0x5040, 0x00},
269 {0x5901, 0x00},
270 {0x3800, 0x00},
271 {0x3801, 0x00},
272 {0x3802, 0x00},
273 {0x3803, 0x00},
274 {0x3804, 0x07},
275 {0x3805, 0x8f},
276 {0x3806, 0x04},
277 {0x3807, 0x47},
278 {0x3808, 0x07},
279 {0x3809, 0x8c},
280 {0x380a, 0x04},
281 {0x380b, 0x44},
282 {0x3810, 0x00},
283 {0x3811, 0x00},
284 {0x3812, 0x00},
285 {0x3813, 0x01},
286};
287
288static const char * const ov2740_test_pattern_menu[] = {
289 "Disabled",
290 "Color Bar",
291 "Top-Bottom Darker Color Bar",
292 "Right-Left Darker Color Bar",
293 "Bottom-Top Darker Color Bar",
294};
295
296static const s64 link_freq_menu_items[] = {
297 OV2740_LINK_FREQ_360MHZ,
298};
299
300static const struct ov2740_link_freq_config link_freq_configs[] = {
301 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
302 .reg_list = {
303 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
304 .regs = mipi_data_rate_720mbps,
305 }
306 },
307};
308
309static const struct ov2740_mode supported_modes[] = {
310 {
311 .width = 1932,
312 .height = 1092,
313 .hts = 1080,
314 .vts_def = OV2740_VTS_DEF,
315 .vts_min = OV2740_VTS_MIN,
316 .reg_list = {
317 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
318 .regs = mode_1932x1092_regs,
319 },
320 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
321 },
322};
323
324struct ov2740 {
325 struct v4l2_subdev sd;
326 struct media_pad pad;
327 struct v4l2_ctrl_handler ctrl_handler;
328
329 /* V4L2 Controls */
330 struct v4l2_ctrl *link_freq;
331 struct v4l2_ctrl *pixel_rate;
332 struct v4l2_ctrl *vblank;
333 struct v4l2_ctrl *hblank;
334 struct v4l2_ctrl *exposure;
335
336 /* Current mode */
337 const struct ov2740_mode *cur_mode;
338
339 /* To serialize asynchronus callbacks */
340 struct mutex mutex;
341
342 /* Streaming on/off */
343 bool streaming;
344
345 /* NVM data inforamtion */
346 struct nvm_data *nvm;
347
348 /* True if the device has been identified */
349 bool identified;
350};
351
352static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
353{
354 return container_of(subdev, struct ov2740, sd);
355}
356
357static u64 to_pixel_rate(u32 f_index)
358{
359 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
360
361 do_div(pixel_rate, OV2740_RGB_DEPTH);
362
363 return pixel_rate;
364}
365
366static u64 to_pixels_per_line(u32 hts, u32 f_index)
367{
368 u64 ppl = hts * to_pixel_rate(f_index);
369
370 do_div(ppl, OV2740_SCLK);
371
372 return ppl;
373}
374
375static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
376{
377 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
378 struct i2c_msg msgs[2];
379 u8 addr_buf[2];
380 u8 data_buf[4] = {0};
381 int ret;
382
383 if (len > sizeof(data_buf))
384 return -EINVAL;
385
386 put_unaligned_be16(reg, addr_buf);
387 msgs[0].addr = client->addr;
388 msgs[0].flags = 0;
389 msgs[0].len = sizeof(addr_buf);
390 msgs[0].buf = addr_buf;
391 msgs[1].addr = client->addr;
392 msgs[1].flags = I2C_M_RD;
393 msgs[1].len = len;
394 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
395
396 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
397 if (ret != ARRAY_SIZE(msgs))
398 return ret < 0 ? ret : -EIO;
399
400 *val = get_unaligned_be32(data_buf);
401
402 return 0;
403}
404
405static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
406{
407 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
408 u8 buf[6];
409 int ret;
410
411 if (len > 4)
412 return -EINVAL;
413
414 put_unaligned_be16(reg, buf);
415 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
416
417 ret = i2c_master_send(client, buf, len + 2);
418 if (ret != len + 2)
419 return ret < 0 ? ret : -EIO;
420
421 return 0;
422}
423
424static int ov2740_write_reg_list(struct ov2740 *ov2740,
425 const struct ov2740_reg_list *r_list)
426{
427 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
428 unsigned int i;
429 int ret;
430
431 for (i = 0; i < r_list->num_of_regs; i++) {
432 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
433 r_list->regs[i].val);
434 if (ret) {
435 dev_err_ratelimited(&client->dev,
436 "write reg 0x%4.4x return err = %d\n",
437 r_list->regs[i].address, ret);
438 return ret;
439 }
440 }
441
442 return 0;
443}
444
445static int ov2740_identify_module(struct ov2740 *ov2740)
446{
447 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
448 int ret;
449 u32 val;
450
451 if (ov2740->identified)
452 return 0;
453
454 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
455 if (ret)
456 return ret;
457
458 if (val != OV2740_CHIP_ID) {
459 dev_err(&client->dev, "chip id mismatch: %x != %x\n",
460 OV2740_CHIP_ID, val);
461 return -ENXIO;
462 }
463
464 ov2740->identified = true;
465
466 return 0;
467}
468
469static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
470{
471 int ret;
472
473 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
474 OV2740_GROUP_HOLD_START);
475 if (ret)
476 return ret;
477
478 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
479 if (ret)
480 return ret;
481
482 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
483 if (ret)
484 return ret;
485
486 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
487 if (ret)
488 return ret;
489
490 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
491 OV2740_GROUP_HOLD_END);
492 if (ret)
493 return ret;
494
495 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
496 OV2740_GROUP_HOLD_LAUNCH);
497 return ret;
498}
499
500static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
501{
502 if (pattern)
503 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
504 OV2740_TEST_PATTERN_ENABLE;
505
506 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
507}
508
509static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
510{
511 struct ov2740 *ov2740 = container_of(ctrl->handler,
512 struct ov2740, ctrl_handler);
513 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
514 s64 exposure_max;
515 int ret;
516
517 /* Propagate change of current control to all related controls */
518 if (ctrl->id == V4L2_CID_VBLANK) {
519 /* Update max exposure while meeting expected vblanking */
520 exposure_max = ov2740->cur_mode->height + ctrl->val -
521 OV2740_EXPOSURE_MAX_MARGIN;
522 __v4l2_ctrl_modify_range(ov2740->exposure,
523 ov2740->exposure->minimum,
524 exposure_max, ov2740->exposure->step,
525 exposure_max);
526 }
527
528 /* V4L2 controls values will be applied only when power is already up */
529 if (!pm_runtime_get_if_in_use(&client->dev))
530 return 0;
531
532 switch (ctrl->id) {
533 case V4L2_CID_ANALOGUE_GAIN:
534 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
535 ctrl->val);
536 break;
537
538 case V4L2_CID_DIGITAL_GAIN:
539 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
540 break;
541
542 case V4L2_CID_EXPOSURE:
543 /* 4 least significant bits of expsoure are fractional part */
544 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
545 ctrl->val << 4);
546 break;
547
548 case V4L2_CID_VBLANK:
549 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
550 ov2740->cur_mode->height + ctrl->val);
551 break;
552
553 case V4L2_CID_TEST_PATTERN:
554 ret = ov2740_test_pattern(ov2740, ctrl->val);
555 break;
556
557 default:
558 ret = -EINVAL;
559 break;
560 }
561
562 pm_runtime_put(&client->dev);
563
564 return ret;
565}
566
567static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
568 .s_ctrl = ov2740_set_ctrl,
569};
570
571static int ov2740_init_controls(struct ov2740 *ov2740)
572{
573 struct v4l2_ctrl_handler *ctrl_hdlr;
574 const struct ov2740_mode *cur_mode;
575 s64 exposure_max, h_blank, pixel_rate;
576 u32 vblank_min, vblank_max, vblank_default;
577 int size;
578 int ret;
579
580 ctrl_hdlr = &ov2740->ctrl_handler;
581 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
582 if (ret)
583 return ret;
584
585 ctrl_hdlr->lock = &ov2740->mutex;
586 cur_mode = ov2740->cur_mode;
587 size = ARRAY_SIZE(link_freq_menu_items);
588
589 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
590 V4L2_CID_LINK_FREQ,
591 size - 1, 0,
592 link_freq_menu_items);
593 if (ov2740->link_freq)
594 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
595
596 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
597 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
598 V4L2_CID_PIXEL_RATE, 0,
599 pixel_rate, 1, pixel_rate);
600
601 vblank_min = cur_mode->vts_min - cur_mode->height;
602 vblank_max = OV2740_VTS_MAX - cur_mode->height;
603 vblank_default = cur_mode->vts_def - cur_mode->height;
604 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
605 V4L2_CID_VBLANK, vblank_min,
606 vblank_max, 1, vblank_default);
607
608 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
609 h_blank -= cur_mode->width;
610 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
611 V4L2_CID_HBLANK, h_blank, h_blank, 1,
612 h_blank);
613 if (ov2740->hblank)
614 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
615
616 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
617 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
618 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
619 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
620 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
621 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
622 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
623 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
624 V4L2_CID_EXPOSURE,
625 OV2740_EXPOSURE_MIN, exposure_max,
626 OV2740_EXPOSURE_STEP,
627 exposure_max);
628 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
629 V4L2_CID_TEST_PATTERN,
630 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
631 0, 0, ov2740_test_pattern_menu);
632 if (ctrl_hdlr->error)
633 return ctrl_hdlr->error;
634
635 ov2740->sd.ctrl_handler = ctrl_hdlr;
636
637 return 0;
638}
639
640static void ov2740_update_pad_format(const struct ov2740_mode *mode,
641 struct v4l2_mbus_framefmt *fmt)
642{
643 fmt->width = mode->width;
644 fmt->height = mode->height;
645 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
646 fmt->field = V4L2_FIELD_NONE;
647}
648
649static int ov2740_load_otp_data(struct nvm_data *nvm)
650{
651 struct device *dev = regmap_get_device(nvm->regmap);
652 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
653 u32 isp_ctrl00 = 0;
654 u32 isp_ctrl01 = 0;
655 int ret;
656
657 if (nvm->nvm_buffer)
658 return 0;
659
660 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
661 if (!nvm->nvm_buffer)
662 return -ENOMEM;
663
664 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
665 if (ret) {
666 dev_err(dev, "failed to read ISP CTRL00\n");
667 goto err;
668 }
669
670 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
671 if (ret) {
672 dev_err(dev, "failed to read ISP CTRL01\n");
673 goto err;
674 }
675
676 /* Clear bit 5 of ISP CTRL00 */
677 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
678 isp_ctrl00 & ~BIT(5));
679 if (ret) {
680 dev_err(dev, "failed to set ISP CTRL00\n");
681 goto err;
682 }
683
684 /* Clear bit 7 of ISP CTRL01 */
685 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
686 isp_ctrl01 & ~BIT(7));
687 if (ret) {
688 dev_err(dev, "failed to set ISP CTRL01\n");
689 goto err;
690 }
691
692 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
693 OV2740_MODE_STREAMING);
694 if (ret) {
695 dev_err(dev, "failed to set streaming mode\n");
696 goto err;
697 }
698
699 /*
700 * Users are not allowed to access OTP-related registers and memory
701 * during the 20 ms period after streaming starts (0x100 = 0x01).
702 */
703 msleep(20);
704
705 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
706 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
707 if (ret) {
708 dev_err(dev, "failed to read OTP data, ret %d\n", ret);
709 goto err;
710 }
711
712 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
713 OV2740_MODE_STANDBY);
714 if (ret) {
715 dev_err(dev, "failed to set streaming mode\n");
716 goto err;
717 }
718
719 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
720 if (ret) {
721 dev_err(dev, "failed to set ISP CTRL01\n");
722 goto err;
723 }
724
725 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
726 if (ret) {
727 dev_err(dev, "failed to set ISP CTRL00\n");
728 goto err;
729 }
730
731 return 0;
732err:
733 kfree(nvm->nvm_buffer);
734 nvm->nvm_buffer = NULL;
735
736 return ret;
737}
738
739static int ov2740_start_streaming(struct ov2740 *ov2740)
740{
741 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
742 const struct ov2740_reg_list *reg_list;
743 int link_freq_index;
744 int ret;
745
746 ret = ov2740_identify_module(ov2740);
747 if (ret)
748 return ret;
749
750 if (ov2740->nvm)
751 ov2740_load_otp_data(ov2740->nvm);
752
753 link_freq_index = ov2740->cur_mode->link_freq_index;
754 reg_list = &link_freq_configs[link_freq_index].reg_list;
755 ret = ov2740_write_reg_list(ov2740, reg_list);
756 if (ret) {
757 dev_err(&client->dev, "failed to set plls\n");
758 return ret;
759 }
760
761 reg_list = &ov2740->cur_mode->reg_list;
762 ret = ov2740_write_reg_list(ov2740, reg_list);
763 if (ret) {
764 dev_err(&client->dev, "failed to set mode\n");
765 return ret;
766 }
767
768 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
769 if (ret)
770 return ret;
771
772 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
773 OV2740_MODE_STREAMING);
774 if (ret)
775 dev_err(&client->dev, "failed to start streaming\n");
776
777 return ret;
778}
779
780static void ov2740_stop_streaming(struct ov2740 *ov2740)
781{
782 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
783
784 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
785 OV2740_MODE_STANDBY))
786 dev_err(&client->dev, "failed to stop streaming\n");
787}
788
789static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
790{
791 struct ov2740 *ov2740 = to_ov2740(sd);
792 struct i2c_client *client = v4l2_get_subdevdata(sd);
793 int ret = 0;
794
795 if (ov2740->streaming == enable)
796 return 0;
797
798 mutex_lock(&ov2740->mutex);
799 if (enable) {
800 ret = pm_runtime_resume_and_get(&client->dev);
801 if (ret < 0) {
802 mutex_unlock(&ov2740->mutex);
803 return ret;
804 }
805
806 ret = ov2740_start_streaming(ov2740);
807 if (ret) {
808 enable = 0;
809 ov2740_stop_streaming(ov2740);
810 pm_runtime_put(&client->dev);
811 }
812 } else {
813 ov2740_stop_streaming(ov2740);
814 pm_runtime_put(&client->dev);
815 }
816
817 ov2740->streaming = enable;
818 mutex_unlock(&ov2740->mutex);
819
820 return ret;
821}
822
823static int ov2740_suspend(struct device *dev)
824{
825 struct v4l2_subdev *sd = dev_get_drvdata(dev);
826 struct ov2740 *ov2740 = to_ov2740(sd);
827
828 mutex_lock(&ov2740->mutex);
829 if (ov2740->streaming)
830 ov2740_stop_streaming(ov2740);
831
832 mutex_unlock(&ov2740->mutex);
833
834 return 0;
835}
836
837static int ov2740_resume(struct device *dev)
838{
839 struct v4l2_subdev *sd = dev_get_drvdata(dev);
840 struct ov2740 *ov2740 = to_ov2740(sd);
841 int ret = 0;
842
843 mutex_lock(&ov2740->mutex);
844 if (!ov2740->streaming)
845 goto exit;
846
847 ret = ov2740_start_streaming(ov2740);
848 if (ret) {
849 ov2740->streaming = false;
850 ov2740_stop_streaming(ov2740);
851 }
852
853exit:
854 mutex_unlock(&ov2740->mutex);
855 return ret;
856}
857
858static int ov2740_set_format(struct v4l2_subdev *sd,
859 struct v4l2_subdev_state *sd_state,
860 struct v4l2_subdev_format *fmt)
861{
862 struct ov2740 *ov2740 = to_ov2740(sd);
863 const struct ov2740_mode *mode;
864 s32 vblank_def, h_blank;
865
866 mode = v4l2_find_nearest_size(supported_modes,
867 ARRAY_SIZE(supported_modes), width,
868 height, fmt->format.width,
869 fmt->format.height);
870
871 mutex_lock(&ov2740->mutex);
872 ov2740_update_pad_format(mode, &fmt->format);
873 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
874 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
875 } else {
876 ov2740->cur_mode = mode;
877 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
878 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
879 to_pixel_rate(mode->link_freq_index));
880
881 /* Update limits and set FPS to default */
882 vblank_def = mode->vts_def - mode->height;
883 __v4l2_ctrl_modify_range(ov2740->vblank,
884 mode->vts_min - mode->height,
885 OV2740_VTS_MAX - mode->height, 1,
886 vblank_def);
887 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
888 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
889 mode->width;
890 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
891 h_blank);
892 }
893 mutex_unlock(&ov2740->mutex);
894
895 return 0;
896}
897
898static int ov2740_get_format(struct v4l2_subdev *sd,
899 struct v4l2_subdev_state *sd_state,
900 struct v4l2_subdev_format *fmt)
901{
902 struct ov2740 *ov2740 = to_ov2740(sd);
903
904 mutex_lock(&ov2740->mutex);
905 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
906 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd,
907 sd_state,
908 fmt->pad);
909 else
910 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
911
912 mutex_unlock(&ov2740->mutex);
913
914 return 0;
915}
916
917static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
918 struct v4l2_subdev_state *sd_state,
919 struct v4l2_subdev_mbus_code_enum *code)
920{
921 if (code->index > 0)
922 return -EINVAL;
923
924 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
925
926 return 0;
927}
928
929static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
930 struct v4l2_subdev_state *sd_state,
931 struct v4l2_subdev_frame_size_enum *fse)
932{
933 if (fse->index >= ARRAY_SIZE(supported_modes))
934 return -EINVAL;
935
936 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
937 return -EINVAL;
938
939 fse->min_width = supported_modes[fse->index].width;
940 fse->max_width = fse->min_width;
941 fse->min_height = supported_modes[fse->index].height;
942 fse->max_height = fse->min_height;
943
944 return 0;
945}
946
947static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
948{
949 struct ov2740 *ov2740 = to_ov2740(sd);
950
951 mutex_lock(&ov2740->mutex);
952 ov2740_update_pad_format(&supported_modes[0],
953 v4l2_subdev_get_try_format(sd, fh->state, 0));
954 mutex_unlock(&ov2740->mutex);
955
956 return 0;
957}
958
959static const struct v4l2_subdev_video_ops ov2740_video_ops = {
960 .s_stream = ov2740_set_stream,
961};
962
963static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
964 .set_fmt = ov2740_set_format,
965 .get_fmt = ov2740_get_format,
966 .enum_mbus_code = ov2740_enum_mbus_code,
967 .enum_frame_size = ov2740_enum_frame_size,
968};
969
970static const struct v4l2_subdev_ops ov2740_subdev_ops = {
971 .video = &ov2740_video_ops,
972 .pad = &ov2740_pad_ops,
973};
974
975static const struct media_entity_operations ov2740_subdev_entity_ops = {
976 .link_validate = v4l2_subdev_link_validate,
977};
978
979static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
980 .open = ov2740_open,
981};
982
983static int ov2740_check_hwcfg(struct device *dev)
984{
985 struct fwnode_handle *ep;
986 struct fwnode_handle *fwnode = dev_fwnode(dev);
987 struct v4l2_fwnode_endpoint bus_cfg = {
988 .bus_type = V4L2_MBUS_CSI2_DPHY
989 };
990 u32 mclk;
991 int ret;
992 unsigned int i, j;
993
994 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
995 if (ret)
996 return ret;
997
998 if (mclk != OV2740_MCLK)
999 return dev_err_probe(dev, -EINVAL,
1000 "external clock %d is not supported\n",
1001 mclk);
1002
1003 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1004 if (!ep)
1005 return -ENXIO;
1006
1007 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1008 fwnode_handle_put(ep);
1009 if (ret)
1010 return ret;
1011
1012 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1013 ret = dev_err_probe(dev, -EINVAL,
1014 "number of CSI2 data lanes %d is not supported\n",
1015 bus_cfg.bus.mipi_csi2.num_data_lanes);
1016 goto check_hwcfg_error;
1017 }
1018
1019 if (!bus_cfg.nr_of_link_frequencies) {
1020 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n");
1021 goto check_hwcfg_error;
1022 }
1023
1024 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1025 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1026 if (link_freq_menu_items[i] ==
1027 bus_cfg.link_frequencies[j])
1028 break;
1029 }
1030
1031 if (j == bus_cfg.nr_of_link_frequencies) {
1032 ret = dev_err_probe(dev, -EINVAL,
1033 "no link frequency %lld supported\n",
1034 link_freq_menu_items[i]);
1035 goto check_hwcfg_error;
1036 }
1037 }
1038
1039check_hwcfg_error:
1040 v4l2_fwnode_endpoint_free(&bus_cfg);
1041
1042 return ret;
1043}
1044
1045static void ov2740_remove(struct i2c_client *client)
1046{
1047 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1048 struct ov2740 *ov2740 = to_ov2740(sd);
1049
1050 v4l2_async_unregister_subdev(sd);
1051 media_entity_cleanup(&sd->entity);
1052 v4l2_ctrl_handler_free(sd->ctrl_handler);
1053 pm_runtime_disable(&client->dev);
1054 mutex_destroy(&ov2740->mutex);
1055}
1056
1057static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1058 size_t count)
1059{
1060 struct nvm_data *nvm = priv;
1061 struct device *dev = regmap_get_device(nvm->regmap);
1062 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
1063 int ret = 0;
1064
1065 mutex_lock(&ov2740->mutex);
1066
1067 if (nvm->nvm_buffer) {
1068 memcpy(val, nvm->nvm_buffer + off, count);
1069 goto exit;
1070 }
1071
1072 ret = pm_runtime_resume_and_get(dev);
1073 if (ret < 0) {
1074 goto exit;
1075 }
1076
1077 ret = ov2740_load_otp_data(nvm);
1078 if (!ret)
1079 memcpy(val, nvm->nvm_buffer + off, count);
1080
1081 pm_runtime_put(dev);
1082exit:
1083 mutex_unlock(&ov2740->mutex);
1084 return ret;
1085}
1086
1087static int ov2740_register_nvmem(struct i2c_client *client,
1088 struct ov2740 *ov2740)
1089{
1090 struct nvm_data *nvm;
1091 struct regmap_config regmap_config = { };
1092 struct nvmem_config nvmem_config = { };
1093 struct regmap *regmap;
1094 struct device *dev = &client->dev;
1095
1096 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1097 if (!nvm)
1098 return -ENOMEM;
1099
1100 regmap_config.val_bits = 8;
1101 regmap_config.reg_bits = 16;
1102 regmap_config.disable_locking = true;
1103 regmap = devm_regmap_init_i2c(client, ®map_config);
1104 if (IS_ERR(regmap))
1105 return PTR_ERR(regmap);
1106
1107 nvm->regmap = regmap;
1108
1109 nvmem_config.name = dev_name(dev);
1110 nvmem_config.dev = dev;
1111 nvmem_config.read_only = true;
1112 nvmem_config.root_only = true;
1113 nvmem_config.owner = THIS_MODULE;
1114 nvmem_config.compat = true;
1115 nvmem_config.base_dev = dev;
1116 nvmem_config.reg_read = ov2740_nvmem_read;
1117 nvmem_config.reg_write = NULL;
1118 nvmem_config.priv = nvm;
1119 nvmem_config.stride = 1;
1120 nvmem_config.word_size = 1;
1121 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1122
1123 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1124 if (IS_ERR(nvm->nvmem))
1125 return PTR_ERR(nvm->nvmem);
1126
1127 ov2740->nvm = nvm;
1128 return 0;
1129}
1130
1131static int ov2740_probe(struct i2c_client *client)
1132{
1133 struct device *dev = &client->dev;
1134 struct ov2740 *ov2740;
1135 bool full_power;
1136 int ret;
1137
1138 ret = ov2740_check_hwcfg(&client->dev);
1139 if (ret)
1140 return dev_err_probe(dev, ret, "failed to check HW configuration\n");
1141
1142 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1143 if (!ov2740)
1144 return -ENOMEM;
1145
1146 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1147 full_power = acpi_dev_state_d0(&client->dev);
1148 if (full_power) {
1149 ret = ov2740_identify_module(ov2740);
1150 if (ret)
1151 return dev_err_probe(dev, ret, "failed to find sensor\n");
1152 }
1153
1154 mutex_init(&ov2740->mutex);
1155 ov2740->cur_mode = &supported_modes[0];
1156 ret = ov2740_init_controls(ov2740);
1157 if (ret) {
1158 dev_err_probe(dev, ret, "failed to init controls\n");
1159 goto probe_error_v4l2_ctrl_handler_free;
1160 }
1161
1162 ov2740->sd.internal_ops = &ov2740_internal_ops;
1163 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1164 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1165 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1166 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1167 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1168 if (ret) {
1169 dev_err_probe(dev, ret, "failed to init entity pads\n");
1170 goto probe_error_v4l2_ctrl_handler_free;
1171 }
1172
1173 ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1174 if (ret < 0) {
1175 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
1176 goto probe_error_media_entity_cleanup;
1177 }
1178
1179 ret = ov2740_register_nvmem(client, ov2740);
1180 if (ret)
1181 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1182
1183 /* Set the device's state to active if it's in D0 state. */
1184 if (full_power)
1185 pm_runtime_set_active(&client->dev);
1186 pm_runtime_enable(&client->dev);
1187 pm_runtime_idle(&client->dev);
1188
1189 return 0;
1190
1191probe_error_media_entity_cleanup:
1192 media_entity_cleanup(&ov2740->sd.entity);
1193
1194probe_error_v4l2_ctrl_handler_free:
1195 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1196 mutex_destroy(&ov2740->mutex);
1197
1198 return ret;
1199}
1200
1201static DEFINE_SIMPLE_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume);
1202
1203static const struct acpi_device_id ov2740_acpi_ids[] = {
1204 {"INT3474"},
1205 {}
1206};
1207
1208MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1209
1210static struct i2c_driver ov2740_i2c_driver = {
1211 .driver = {
1212 .name = "ov2740",
1213 .pm = pm_sleep_ptr(&ov2740_pm_ops),
1214 .acpi_match_table = ov2740_acpi_ids,
1215 },
1216 .probe_new = ov2740_probe,
1217 .remove = ov2740_remove,
1218 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1219};
1220
1221module_i2c_driver(ov2740_i2c_driver);
1222
1223MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1224MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1225MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1226MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1227MODULE_LICENSE("GPL v2");