Linux kernel mirror (for testing)
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linux
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __AMDGPU_H__
29#define __AMDGPU_H__
30
31#ifdef pr_fmt
32#undef pr_fmt
33#endif
34
35#define pr_fmt(fmt) "amdgpu: " fmt
36
37#ifdef dev_fmt
38#undef dev_fmt
39#endif
40
41#define dev_fmt(fmt) "amdgpu: " fmt
42
43#include "amdgpu_ctx.h"
44
45#include <linux/atomic.h>
46#include <linux/wait.h>
47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54
55#include <drm/ttm/ttm_bo_api.h>
56#include <drm/ttm/ttm_bo_driver.h>
57#include <drm/ttm/ttm_placement.h>
58#include <drm/ttm/ttm_execbuf_util.h>
59
60#include <drm/amdgpu_drm.h>
61#include <drm/drm_gem.h>
62#include <drm/drm_ioctl.h>
63
64#include <kgd_kfd_interface.h>
65#include "dm_pp_interface.h"
66#include "kgd_pp_interface.h"
67
68#include "amd_shared.h"
69#include "amdgpu_mode.h"
70#include "amdgpu_ih.h"
71#include "amdgpu_irq.h"
72#include "amdgpu_ucode.h"
73#include "amdgpu_ttm.h"
74#include "amdgpu_psp.h"
75#include "amdgpu_gds.h"
76#include "amdgpu_sync.h"
77#include "amdgpu_ring.h"
78#include "amdgpu_vm.h"
79#include "amdgpu_dpm.h"
80#include "amdgpu_acp.h"
81#include "amdgpu_uvd.h"
82#include "amdgpu_vce.h"
83#include "amdgpu_vcn.h"
84#include "amdgpu_jpeg.h"
85#include "amdgpu_gmc.h"
86#include "amdgpu_gfx.h"
87#include "amdgpu_sdma.h"
88#include "amdgpu_lsdma.h"
89#include "amdgpu_nbio.h"
90#include "amdgpu_hdp.h"
91#include "amdgpu_dm.h"
92#include "amdgpu_virt.h"
93#include "amdgpu_csa.h"
94#include "amdgpu_mes_ctx.h"
95#include "amdgpu_gart.h"
96#include "amdgpu_debugfs.h"
97#include "amdgpu_job.h"
98#include "amdgpu_bo_list.h"
99#include "amdgpu_gem.h"
100#include "amdgpu_doorbell.h"
101#include "amdgpu_amdkfd.h"
102#include "amdgpu_discovery.h"
103#include "amdgpu_mes.h"
104#include "amdgpu_umc.h"
105#include "amdgpu_mmhub.h"
106#include "amdgpu_gfxhub.h"
107#include "amdgpu_df.h"
108#include "amdgpu_smuio.h"
109#include "amdgpu_fdinfo.h"
110#include "amdgpu_mca.h"
111#include "amdgpu_ras.h"
112
113#define MAX_GPU_INSTANCE 16
114
115struct amdgpu_gpu_instance
116{
117 struct amdgpu_device *adev;
118 int mgpu_fan_enabled;
119};
120
121struct amdgpu_mgpu_info
122{
123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
124 struct mutex mutex;
125 uint32_t num_gpu;
126 uint32_t num_dgpu;
127 uint32_t num_apu;
128
129 /* delayed reset_func for XGMI configuration if necessary */
130 struct delayed_work delayed_reset_work;
131 bool pending_reset;
132};
133
134enum amdgpu_ss {
135 AMDGPU_SS_DRV_LOAD,
136 AMDGPU_SS_DEV_D0,
137 AMDGPU_SS_DEV_D3,
138 AMDGPU_SS_DRV_UNLOAD
139};
140
141struct amdgpu_watchdog_timer
142{
143 bool timeout_fatal_disable;
144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
145};
146
147#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
148
149/*
150 * Modules parameters.
151 */
152extern int amdgpu_modeset;
153extern int amdgpu_vram_limit;
154extern int amdgpu_vis_vram_limit;
155extern int amdgpu_gart_size;
156extern int amdgpu_gtt_size;
157extern int amdgpu_moverate;
158extern int amdgpu_audio;
159extern int amdgpu_disp_priority;
160extern int amdgpu_hw_i2c;
161extern int amdgpu_pcie_gen2;
162extern int amdgpu_msi;
163extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
164extern int amdgpu_dpm;
165extern int amdgpu_fw_load_type;
166extern int amdgpu_aspm;
167extern int amdgpu_runtime_pm;
168extern uint amdgpu_ip_block_mask;
169extern int amdgpu_bapm;
170extern int amdgpu_deep_color;
171extern int amdgpu_vm_size;
172extern int amdgpu_vm_block_size;
173extern int amdgpu_vm_fragment_size;
174extern int amdgpu_vm_fault_stop;
175extern int amdgpu_vm_debug;
176extern int amdgpu_vm_update_mode;
177extern int amdgpu_exp_hw_support;
178extern int amdgpu_dc;
179extern int amdgpu_sched_jobs;
180extern int amdgpu_sched_hw_submission;
181extern uint amdgpu_pcie_gen_cap;
182extern uint amdgpu_pcie_lane_cap;
183extern u64 amdgpu_cg_mask;
184extern uint amdgpu_pg_mask;
185extern uint amdgpu_sdma_phase_quantum;
186extern char *amdgpu_disable_cu;
187extern char *amdgpu_virtual_display;
188extern uint amdgpu_pp_feature_mask;
189extern uint amdgpu_force_long_training;
190extern int amdgpu_job_hang_limit;
191extern int amdgpu_lbpw;
192extern int amdgpu_compute_multipipe;
193extern int amdgpu_gpu_recovery;
194extern int amdgpu_emu_mode;
195extern uint amdgpu_smu_memory_pool_size;
196extern int amdgpu_smu_pptable_id;
197extern uint amdgpu_dc_feature_mask;
198extern uint amdgpu_dc_debug_mask;
199extern uint amdgpu_dc_visual_confirm;
200extern uint amdgpu_dm_abm_level;
201extern int amdgpu_backlight;
202extern struct amdgpu_mgpu_info mgpu_info;
203extern int amdgpu_ras_enable;
204extern uint amdgpu_ras_mask;
205extern int amdgpu_bad_page_threshold;
206extern bool amdgpu_ignore_bad_page_threshold;
207extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;
208extern int amdgpu_async_gfx_ring;
209extern int amdgpu_mcbp;
210extern int amdgpu_discovery;
211extern int amdgpu_mes;
212extern int amdgpu_mes_kiq;
213extern int amdgpu_noretry;
214extern int amdgpu_force_asic_type;
215extern int amdgpu_smartshift_bias;
216extern int amdgpu_use_xgmi_p2p;
217#ifdef CONFIG_HSA_AMD
218extern int sched_policy;
219extern bool debug_evictions;
220extern bool no_system_mem_limit;
221extern int halt_if_hws_hang;
222#else
223static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS;
224static const bool __maybe_unused debug_evictions; /* = false */
225static const bool __maybe_unused no_system_mem_limit;
226static const int __maybe_unused halt_if_hws_hang;
227#endif
228#ifdef CONFIG_HSA_AMD_P2P
229extern bool pcie_p2p;
230#endif
231
232extern int amdgpu_tmz;
233extern int amdgpu_reset_method;
234
235#ifdef CONFIG_DRM_AMDGPU_SI
236extern int amdgpu_si_support;
237#endif
238#ifdef CONFIG_DRM_AMDGPU_CIK
239extern int amdgpu_cik_support;
240#endif
241extern int amdgpu_num_kcq;
242
243#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
244extern int amdgpu_vcnfw_log;
245
246#define AMDGPU_VM_MAX_NUM_CTX 4096
247#define AMDGPU_SG_THRESHOLD (256*1024*1024)
248#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
249#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
250#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
251#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
252#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
253#define AMDGPUFB_CONN_LIMIT 4
254#define AMDGPU_BIOS_NUM_SCRATCH 16
255
256#define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */
257
258/* hard reset data */
259#define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
260
261/* reset flags */
262#define AMDGPU_RESET_GFX (1 << 0)
263#define AMDGPU_RESET_COMPUTE (1 << 1)
264#define AMDGPU_RESET_DMA (1 << 2)
265#define AMDGPU_RESET_CP (1 << 3)
266#define AMDGPU_RESET_GRBM (1 << 4)
267#define AMDGPU_RESET_DMA1 (1 << 5)
268#define AMDGPU_RESET_RLC (1 << 6)
269#define AMDGPU_RESET_SEM (1 << 7)
270#define AMDGPU_RESET_IH (1 << 8)
271#define AMDGPU_RESET_VMC (1 << 9)
272#define AMDGPU_RESET_MC (1 << 10)
273#define AMDGPU_RESET_DISPLAY (1 << 11)
274#define AMDGPU_RESET_UVD (1 << 12)
275#define AMDGPU_RESET_VCE (1 << 13)
276#define AMDGPU_RESET_VCE1 (1 << 14)
277
278/* max cursor sizes (in pixels) */
279#define CIK_CURSOR_WIDTH 128
280#define CIK_CURSOR_HEIGHT 128
281
282/* smart shift bias level limits */
283#define AMDGPU_SMARTSHIFT_MAX_BIAS (100)
284#define AMDGPU_SMARTSHIFT_MIN_BIAS (-100)
285
286struct amdgpu_device;
287struct amdgpu_irq_src;
288struct amdgpu_fpriv;
289struct amdgpu_bo_va_mapping;
290struct kfd_vm_fault_info;
291struct amdgpu_hive_info;
292struct amdgpu_reset_context;
293struct amdgpu_reset_control;
294
295enum amdgpu_cp_irq {
296 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
297 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP,
298 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
299 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
300 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
301 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
302 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
303 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
304 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
305 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
306
307 AMDGPU_CP_IRQ_LAST
308};
309
310enum amdgpu_thermal_irq {
311 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
312 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
313
314 AMDGPU_THERMAL_IRQ_LAST
315};
316
317enum amdgpu_kiq_irq {
318 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
319 AMDGPU_CP_KIQ_IRQ_LAST
320};
321#define SRIOV_USEC_TIMEOUT 1200000 /* wait 12 * 100ms for SRIOV */
322#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
323#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
324#define MAX_KIQ_REG_TRY 1000
325
326int amdgpu_device_ip_set_clockgating_state(void *dev,
327 enum amd_ip_block_type block_type,
328 enum amd_clockgating_state state);
329int amdgpu_device_ip_set_powergating_state(void *dev,
330 enum amd_ip_block_type block_type,
331 enum amd_powergating_state state);
332void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
333 u64 *flags);
334int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
335 enum amd_ip_block_type block_type);
336bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
337 enum amd_ip_block_type block_type);
338
339#define AMDGPU_MAX_IP_NUM 16
340
341struct amdgpu_ip_block_status {
342 bool valid;
343 bool sw;
344 bool hw;
345 bool late_initialized;
346 bool hang;
347};
348
349struct amdgpu_ip_block_version {
350 const enum amd_ip_block_type type;
351 const u32 major;
352 const u32 minor;
353 const u32 rev;
354 const struct amd_ip_funcs *funcs;
355};
356
357#define HW_REV(_Major, _Minor, _Rev) \
358 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev)))
359
360struct amdgpu_ip_block {
361 struct amdgpu_ip_block_status status;
362 const struct amdgpu_ip_block_version *version;
363};
364
365int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
366 enum amd_ip_block_type type,
367 u32 major, u32 minor);
368
369struct amdgpu_ip_block *
370amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
371 enum amd_ip_block_type type);
372
373int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
374 const struct amdgpu_ip_block_version *ip_block_version);
375
376/*
377 * BIOS.
378 */
379bool amdgpu_get_bios(struct amdgpu_device *adev);
380bool amdgpu_read_bios(struct amdgpu_device *adev);
381bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev,
382 u8 *bios, u32 length_bytes);
383/*
384 * Clocks
385 */
386
387#define AMDGPU_MAX_PPLL 3
388
389struct amdgpu_clock {
390 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
391 struct amdgpu_pll spll;
392 struct amdgpu_pll mpll;
393 /* 10 Khz units */
394 uint32_t default_mclk;
395 uint32_t default_sclk;
396 uint32_t default_dispclk;
397 uint32_t current_dispclk;
398 uint32_t dp_extclk;
399 uint32_t max_pixel_clock;
400};
401
402/* sub-allocation manager, it has to be protected by another lock.
403 * By conception this is an helper for other part of the driver
404 * like the indirect buffer or semaphore, which both have their
405 * locking.
406 *
407 * Principe is simple, we keep a list of sub allocation in offset
408 * order (first entry has offset == 0, last entry has the highest
409 * offset).
410 *
411 * When allocating new object we first check if there is room at
412 * the end total_size - (last_object_offset + last_object_size) >=
413 * alloc_size. If so we allocate new object there.
414 *
415 * When there is not enough room at the end, we start waiting for
416 * each sub object until we reach object_offset+object_size >=
417 * alloc_size, this object then become the sub object we return.
418 *
419 * Alignment can't be bigger than page size.
420 *
421 * Hole are not considered for allocation to keep things simple.
422 * Assumption is that there won't be hole (all object on same
423 * alignment).
424 */
425
426#define AMDGPU_SA_NUM_FENCE_LISTS 32
427
428struct amdgpu_sa_manager {
429 wait_queue_head_t wq;
430 struct amdgpu_bo *bo;
431 struct list_head *hole;
432 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
433 struct list_head olist;
434 unsigned size;
435 uint64_t gpu_addr;
436 void *cpu_ptr;
437 uint32_t domain;
438 uint32_t align;
439};
440
441/* sub-allocation buffer */
442struct amdgpu_sa_bo {
443 struct list_head olist;
444 struct list_head flist;
445 struct amdgpu_sa_manager *manager;
446 unsigned soffset;
447 unsigned eoffset;
448 struct dma_fence *fence;
449};
450
451int amdgpu_fence_slab_init(void);
452void amdgpu_fence_slab_fini(void);
453
454/*
455 * IRQS.
456 */
457
458struct amdgpu_flip_work {
459 struct delayed_work flip_work;
460 struct work_struct unpin_work;
461 struct amdgpu_device *adev;
462 int crtc_id;
463 u32 target_vblank;
464 uint64_t base;
465 struct drm_pending_vblank_event *event;
466 struct amdgpu_bo *old_abo;
467 unsigned shared_count;
468 struct dma_fence **shared;
469 struct dma_fence_cb cb;
470 bool async;
471};
472
473
474/*
475 * file private structure
476 */
477
478struct amdgpu_fpriv {
479 struct amdgpu_vm vm;
480 struct amdgpu_bo_va *prt_va;
481 struct amdgpu_bo_va *csa_va;
482 struct mutex bo_list_lock;
483 struct idr bo_list_handles;
484 struct amdgpu_ctx_mgr ctx_mgr;
485};
486
487int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
488
489/*
490 * Writeback
491 */
492#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */
493
494struct amdgpu_wb {
495 struct amdgpu_bo *wb_obj;
496 volatile uint32_t *wb;
497 uint64_t gpu_addr;
498 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
499 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
500};
501
502int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);
503void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);
504
505/*
506 * Benchmarking
507 */
508int amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
509
510/*
511 * ASIC specific register table accessible by UMD
512 */
513struct amdgpu_allowed_register_entry {
514 uint32_t reg_offset;
515 bool grbm_indexed;
516};
517
518enum amd_reset_method {
519 AMD_RESET_METHOD_NONE = -1,
520 AMD_RESET_METHOD_LEGACY = 0,
521 AMD_RESET_METHOD_MODE0,
522 AMD_RESET_METHOD_MODE1,
523 AMD_RESET_METHOD_MODE2,
524 AMD_RESET_METHOD_BACO,
525 AMD_RESET_METHOD_PCI,
526};
527
528struct amdgpu_video_codec_info {
529 u32 codec_type;
530 u32 max_width;
531 u32 max_height;
532 u32 max_pixels_per_frame;
533 u32 max_level;
534};
535
536#define codec_info_build(type, width, height, level) \
537 .codec_type = type,\
538 .max_width = width,\
539 .max_height = height,\
540 .max_pixels_per_frame = height * width,\
541 .max_level = level,
542
543struct amdgpu_video_codecs {
544 const u32 codec_count;
545 const struct amdgpu_video_codec_info *codec_array;
546};
547
548/*
549 * ASIC specific functions.
550 */
551struct amdgpu_asic_funcs {
552 bool (*read_disabled_bios)(struct amdgpu_device *adev);
553 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
554 u8 *bios, u32 length_bytes);
555 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
556 u32 sh_num, u32 reg_offset, u32 *value);
557 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
558 int (*reset)(struct amdgpu_device *adev);
559 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
560 /* get the reference clock */
561 u32 (*get_xclk)(struct amdgpu_device *adev);
562 /* MM block clocks */
563 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
564 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
565 /* static power management */
566 int (*get_pcie_lanes)(struct amdgpu_device *adev);
567 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
568 /* get config memsize register */
569 u32 (*get_config_memsize)(struct amdgpu_device *adev);
570 /* flush hdp write queue */
571 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
572 /* invalidate hdp read cache */
573 void (*invalidate_hdp)(struct amdgpu_device *adev,
574 struct amdgpu_ring *ring);
575 /* check if the asic needs a full reset of if soft reset will work */
576 bool (*need_full_reset)(struct amdgpu_device *adev);
577 /* initialize doorbell layout for specific asic*/
578 void (*init_doorbell_index)(struct amdgpu_device *adev);
579 /* PCIe bandwidth usage */
580 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0,
581 uint64_t *count1);
582 /* do we need to reset the asic at init time (e.g., kexec) */
583 bool (*need_reset_on_init)(struct amdgpu_device *adev);
584 /* PCIe replay counter */
585 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev);
586 /* device supports BACO */
587 bool (*supports_baco)(struct amdgpu_device *adev);
588 /* pre asic_init quirks */
589 void (*pre_asic_init)(struct amdgpu_device *adev);
590 /* enter/exit umd stable pstate */
591 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);
592 /* query video codecs */
593 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,
594 const struct amdgpu_video_codecs **codecs);
595};
596
597/*
598 * IOCTL.
599 */
600int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
601 struct drm_file *filp);
602
603int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
604int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
605 struct drm_file *filp);
606int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
607int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
608 struct drm_file *filp);
609
610/* VRAM scratch page for HDP bug, default vram page */
611struct amdgpu_vram_scratch {
612 struct amdgpu_bo *robj;
613 volatile uint32_t *ptr;
614 u64 gpu_addr;
615};
616
617/*
618 * CGS
619 */
620struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
621void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
622
623/*
624 * Core structure, functions and helpers.
625 */
626typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
627typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
628
629typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t);
630typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t);
631
632typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
633typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
634
635struct amdgpu_mmio_remap {
636 u32 reg_offset;
637 resource_size_t bus_addr;
638};
639
640/* Define the HW IP blocks will be used in driver , add more if necessary */
641enum amd_hw_ip_block_type {
642 GC_HWIP = 1,
643 HDP_HWIP,
644 SDMA0_HWIP,
645 SDMA1_HWIP,
646 SDMA2_HWIP,
647 SDMA3_HWIP,
648 SDMA4_HWIP,
649 SDMA5_HWIP,
650 SDMA6_HWIP,
651 SDMA7_HWIP,
652 LSDMA_HWIP,
653 MMHUB_HWIP,
654 ATHUB_HWIP,
655 NBIO_HWIP,
656 MP0_HWIP,
657 MP1_HWIP,
658 UVD_HWIP,
659 VCN_HWIP = UVD_HWIP,
660 JPEG_HWIP = VCN_HWIP,
661 VCN1_HWIP,
662 VCE_HWIP,
663 DF_HWIP,
664 DCE_HWIP,
665 OSSSYS_HWIP,
666 SMUIO_HWIP,
667 PWR_HWIP,
668 NBIF_HWIP,
669 THM_HWIP,
670 CLK_HWIP,
671 UMC_HWIP,
672 RSMU_HWIP,
673 XGMI_HWIP,
674 DCI_HWIP,
675 PCIE_HWIP,
676 MAX_HWIP
677};
678
679#define HWIP_MAX_INSTANCE 28
680
681#define HW_ID_MAX 300
682#define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
683#define IP_VERSION_MAJ(ver) ((ver) >> 16)
684#define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
685#define IP_VERSION_REV(ver) ((ver) & 0xFF)
686
687struct amd_powerplay {
688 void *pp_handle;
689 const struct amd_pm_funcs *pp_funcs;
690};
691
692struct ip_discovery_top;
693
694/* polaris10 kickers */
695#define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \
696 ((rid == 0xE3) || \
697 (rid == 0xE4) || \
698 (rid == 0xE5) || \
699 (rid == 0xE7) || \
700 (rid == 0xEF))) || \
701 ((did == 0x6FDF) && \
702 ((rid == 0xE7) || \
703 (rid == 0xEF) || \
704 (rid == 0xFF))))
705
706#define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \
707 ((rid == 0xE1) || \
708 (rid == 0xF7)))
709
710/* polaris11 kickers */
711#define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \
712 ((rid == 0xE0) || \
713 (rid == 0xE5))) || \
714 ((did == 0x67FF) && \
715 ((rid == 0xCF) || \
716 (rid == 0xEF) || \
717 (rid == 0xFF))))
718
719#define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \
720 ((rid == 0xE2)))
721
722/* polaris12 kickers */
723#define ASICID_IS_P23(did, rid) (((did == 0x6987) && \
724 ((rid == 0xC0) || \
725 (rid == 0xC1) || \
726 (rid == 0xC3) || \
727 (rid == 0xC7))) || \
728 ((did == 0x6981) && \
729 ((rid == 0x00) || \
730 (rid == 0x01) || \
731 (rid == 0x10))))
732
733struct amdgpu_mqd_prop {
734 uint64_t mqd_gpu_addr;
735 uint64_t hqd_base_gpu_addr;
736 uint64_t rptr_gpu_addr;
737 uint64_t wptr_gpu_addr;
738 uint32_t queue_size;
739 bool use_doorbell;
740 uint32_t doorbell_index;
741 uint64_t eop_gpu_addr;
742 uint32_t hqd_pipe_priority;
743 uint32_t hqd_queue_priority;
744 bool hqd_active;
745};
746
747struct amdgpu_mqd {
748 unsigned mqd_size;
749 int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
750 struct amdgpu_mqd_prop *p);
751};
752
753#define AMDGPU_RESET_MAGIC_NUM 64
754#define AMDGPU_MAX_DF_PERFMONS 4
755#define AMDGPU_PRODUCT_NAME_LEN 64
756struct amdgpu_reset_domain;
757
758struct amdgpu_device {
759 struct device *dev;
760 struct pci_dev *pdev;
761 struct drm_device ddev;
762
763#ifdef CONFIG_DRM_AMD_ACP
764 struct amdgpu_acp acp;
765#endif
766 struct amdgpu_hive_info *hive;
767 /* ASIC */
768 enum amd_asic_type asic_type;
769 uint32_t family;
770 uint32_t rev_id;
771 uint32_t external_rev_id;
772 unsigned long flags;
773 unsigned long apu_flags;
774 int usec_timeout;
775 const struct amdgpu_asic_funcs *asic_funcs;
776 bool shutdown;
777 bool need_swiotlb;
778 bool accel_working;
779 struct notifier_block acpi_nb;
780 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
781 struct debugfs_blob_wrapper debugfs_vbios_blob;
782 struct debugfs_blob_wrapper debugfs_discovery_blob;
783 struct mutex srbm_mutex;
784 /* GRBM index mutex. Protects concurrent access to GRBM index */
785 struct mutex grbm_idx_mutex;
786 struct dev_pm_domain vga_pm_domain;
787 bool have_disp_power_ref;
788 bool have_atomics_support;
789
790 /* BIOS */
791 bool is_atom_fw;
792 uint8_t *bios;
793 uint32_t bios_size;
794 uint32_t bios_scratch_reg_offset;
795 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
796
797 /* Register/doorbell mmio */
798 resource_size_t rmmio_base;
799 resource_size_t rmmio_size;
800 void __iomem *rmmio;
801 /* protects concurrent MM_INDEX/DATA based register access */
802 spinlock_t mmio_idx_lock;
803 struct amdgpu_mmio_remap rmmio_remap;
804 /* protects concurrent SMC based register access */
805 spinlock_t smc_idx_lock;
806 amdgpu_rreg_t smc_rreg;
807 amdgpu_wreg_t smc_wreg;
808 /* protects concurrent PCIE register access */
809 spinlock_t pcie_idx_lock;
810 amdgpu_rreg_t pcie_rreg;
811 amdgpu_wreg_t pcie_wreg;
812 amdgpu_rreg_t pciep_rreg;
813 amdgpu_wreg_t pciep_wreg;
814 amdgpu_rreg64_t pcie_rreg64;
815 amdgpu_wreg64_t pcie_wreg64;
816 /* protects concurrent UVD register access */
817 spinlock_t uvd_ctx_idx_lock;
818 amdgpu_rreg_t uvd_ctx_rreg;
819 amdgpu_wreg_t uvd_ctx_wreg;
820 /* protects concurrent DIDT register access */
821 spinlock_t didt_idx_lock;
822 amdgpu_rreg_t didt_rreg;
823 amdgpu_wreg_t didt_wreg;
824 /* protects concurrent gc_cac register access */
825 spinlock_t gc_cac_idx_lock;
826 amdgpu_rreg_t gc_cac_rreg;
827 amdgpu_wreg_t gc_cac_wreg;
828 /* protects concurrent se_cac register access */
829 spinlock_t se_cac_idx_lock;
830 amdgpu_rreg_t se_cac_rreg;
831 amdgpu_wreg_t se_cac_wreg;
832 /* protects concurrent ENDPOINT (audio) register access */
833 spinlock_t audio_endpt_idx_lock;
834 amdgpu_block_rreg_t audio_endpt_rreg;
835 amdgpu_block_wreg_t audio_endpt_wreg;
836 struct amdgpu_doorbell doorbell;
837
838 /* clock/pll info */
839 struct amdgpu_clock clock;
840
841 /* MC */
842 struct amdgpu_gmc gmc;
843 struct amdgpu_gart gart;
844 dma_addr_t dummy_page_addr;
845 struct amdgpu_vm_manager vm_manager;
846 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
847 unsigned num_vmhubs;
848
849 /* memory management */
850 struct amdgpu_mman mman;
851 struct amdgpu_vram_scratch vram_scratch;
852 struct amdgpu_wb wb;
853 atomic64_t num_bytes_moved;
854 atomic64_t num_evictions;
855 atomic64_t num_vram_cpu_page_faults;
856 atomic_t gpu_reset_counter;
857 atomic_t vram_lost_counter;
858
859 /* data for buffer migration throttling */
860 struct {
861 spinlock_t lock;
862 s64 last_update_us;
863 s64 accum_us; /* accumulated microseconds */
864 s64 accum_us_vis; /* for visible VRAM */
865 u32 log2_max_MBps;
866 } mm_stats;
867
868 /* display */
869 bool enable_virtual_display;
870 struct amdgpu_vkms_output *amdgpu_vkms_output;
871 struct amdgpu_mode_info mode_info;
872 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
873 struct work_struct hotplug_work;
874 struct amdgpu_irq_src crtc_irq;
875 struct amdgpu_irq_src vline0_irq;
876 struct amdgpu_irq_src vupdate_irq;
877 struct amdgpu_irq_src pageflip_irq;
878 struct amdgpu_irq_src hpd_irq;
879 struct amdgpu_irq_src dmub_trace_irq;
880 struct amdgpu_irq_src dmub_outbox_irq;
881
882 /* rings */
883 u64 fence_context;
884 unsigned num_rings;
885 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
886 struct dma_fence __rcu *gang_submit;
887 bool ib_pool_ready;
888 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
889 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
890
891 /* interrupts */
892 struct amdgpu_irq irq;
893
894 /* powerplay */
895 struct amd_powerplay powerplay;
896 struct amdgpu_pm pm;
897 u64 cg_flags;
898 u32 pg_flags;
899
900 /* nbio */
901 struct amdgpu_nbio nbio;
902
903 /* hdp */
904 struct amdgpu_hdp hdp;
905
906 /* smuio */
907 struct amdgpu_smuio smuio;
908
909 /* mmhub */
910 struct amdgpu_mmhub mmhub;
911
912 /* gfxhub */
913 struct amdgpu_gfxhub gfxhub;
914
915 /* gfx */
916 struct amdgpu_gfx gfx;
917
918 /* sdma */
919 struct amdgpu_sdma sdma;
920
921 /* lsdma */
922 struct amdgpu_lsdma lsdma;
923
924 /* uvd */
925 struct amdgpu_uvd uvd;
926
927 /* vce */
928 struct amdgpu_vce vce;
929
930 /* vcn */
931 struct amdgpu_vcn vcn;
932
933 /* jpeg */
934 struct amdgpu_jpeg jpeg;
935
936 /* firmwares */
937 struct amdgpu_firmware firmware;
938
939 /* PSP */
940 struct psp_context psp;
941
942 /* GDS */
943 struct amdgpu_gds gds;
944
945 /* KFD */
946 struct amdgpu_kfd_dev kfd;
947
948 /* UMC */
949 struct amdgpu_umc umc;
950
951 /* display related functionality */
952 struct amdgpu_display_manager dm;
953
954 /* mes */
955 bool enable_mes;
956 bool enable_mes_kiq;
957 struct amdgpu_mes mes;
958 struct amdgpu_mqd mqds[AMDGPU_HW_IP_NUM];
959
960 /* df */
961 struct amdgpu_df df;
962
963 /* MCA */
964 struct amdgpu_mca mca;
965
966 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
967 uint32_t harvest_ip_mask;
968 int num_ip_blocks;
969 struct mutex mn_lock;
970 DECLARE_HASHTABLE(mn_hash, 7);
971
972 /* tracking pinned memory */
973 atomic64_t vram_pin_size;
974 atomic64_t visible_pin_size;
975 atomic64_t gart_pin_size;
976
977 /* soc15 register offset based on ip, instance and segment */
978 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
979
980 /* delayed work_func for deferring clockgating during resume */
981 struct delayed_work delayed_init_work;
982
983 struct amdgpu_virt virt;
984
985 /* link all shadow bo */
986 struct list_head shadow_list;
987 struct mutex shadow_list_lock;
988
989 /* record hw reset is performed */
990 bool has_hw_reset;
991 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
992
993 /* s3/s4 mask */
994 bool in_suspend;
995 bool in_s3;
996 bool in_s4;
997 bool in_s0ix;
998
999 enum pp_mp1_state mp1_state;
1000 struct amdgpu_doorbell_index doorbell_index;
1001
1002 struct mutex notifier_lock;
1003
1004 int asic_reset_res;
1005 struct work_struct xgmi_reset_work;
1006 struct list_head reset_list;
1007
1008 long gfx_timeout;
1009 long sdma_timeout;
1010 long video_timeout;
1011 long compute_timeout;
1012
1013 uint64_t unique_id;
1014 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
1015
1016 /* enable runtime pm on the device */
1017 bool in_runpm;
1018 bool has_pr3;
1019
1020 bool pm_sysfs_en;
1021 bool ucode_sysfs_en;
1022 bool psp_sysfs_en;
1023
1024 /* Chip product information */
1025 char product_number[20];
1026 char product_name[AMDGPU_PRODUCT_NAME_LEN];
1027 char serial[20];
1028
1029 atomic_t throttling_logging_enabled;
1030 struct ratelimit_state throttling_logging_rs;
1031 uint32_t ras_hw_enabled;
1032 uint32_t ras_enabled;
1033
1034 bool no_hw_access;
1035 struct pci_saved_state *pci_state;
1036 pci_channel_state_t pci_channel_state;
1037
1038 struct amdgpu_reset_control *reset_cntl;
1039 uint32_t ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
1040
1041 bool ram_is_direct_mapped;
1042
1043 struct list_head ras_list;
1044
1045 struct ip_discovery_top *ip_top;
1046
1047 struct amdgpu_reset_domain *reset_domain;
1048
1049 struct mutex benchmark_mutex;
1050
1051 /* reset dump register */
1052 uint32_t *reset_dump_reg_list;
1053 uint32_t *reset_dump_reg_value;
1054 int num_regs;
1055#ifdef CONFIG_DEV_COREDUMP
1056 struct amdgpu_task_info reset_task_info;
1057 bool reset_vram_lost;
1058 struct timespec64 reset_time;
1059#endif
1060
1061 bool scpm_enabled;
1062 uint32_t scpm_status;
1063
1064 struct work_struct reset_work;
1065
1066 bool job_hang;
1067 bool dc_enabled;
1068};
1069
1070static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
1071{
1072 return container_of(ddev, struct amdgpu_device, ddev);
1073}
1074
1075static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev)
1076{
1077 return &adev->ddev;
1078}
1079
1080static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev)
1081{
1082 return container_of(bdev, struct amdgpu_device, mman.bdev);
1083}
1084
1085int amdgpu_device_init(struct amdgpu_device *adev,
1086 uint32_t flags);
1087void amdgpu_device_fini_hw(struct amdgpu_device *adev);
1088void amdgpu_device_fini_sw(struct amdgpu_device *adev);
1089
1090int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1091
1092void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos,
1093 void *buf, size_t size, bool write);
1094size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos,
1095 void *buf, size_t size, bool write);
1096
1097void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
1098 void *buf, size_t size, bool write);
1099uint32_t amdgpu_device_rreg(struct amdgpu_device *adev,
1100 uint32_t reg, uint32_t acc_flags);
1101void amdgpu_device_wreg(struct amdgpu_device *adev,
1102 uint32_t reg, uint32_t v,
1103 uint32_t acc_flags);
1104void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
1105 uint32_t reg, uint32_t v);
1106void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);
1107uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
1108
1109u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,
1110 u32 pcie_index, u32 pcie_data,
1111 u32 reg_addr);
1112u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev,
1113 u32 pcie_index, u32 pcie_data,
1114 u32 reg_addr);
1115void amdgpu_device_indirect_wreg(struct amdgpu_device *adev,
1116 u32 pcie_index, u32 pcie_data,
1117 u32 reg_addr, u32 reg_data);
1118void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev,
1119 u32 pcie_index, u32 pcie_data,
1120 u32 reg_addr, u64 reg_data);
1121
1122bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
1123bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
1124
1125void amdgpu_device_set_sriov_virtual_display(struct amdgpu_device *adev);
1126
1127int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
1128 struct amdgpu_reset_context *reset_context);
1129
1130int amdgpu_do_asic_reset(struct list_head *device_list_handle,
1131 struct amdgpu_reset_context *reset_context);
1132
1133int emu_soc_asic_init(struct amdgpu_device *adev);
1134
1135/*
1136 * Registers read & write functions.
1137 */
1138#define AMDGPU_REGS_NO_KIQ (1<<1)
1139#define AMDGPU_REGS_RLC (1<<2)
1140
1141#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1142#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1143
1144#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1145#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1146
1147#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1148#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1149
1150#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1151#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1152#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1153#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1154#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1155#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1156#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1157#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1158#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1159#define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1160#define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1161#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1162#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1163#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1164#define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1165#define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1166#define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1167#define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1168#define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1169#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1170#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1171#define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1172#define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1173#define WREG32_P(reg, val, mask) \
1174 do { \
1175 uint32_t tmp_ = RREG32(reg); \
1176 tmp_ &= (mask); \
1177 tmp_ |= ((val) & ~(mask)); \
1178 WREG32(reg, tmp_); \
1179 } while (0)
1180#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1181#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1182#define WREG32_PLL_P(reg, val, mask) \
1183 do { \
1184 uint32_t tmp_ = RREG32_PLL(reg); \
1185 tmp_ &= (mask); \
1186 tmp_ |= ((val) & ~(mask)); \
1187 WREG32_PLL(reg, tmp_); \
1188 } while (0)
1189
1190#define WREG32_SMC_P(_Reg, _Val, _Mask) \
1191 do { \
1192 u32 tmp = RREG32_SMC(_Reg); \
1193 tmp &= (_Mask); \
1194 tmp |= ((_Val) & ~(_Mask)); \
1195 WREG32_SMC(_Reg, tmp); \
1196 } while (0)
1197
1198#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1199
1200#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1201#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1202
1203#define REG_SET_FIELD(orig_val, reg, field, field_val) \
1204 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1205 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1206
1207#define REG_GET_FIELD(value, reg, field) \
1208 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1209
1210#define WREG32_FIELD(reg, field, val) \
1211 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1212
1213#define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1214 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1215
1216/*
1217 * BIOS helpers.
1218 */
1219#define RBIOS8(i) (adev->bios[i])
1220#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1221#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1222
1223/*
1224 * ASICs macro.
1225 */
1226#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1227#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1228#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
1229#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1230#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1231#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1232#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1233#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1234#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1235#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1236#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1237#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1238#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1239#define amdgpu_asic_flush_hdp(adev, r) \
1240 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
1241#define amdgpu_asic_invalidate_hdp(adev, r) \
1242 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
1243 ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
1244#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
1245#define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
1246#define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))
1247#define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev))
1248#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
1249#define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev))
1250#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
1251#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
1252 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
1253#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
1254
1255#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
1256
1257#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
1258
1259/* Common functions */
1260bool amdgpu_device_has_job_running(struct amdgpu_device *adev);
1261bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev);
1262int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
1263 struct amdgpu_job *job,
1264 struct amdgpu_reset_context *reset_context);
1265void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
1266int amdgpu_device_pci_reset(struct amdgpu_device *adev);
1267bool amdgpu_device_need_post(struct amdgpu_device *adev);
1268bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
1269
1270void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1271 u64 num_vis_bytes);
1272int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
1273void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
1274 const u32 *registers,
1275 const u32 array_size);
1276
1277int amdgpu_device_mode1_reset(struct amdgpu_device *adev);
1278bool amdgpu_device_supports_atpx(struct drm_device *dev);
1279bool amdgpu_device_supports_px(struct drm_device *dev);
1280bool amdgpu_device_supports_boco(struct drm_device *dev);
1281bool amdgpu_device_supports_smart_shift(struct drm_device *dev);
1282bool amdgpu_device_supports_baco(struct drm_device *dev);
1283bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
1284 struct amdgpu_device *peer_adev);
1285int amdgpu_device_baco_enter(struct drm_device *dev);
1286int amdgpu_device_baco_exit(struct drm_device *dev);
1287
1288void amdgpu_device_flush_hdp(struct amdgpu_device *adev,
1289 struct amdgpu_ring *ring);
1290void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev,
1291 struct amdgpu_ring *ring);
1292
1293void amdgpu_device_halt(struct amdgpu_device *adev);
1294u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev,
1295 u32 reg);
1296void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
1297 u32 reg, u32 v);
1298struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
1299 struct dma_fence *gang);
1300bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
1301
1302/* atpx handler */
1303#if defined(CONFIG_VGA_SWITCHEROO)
1304void amdgpu_register_atpx_handler(void);
1305void amdgpu_unregister_atpx_handler(void);
1306bool amdgpu_has_atpx_dgpu_power_cntl(void);
1307bool amdgpu_is_atpx_hybrid(void);
1308bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1309bool amdgpu_has_atpx(void);
1310#else
1311static inline void amdgpu_register_atpx_handler(void) {}
1312static inline void amdgpu_unregister_atpx_handler(void) {}
1313static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1314static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1315static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1316static inline bool amdgpu_has_atpx(void) { return false; }
1317#endif
1318
1319#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI)
1320void *amdgpu_atpx_get_dhandle(void);
1321#else
1322static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; }
1323#endif
1324
1325/*
1326 * KMS
1327 */
1328extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1329extern const int amdgpu_max_kms_ioctl;
1330
1331int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags);
1332void amdgpu_driver_unload_kms(struct drm_device *dev);
1333void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1334int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1335void amdgpu_driver_postclose_kms(struct drm_device *dev,
1336 struct drm_file *file_priv);
1337void amdgpu_driver_release_kms(struct drm_device *dev);
1338
1339int amdgpu_device_ip_suspend(struct amdgpu_device *adev);
1340int amdgpu_device_suspend(struct drm_device *dev, bool fbcon);
1341int amdgpu_device_resume(struct drm_device *dev, bool fbcon);
1342u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc);
1343int amdgpu_enable_vblank_kms(struct drm_crtc *crtc);
1344void amdgpu_disable_vblank_kms(struct drm_crtc *crtc);
1345int amdgpu_info_ioctl(struct drm_device *dev, void *data,
1346 struct drm_file *filp);
1347
1348/*
1349 * functions used by amdgpu_encoder.c
1350 */
1351struct amdgpu_afmt_acr {
1352 u32 clock;
1353
1354 int n_32khz;
1355 int cts_32khz;
1356
1357 int n_44_1khz;
1358 int cts_44_1khz;
1359
1360 int n_48khz;
1361 int cts_48khz;
1362
1363};
1364
1365struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1366
1367/* amdgpu_acpi.c */
1368
1369/* ATCS Device/Driver State */
1370#define AMDGPU_ATCS_PSC_DEV_STATE_D0 0
1371#define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3
1372#define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0
1373#define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1
1374
1375#if defined(CONFIG_ACPI)
1376int amdgpu_acpi_init(struct amdgpu_device *adev);
1377void amdgpu_acpi_fini(struct amdgpu_device *adev);
1378bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1379bool amdgpu_acpi_is_power_shift_control_supported(void);
1380int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1381 u8 perf_req, bool advertise);
1382int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1383 u8 dev_state, bool drv_state);
1384int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state);
1385int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1386
1387void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps);
1388void amdgpu_acpi_detect(void);
1389#else
1390static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1391static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1392static inline void amdgpu_acpi_detect(void) { }
1393static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; }
1394static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev,
1395 u8 dev_state, bool drv_state) { return 0; }
1396static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev,
1397 enum amdgpu_ss ss_state) { return 0; }
1398#endif
1399
1400#if defined(CONFIG_ACPI) && defined(CONFIG_SUSPEND)
1401bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev);
1402bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev);
1403bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev);
1404#else
1405static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; }
1406static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; }
1407static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return false; }
1408#endif
1409
1410#if defined(CONFIG_DRM_AMD_DC)
1411int amdgpu_dm_display_resume(struct amdgpu_device *adev );
1412#else
1413static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; }
1414#endif
1415
1416
1417void amdgpu_register_gpu_instance(struct amdgpu_device *adev);
1418void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev);
1419
1420pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev,
1421 pci_channel_state_t state);
1422pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev);
1423pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev);
1424void amdgpu_pci_resume(struct pci_dev *pdev);
1425
1426bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);
1427bool amdgpu_device_load_pci_state(struct pci_dev *pdev);
1428
1429bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);
1430
1431int amdgpu_device_set_cg_state(struct amdgpu_device *adev,
1432 enum amd_clockgating_state state);
1433int amdgpu_device_set_pg_state(struct amdgpu_device *adev,
1434 enum amd_powergating_state state);
1435
1436static inline bool amdgpu_device_has_timeouts_enabled(struct amdgpu_device *adev)
1437{
1438 return amdgpu_gpu_recovery != 0 &&
1439 adev->gfx_timeout != MAX_SCHEDULE_TIMEOUT &&
1440 adev->compute_timeout != MAX_SCHEDULE_TIMEOUT &&
1441 adev->sdma_timeout != MAX_SCHEDULE_TIMEOUT &&
1442 adev->video_timeout != MAX_SCHEDULE_TIMEOUT;
1443}
1444
1445#include "amdgpu_object.h"
1446
1447static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)
1448{
1449 return adev->gmc.tmz_enabled;
1450}
1451
1452int amdgpu_in_reset(struct amdgpu_device *adev);
1453
1454#endif