Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * CS42L43 core driver
4 *
5 * Copyright (C) 2022-2023 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8
9#include <linux/array_size.h>
10#include <linux/bitops.h>
11#include <linux/build_bug.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/err.h>
15#include <linux/firmware.h>
16#include <linux/gpio/consumer.h>
17#include <linux/jiffies.h>
18#include <linux/mfd/core.h>
19#include <linux/mfd/cs42l43.h>
20#include <linux/mfd/cs42l43-regs.h>
21#include <linux/module.h>
22#include <linux/pm.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
25#include <linux/soundwire/sdw.h>
26#include <linux/types.h>
27
28#include "cs42l43.h"
29
30#define CS42L43_RESET_DELAY_MS 20
31
32#define CS42L43_SDW_ATTACH_TIMEOUT_MS 5000
33#define CS42L43_SDW_DETACH_TIMEOUT_MS 100
34
35#define CS42L43_MCU_BOOT_STAGE1 1
36#define CS42L43_MCU_BOOT_STAGE2 2
37#define CS42L43_MCU_BOOT_STAGE3 3
38#define CS42L43_MCU_BOOT_STAGE4 4
39#define CS42L43_MCU_POLL_US 5000
40#define CS42L43_MCU_CMD_TIMEOUT_US 20000
41#define CS42L43_MCU_UPDATE_FORMAT 3
42#define CS42L43_MCU_UPDATE_OFFSET 0x100000
43#define CS42L43_MCU_UPDATE_TIMEOUT_US 500000
44#define CS42L43_MCU_UPDATE_RETRIES 5
45
46#define CS42L43_MCU_ROM_REV 0x2001
47#define CS42L43_MCU_ROM_BIOS_REV 0x0000
48
49#define CS42L43_MCU_SUPPORTED_REV 0x2105
50#define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200
51#define CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV 0x1002
52#define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001
53
54#define CS42L43_VDDP_DELAY_US 50
55#define CS42L43_VDDD_DELAY_US 1000
56
57#define CS42L43_AUTOSUSPEND_TIME_MS 250
58
59struct cs42l43_patch_header {
60 __le16 version;
61 __le16 size;
62 __u8 reserved;
63 __u8 secure;
64 __le16 bss_size;
65 __le32 apply_addr;
66 __le32 checksum;
67 __le32 sha;
68 __le16 swrev;
69 __le16 patchid;
70 __le16 ipxid;
71 __le16 romver;
72 __le32 load_addr;
73} __packed;
74
75static const struct reg_sequence cs42l43_reva_patch[] = {
76 { 0x4000, 0x00000055 },
77 { 0x4000, 0x000000AA },
78 { 0x10084, 0x00000000 },
79 { 0x1741C, 0x00CD2000 },
80 { 0x1718C, 0x00000003 },
81 { 0x4000, 0x00000000 },
82 { CS42L43_CCM_BLK_CLK_CONTROL, 0x00000002 },
83 { CS42L43_HPPATHVOL, 0x011B011B },
84 { CS42L43_OSC_DIV_SEL, 0x00000001 },
85 { CS42L43_DACCNFG2, 0x00000005 },
86 { CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
87 { CS42L43_RELID, 0x0000000F },
88};
89
90const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = {
91 { CS42L43_DRV_CTRL1, 0x000186C0 },
92 { CS42L43_DRV_CTRL3, 0x286DB018 },
93 { CS42L43_DRV_CTRL4, 0x000006D8 },
94 { CS42L43_DRV_CTRL_5, 0x136C00C0 },
95 { CS42L43_GPIO_CTRL1, 0x00000707 },
96 { CS42L43_GPIO_CTRL2, 0x00000000 },
97 { CS42L43_GPIO_FN_SEL, 0x00000004 },
98 { CS42L43_MCLK_SRC_SEL, 0x00000000 },
99 { CS42L43_SAMPLE_RATE1, 0x00000003 },
100 { CS42L43_SAMPLE_RATE2, 0x00000003 },
101 { CS42L43_SAMPLE_RATE3, 0x00000003 },
102 { CS42L43_SAMPLE_RATE4, 0x00000003 },
103 { CS42L43_PLL_CONTROL, 0x00000000 },
104 { CS42L43_FS_SELECT1, 0x00000000 },
105 { CS42L43_FS_SELECT2, 0x00000000 },
106 { CS42L43_FS_SELECT3, 0x00000000 },
107 { CS42L43_FS_SELECT4, 0x00000000 },
108 { CS42L43_PDM_CONTROL, 0x00000000 },
109 { CS42L43_ASP_CLK_CONFIG1, 0x00010001 },
110 { CS42L43_ASP_CLK_CONFIG2, 0x00000000 },
111 { CS42L43_OSC_DIV_SEL, 0x00000001 },
112 { CS42L43_ADC_B_CTRL1, 0x00000000 },
113 { CS42L43_ADC_B_CTRL2, 0x00000000 },
114 { CS42L43_DECIM_HPF_WNF_CTRL1, 0x00000001 },
115 { CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 },
116 { CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 },
117 { CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 },
118 { CS42L43_DMIC_PDM_CTRL, 0x00000000 },
119 { CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 },
120 { CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 },
121 { CS42L43_INTP_VOLUME_CTRL1, 0x00000180 },
122 { CS42L43_INTP_VOLUME_CTRL2, 0x00000180 },
123 { CS42L43_AMP1_2_VOL_RAMP, 0x00000022 },
124 { CS42L43_ASP_CTRL, 0x00000004 },
125 { CS42L43_ASP_FSYNC_CTRL1, 0x000000FA },
126 { CS42L43_ASP_FSYNC_CTRL2, 0x00000001 },
127 { CS42L43_ASP_FSYNC_CTRL3, 0x00000000 },
128 { CS42L43_ASP_FSYNC_CTRL4, 0x000001F4 },
129 { CS42L43_ASP_DATA_CTRL, 0x0000003A },
130 { CS42L43_ASP_RX_EN, 0x00000000 },
131 { CS42L43_ASP_TX_EN, 0x00000000 },
132 { CS42L43_ASP_RX_CH1_CTRL, 0x00170001 },
133 { CS42L43_ASP_RX_CH2_CTRL, 0x00170031 },
134 { CS42L43_ASP_RX_CH3_CTRL, 0x00170061 },
135 { CS42L43_ASP_RX_CH4_CTRL, 0x00170091 },
136 { CS42L43_ASP_RX_CH5_CTRL, 0x001700C1 },
137 { CS42L43_ASP_RX_CH6_CTRL, 0x001700F1 },
138 { CS42L43_ASP_TX_CH1_CTRL, 0x00170001 },
139 { CS42L43_ASP_TX_CH2_CTRL, 0x00170031 },
140 { CS42L43_ASP_TX_CH3_CTRL, 0x00170061 },
141 { CS42L43_ASP_TX_CH4_CTRL, 0x00170091 },
142 { CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 },
143 { CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 },
144 { CS42L43_ASPTX1_INPUT, 0x00000000 },
145 { CS42L43_ASPTX2_INPUT, 0x00000000 },
146 { CS42L43_ASPTX3_INPUT, 0x00000000 },
147 { CS42L43_ASPTX4_INPUT, 0x00000000 },
148 { CS42L43_ASPTX5_INPUT, 0x00000000 },
149 { CS42L43_ASPTX6_INPUT, 0x00000000 },
150 { CS42L43_SWIRE_DP1_CH1_INPUT, 0x00000000 },
151 { CS42L43_SWIRE_DP1_CH2_INPUT, 0x00000000 },
152 { CS42L43_SWIRE_DP1_CH3_INPUT, 0x00000000 },
153 { CS42L43_SWIRE_DP1_CH4_INPUT, 0x00000000 },
154 { CS42L43_SWIRE_DP2_CH1_INPUT, 0x00000000 },
155 { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 },
156 { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 },
157 { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 },
158 { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 },
159 { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 },
160 { CS42L43_ASRC_INT1_INPUT1, 0x00000000 },
161 { CS42L43_ASRC_INT2_INPUT1, 0x00000000 },
162 { CS42L43_ASRC_INT3_INPUT1, 0x00000000 },
163 { CS42L43_ASRC_INT4_INPUT1, 0x00000000 },
164 { CS42L43_ASRC_DEC1_INPUT1, 0x00000000 },
165 { CS42L43_ASRC_DEC2_INPUT1, 0x00000000 },
166 { CS42L43_ASRC_DEC3_INPUT1, 0x00000000 },
167 { CS42L43_ASRC_DEC4_INPUT1, 0x00000000 },
168 { CS42L43_ISRC1INT1_INPUT1, 0x00000000 },
169 { CS42L43_ISRC1INT2_INPUT1, 0x00000000 },
170 { CS42L43_ISRC1DEC1_INPUT1, 0x00000000 },
171 { CS42L43_ISRC1DEC2_INPUT1, 0x00000000 },
172 { CS42L43_ISRC2INT1_INPUT1, 0x00000000 },
173 { CS42L43_ISRC2INT2_INPUT1, 0x00000000 },
174 { CS42L43_ISRC2DEC1_INPUT1, 0x00000000 },
175 { CS42L43_ISRC2DEC2_INPUT1, 0x00000000 },
176 { CS42L43_EQ1MIX_INPUT1, 0x00800000 },
177 { CS42L43_EQ1MIX_INPUT2, 0x00800000 },
178 { CS42L43_EQ1MIX_INPUT3, 0x00800000 },
179 { CS42L43_EQ1MIX_INPUT4, 0x00800000 },
180 { CS42L43_EQ2MIX_INPUT1, 0x00800000 },
181 { CS42L43_EQ2MIX_INPUT2, 0x00800000 },
182 { CS42L43_EQ2MIX_INPUT3, 0x00800000 },
183 { CS42L43_EQ2MIX_INPUT4, 0x00800000 },
184 { CS42L43_SPDIF1_INPUT1, 0x00000000 },
185 { CS42L43_SPDIF2_INPUT1, 0x00000000 },
186 { CS42L43_AMP1MIX_INPUT1, 0x00800000 },
187 { CS42L43_AMP1MIX_INPUT2, 0x00800000 },
188 { CS42L43_AMP1MIX_INPUT3, 0x00800000 },
189 { CS42L43_AMP1MIX_INPUT4, 0x00800000 },
190 { CS42L43_AMP2MIX_INPUT1, 0x00800000 },
191 { CS42L43_AMP2MIX_INPUT2, 0x00800000 },
192 { CS42L43_AMP2MIX_INPUT3, 0x00800000 },
193 { CS42L43_AMP2MIX_INPUT4, 0x00800000 },
194 { CS42L43_AMP3MIX_INPUT1, 0x00800000 },
195 { CS42L43_AMP3MIX_INPUT2, 0x00800000 },
196 { CS42L43_AMP3MIX_INPUT3, 0x00800000 },
197 { CS42L43_AMP3MIX_INPUT4, 0x00800000 },
198 { CS42L43_AMP4MIX_INPUT1, 0x00800000 },
199 { CS42L43_AMP4MIX_INPUT2, 0x00800000 },
200 { CS42L43_AMP4MIX_INPUT3, 0x00800000 },
201 { CS42L43_AMP4MIX_INPUT4, 0x00800000 },
202 { CS42L43_ASRC_INT_ENABLES, 0x00000100 },
203 { CS42L43_ASRC_DEC_ENABLES, 0x00000100 },
204 { CS42L43_PDNCNTL, 0x00000000 },
205 { CS42L43_RINGSENSE_DEB_CTRL, 0x0000001B },
206 { CS42L43_TIPSENSE_DEB_CTRL, 0x0000001B },
207 { CS42L43_HS2, 0x050106F3 },
208 { CS42L43_STEREO_MIC_CTRL, 0x00000000 },
209 { CS42L43_STEREO_MIC_CLAMP_CTRL, 0x00000001 },
210 { CS42L43_BLOCK_EN2, 0x00000000 },
211 { CS42L43_BLOCK_EN3, 0x00000000 },
212 { CS42L43_BLOCK_EN4, 0x00000000 },
213 { CS42L43_BLOCK_EN5, 0x00000000 },
214 { CS42L43_BLOCK_EN6, 0x00000000 },
215 { CS42L43_BLOCK_EN7, 0x00000000 },
216 { CS42L43_BLOCK_EN8, 0x00000000 },
217 { CS42L43_BLOCK_EN9, 0x00000000 },
218 { CS42L43_BLOCK_EN10, 0x00000000 },
219 { CS42L43_BLOCK_EN11, 0x00000000 },
220 { CS42L43_TONE_CH1_CTRL, 0x00000000 },
221 { CS42L43_TONE_CH2_CTRL, 0x00000000 },
222 { CS42L43_MIC_DETECT_CONTROL_1, 0x00000003 },
223 { CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL, 0x02000003 },
224 { CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 },
225 { CS42L43_ISRC1_CTRL, 0x00000000 },
226 { CS42L43_ISRC2_CTRL, 0x00000000 },
227 { CS42L43_CTRL_REG, 0x00000006 },
228 { CS42L43_FDIV_FRAC, 0x40000000 },
229 { CS42L43_CAL_RATIO, 0x00000080 },
230 { CS42L43_SPI_CLK_CONFIG1, 0x00000001 },
231 { CS42L43_SPI_CONFIG1, 0x00000000 },
232 { CS42L43_SPI_CONFIG2, 0x00000000 },
233 { CS42L43_SPI_CONFIG3, 0x00000001 },
234 { CS42L43_SPI_CONFIG4, 0x00000000 },
235 { CS42L43_TRAN_CONFIG3, 0x00000000 },
236 { CS42L43_TRAN_CONFIG4, 0x00000000 },
237 { CS42L43_TRAN_CONFIG5, 0x00000000 },
238 { CS42L43_TRAN_CONFIG6, 0x00000000 },
239 { CS42L43_TRAN_CONFIG7, 0x00000000 },
240 { CS42L43_TRAN_CONFIG8, 0x00000000 },
241 { CS42L43_DACCNFG1, 0x00000008 },
242 { CS42L43_DACCNFG2, 0x00000005 },
243 { CS42L43_HPPATHVOL, 0x011B011B },
244 { CS42L43_PGAVOL, 0x00003470 },
245 { CS42L43_LOADDETENA, 0x00000000 },
246 { CS42L43_CTRL, 0x00000037 },
247 { CS42L43_COEFF_DATA_IN0, 0x00000000 },
248 { CS42L43_COEFF_RD_WR0, 0x00000000 },
249 { CS42L43_START_EQZ0, 0x00000000 },
250 { CS42L43_MUTE_EQ_IN0, 0x00000000 },
251 { CS42L43_DECIM_MASK, 0x0000000F },
252 { CS42L43_EQ_MIX_MASK, 0x0000000F },
253 { CS42L43_ASP_MASK, 0x000000FF },
254 { CS42L43_PLL_MASK, 0x00000003 },
255 { CS42L43_SOFT_MASK, 0x0000FFFF },
256 { CS42L43_SWIRE_MASK, 0x00007FFF },
257 { CS42L43_MSM_MASK, 0x00000FFF },
258 { CS42L43_ACC_DET_MASK, 0x00000FFF },
259 { CS42L43_I2C_TGT_MASK, 0x00000003 },
260 { CS42L43_SPI_MSTR_MASK, 0x00000007 },
261 { CS42L43_SW_TO_SPI_BRIDGE_MASK, 0x00000001 },
262 { CS42L43_OTP_MASK, 0x00000007 },
263 { CS42L43_CLASS_D_AMP_MASK, 0x00003FFF },
264 { CS42L43_GPIO_INT_MASK, 0x0000003F },
265 { CS42L43_ASRC_MASK, 0x0000000F },
266 { CS42L43_HPOUT_MASK, 0x00000003 },
267};
268EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, "MFD_CS42L43");
269
270bool cs42l43_readable_register(struct device *dev, unsigned int reg)
271{
272 switch (reg) {
273 case CS42L43_DEVID:
274 case CS42L43_REVID:
275 case CS42L43_RELID:
276 case CS42L43_SFT_RESET:
277 case CS42L43_DRV_CTRL1:
278 case CS42L43_DRV_CTRL3:
279 case CS42L43_DRV_CTRL4:
280 case CS42L43_DRV_CTRL_5:
281 case CS42L43_GPIO_CTRL1:
282 case CS42L43_GPIO_CTRL2:
283 case CS42L43_GPIO_STS:
284 case CS42L43_GPIO_FN_SEL:
285 case CS42L43_MCLK_SRC_SEL:
286 case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4:
287 case CS42L43_PLL_CONTROL:
288 case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4:
289 case CS42L43_PDM_CONTROL:
290 case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2:
291 case CS42L43_OSC_DIV_SEL:
292 case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2:
293 case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4:
294 case CS42L43_DMIC_PDM_CTRL:
295 case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4:
296 case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2:
297 case CS42L43_AMP1_2_VOL_RAMP:
298 case CS42L43_ASP_CTRL:
299 case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4:
300 case CS42L43_ASP_DATA_CTRL:
301 case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN:
302 case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL:
303 case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL:
304 case CS42L43_OTP_REVISION_ID:
305 case CS42L43_ASPTX1_INPUT:
306 case CS42L43_ASPTX2_INPUT:
307 case CS42L43_ASPTX3_INPUT:
308 case CS42L43_ASPTX4_INPUT:
309 case CS42L43_ASPTX5_INPUT:
310 case CS42L43_ASPTX6_INPUT:
311 case CS42L43_SWIRE_DP1_CH1_INPUT:
312 case CS42L43_SWIRE_DP1_CH2_INPUT:
313 case CS42L43_SWIRE_DP1_CH3_INPUT:
314 case CS42L43_SWIRE_DP1_CH4_INPUT:
315 case CS42L43_SWIRE_DP2_CH1_INPUT:
316 case CS42L43_SWIRE_DP2_CH2_INPUT:
317 case CS42L43_SWIRE_DP3_CH1_INPUT:
318 case CS42L43_SWIRE_DP3_CH2_INPUT:
319 case CS42L43_SWIRE_DP4_CH1_INPUT:
320 case CS42L43_SWIRE_DP4_CH2_INPUT:
321 case CS42L43_ASRC_INT1_INPUT1:
322 case CS42L43_ASRC_INT2_INPUT1:
323 case CS42L43_ASRC_INT3_INPUT1:
324 case CS42L43_ASRC_INT4_INPUT1:
325 case CS42L43_ASRC_DEC1_INPUT1:
326 case CS42L43_ASRC_DEC2_INPUT1:
327 case CS42L43_ASRC_DEC3_INPUT1:
328 case CS42L43_ASRC_DEC4_INPUT1:
329 case CS42L43_ISRC1INT1_INPUT1:
330 case CS42L43_ISRC1INT2_INPUT1:
331 case CS42L43_ISRC1DEC1_INPUT1:
332 case CS42L43_ISRC1DEC2_INPUT1:
333 case CS42L43_ISRC2INT1_INPUT1:
334 case CS42L43_ISRC2INT2_INPUT1:
335 case CS42L43_ISRC2DEC1_INPUT1:
336 case CS42L43_ISRC2DEC2_INPUT1:
337 case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4:
338 case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4:
339 case CS42L43_SPDIF1_INPUT1:
340 case CS42L43_SPDIF2_INPUT1:
341 case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4:
342 case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4:
343 case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4:
344 case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4:
345 case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES:
346 case CS42L43_PDNCNTL:
347 case CS42L43_RINGSENSE_DEB_CTRL:
348 case CS42L43_TIPSENSE_DEB_CTRL:
349 case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
350 case CS42L43_HS2:
351 case CS42L43_HS_STAT:
352 case CS42L43_MCU_SW_INTERRUPT:
353 case CS42L43_STEREO_MIC_CTRL:
354 case CS42L43_STEREO_MIC_CLAMP_CTRL:
355 case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11:
356 case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL:
357 case CS42L43_MIC_DETECT_CONTROL_1:
358 case CS42L43_DETECT_STATUS_1:
359 case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL:
360 case CS42L43_MIC_DETECT_CONTROL_ANDROID:
361 case CS42L43_ISRC1_CTRL:
362 case CS42L43_ISRC2_CTRL:
363 case CS42L43_CTRL_REG:
364 case CS42L43_FDIV_FRAC:
365 case CS42L43_CAL_RATIO:
366 case CS42L43_SPI_CLK_CONFIG1:
367 case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4:
368 case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
369 case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8:
370 case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
371 case CS42L43_TX_DATA:
372 case CS42L43_RX_DATA:
373 case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2:
374 case CS42L43_HPPATHVOL:
375 case CS42L43_PGAVOL:
376 case CS42L43_LOADDETRESULTS:
377 case CS42L43_LOADDETENA:
378 case CS42L43_CTRL:
379 case CS42L43_COEFF_DATA_IN0:
380 case CS42L43_COEFF_RD_WR0:
381 case CS42L43_INIT_DONE0:
382 case CS42L43_START_EQZ0:
383 case CS42L43_MUTE_EQ_IN0:
384 case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
385 case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK:
386 case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
387 case CS42L43_BOOT_CONTROL:
388 case CS42L43_BLOCK_EN:
389 case CS42L43_SHUTTER_CONTROL:
390 case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
391 return true;
392 default:
393 return false;
394 }
395}
396EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, "MFD_CS42L43");
397
398bool cs42l43_precious_register(struct device *dev, unsigned int reg)
399{
400 switch (reg) {
401 case CS42L43_SFT_RESET:
402 case CS42L43_TX_DATA:
403 case CS42L43_RX_DATA:
404 case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT:
405 case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX:
406 return true;
407 default:
408 return false;
409 }
410}
411EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, "MFD_CS42L43");
412
413bool cs42l43_volatile_register(struct device *dev, unsigned int reg)
414{
415 switch (reg) {
416 case CS42L43_DEVID:
417 case CS42L43_REVID:
418 case CS42L43_RELID:
419 case CS42L43_GPIO_STS:
420 case CS42L43_OTP_REVISION_ID:
421 case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS:
422 case CS42L43_HS_STAT:
423 case CS42L43_MCU_SW_INTERRUPT:
424 case CS42L43_DETECT_STATUS_1:
425 case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2:
426 case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2:
427 case CS42L43_TRAN_CONFIG8:
428 case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3:
429 case CS42L43_LOADDETRESULTS:
430 case CS42L43_INIT_DONE0:
431 case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW:
432 case CS42L43_BOOT_CONTROL:
433 case CS42L43_BLOCK_EN:
434 return true;
435 default:
436 return cs42l43_precious_register(dev, reg);
437 }
438}
439EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, "MFD_CS42L43");
440
441#define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT)
442
443#define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \
444 CS42L43_IRQ_OFFSET(reg), \
445 CS42L43_##name##_INT_MASK)
446
447static const struct regmap_irq cs42l43_regmap_irqs[] = {
448 CS42L43_IRQ_REG(PLL_LOST_LOCK, PLL),
449 CS42L43_IRQ_REG(PLL_READY, PLL),
450
451 CS42L43_IRQ_REG(HP_STARTUP_DONE, MSM),
452 CS42L43_IRQ_REG(HP_SHUTDOWN_DONE, MSM),
453 CS42L43_IRQ_REG(HSDET_DONE, MSM),
454 CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB, MSM),
455 CS42L43_IRQ_REG(TIPSENSE_PLUG_DB, MSM),
456 CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB, MSM),
457 CS42L43_IRQ_REG(RINGSENSE_PLUG_DB, MSM),
458 CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET, MSM),
459 CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET, MSM),
460 CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET, MSM),
461 CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET, MSM),
462
463 CS42L43_IRQ_REG(HS2_BIAS_SENSE, ACC_DET),
464 CS42L43_IRQ_REG(HS1_BIAS_SENSE, ACC_DET),
465 CS42L43_IRQ_REG(DC_DETECT1_FALSE, ACC_DET),
466 CS42L43_IRQ_REG(DC_DETECT1_TRUE, ACC_DET),
467 CS42L43_IRQ_REG(HSBIAS_CLAMPED, ACC_DET),
468 CS42L43_IRQ_REG(HS3_4_BIAS_SENSE, ACC_DET),
469
470 CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT, CLASS_D_AMP),
471 CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT, CLASS_D_AMP),
472 CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT, CLASS_D_AMP),
473 CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT, CLASS_D_AMP),
474 CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE, CLASS_D_AMP),
475 CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE, CLASS_D_AMP),
476 CS42L43_IRQ_REG(AMP2_STARTUP_DONE, CLASS_D_AMP),
477 CS42L43_IRQ_REG(AMP1_STARTUP_DONE, CLASS_D_AMP),
478 CS42L43_IRQ_REG(AMP2_THERM_SHDN, CLASS_D_AMP),
479 CS42L43_IRQ_REG(AMP1_THERM_SHDN, CLASS_D_AMP),
480 CS42L43_IRQ_REG(AMP2_THERM_WARN, CLASS_D_AMP),
481 CS42L43_IRQ_REG(AMP1_THERM_WARN, CLASS_D_AMP),
482 CS42L43_IRQ_REG(AMP2_SCDET, CLASS_D_AMP),
483 CS42L43_IRQ_REG(AMP1_SCDET, CLASS_D_AMP),
484
485 CS42L43_IRQ_REG(GPIO3_FALL, GPIO),
486 CS42L43_IRQ_REG(GPIO3_RISE, GPIO),
487 CS42L43_IRQ_REG(GPIO2_FALL, GPIO),
488 CS42L43_IRQ_REG(GPIO2_RISE, GPIO),
489 CS42L43_IRQ_REG(GPIO1_FALL, GPIO),
490 CS42L43_IRQ_REG(GPIO1_RISE, GPIO),
491
492 CS42L43_IRQ_REG(HP_ILIMIT, HPOUT),
493 CS42L43_IRQ_REG(HP_LOADDET_DONE, HPOUT),
494};
495
496static const struct regmap_irq_chip cs42l43_irq_chip = {
497 .name = "cs42l43",
498
499 .status_base = CS42L43_DECIM_INT,
500 .mask_base = CS42L43_DECIM_MASK,
501 .num_regs = 16,
502
503 .irqs = cs42l43_regmap_irqs,
504 .num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs),
505
506 .runtime_pm = true,
507};
508
509static const char * const cs42l43_core_supplies[] = {
510 "vdd-a", "vdd-io", "vdd-cp",
511};
512
513static const char * const cs42l43_parent_supplies[] = { "vdd-amp" };
514
515static const struct mfd_cell cs42l43_devs[] = {
516 { .name = "cs42l43-pinctrl", },
517 { .name = "cs42l43-spi", },
518 {
519 .name = "cs42l43-codec",
520 .parent_supplies = cs42l43_parent_supplies,
521 .num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies),
522 },
523};
524
525/*
526 * If the device is connected over Soundwire, as well as soft resetting the
527 * device, this function will also way for the device to detach from the bus
528 * before returning.
529 */
530static int cs42l43_soft_reset(struct cs42l43 *cs42l43)
531{
532 static const struct reg_sequence reset[] = {
533 { CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL },
534 };
535
536 reinit_completion(&cs42l43->device_detach);
537
538 /*
539 * Apply cache only because the soft reset will cause the device to
540 * detach from the soundwire bus.
541 */
542 regcache_cache_only(cs42l43->regmap, true);
543 regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset));
544
545 msleep(CS42L43_RESET_DELAY_MS);
546
547 if (cs42l43->sdw) {
548 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT_MS);
549 unsigned long time;
550
551 time = wait_for_completion_timeout(&cs42l43->device_detach, timeout);
552 if (!time) {
553 dev_err(cs42l43->dev, "Timed out waiting for device detach\n");
554 return -ETIMEDOUT;
555 }
556 }
557
558 return -EAGAIN;
559}
560
561/*
562 * This function is essentially a no-op on I2C, but will wait for the device to
563 * attach when the device is used on a SoundWire bus.
564 */
565static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43)
566{
567 if (!cs42l43->attached) {
568 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT_MS);
569 unsigned long time;
570
571 time = wait_for_completion_timeout(&cs42l43->device_attach, timeout);
572 if (!time) {
573 dev_err(cs42l43->dev, "Timed out waiting for device re-attach\n");
574 return -ETIMEDOUT;
575 }
576 }
577
578 regcache_cache_only(cs42l43->regmap, false);
579
580 /* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */
581 if (cs42l43->sdw)
582 regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL,
583 CS42L43_OSC_DIV2_EN_MASK);
584
585 return 0;
586}
587
588/*
589 * This function will advance the firmware into boot stage 3 from boot stage 2.
590 * Boot stage 3 is required to send commands to the firmware. This is achieved
591 * by setting the firmware NEED configuration register to zero, this indicates
592 * no configuration is required forcing the firmware to advance to boot stage 3.
593 *
594 * Later revisions of the firmware require the use of an alternative register
595 * for this purpose, which is indicated through the shadow flag.
596 */
597static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow)
598{
599 unsigned int need_reg = CS42L43_NEED_CONFIGS;
600 unsigned int val;
601 int ret;
602
603 if (shadow)
604 need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS;
605
606 regmap_write(cs42l43->regmap, need_reg, 0);
607
608 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_BOOT_STATUS,
609 val, (val == CS42L43_MCU_BOOT_STAGE3),
610 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
611 if (ret) {
612 dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val);
613 return ret;
614 }
615
616 return -EAGAIN;
617}
618
619/*
620 * This function will return the firmware to boot stage 2 from boot stage 3.
621 * Boot stage 2 is required to apply updates to the firmware. This is achieved
622 * by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG,
623 * setting the HAVE configuration register to 0, and soft resetting. The
624 * firmware will see it is missing a patch configuration and will pause in boot
625 * stage 2.
626 *
627 * Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow
628 * register here as the driver will only return to boot stage 2 if the firmware
629 * requires update which means the revision does not include shadow register
630 * support.
631 */
632static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43)
633{
634 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS,
635 CS42L43_FW_PATCH_NEED_CFG_MASK);
636 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0);
637
638 return cs42l43_soft_reset(cs42l43);
639}
640
641/*
642 * Disable the firmware running on the device such that the driver can access
643 * the registers without fear of the MCU changing them under it.
644 */
645static int cs42l43_mcu_disable(struct cs42l43 *cs42l43)
646{
647 unsigned int val;
648 int ret;
649
650 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG,
651 CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL);
652 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION,
653 CS42L43_FW_MM_CTRL_MCU_SEL_MASK);
654 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK);
655 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
656
657 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
658 (val & CS42L43_CONTROL_APPLIED_INT_MASK),
659 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US);
660 if (ret) {
661 dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val);
662 return ret;
663 }
664
665 /* Soft reset to clear any register state the firmware left behind. */
666 return cs42l43_soft_reset(cs42l43);
667}
668
669/*
670 * Callback to load firmware updates.
671 */
672static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context)
673{
674 struct cs42l43 *cs42l43 = context;
675 const struct cs42l43_patch_header *hdr;
676 unsigned int loadaddr, val;
677 int ret;
678
679 if (!firmware) {
680 dev_err(cs42l43->dev, "Failed to load firmware\n");
681 cs42l43->firmware_error = -ENODEV;
682 goto err;
683 }
684
685 hdr = (const struct cs42l43_patch_header *)&firmware->data[0];
686 loadaddr = le32_to_cpu(hdr->load_addr);
687
688 if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) {
689 dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version);
690 cs42l43->firmware_error = -EINVAL;
691 goto err_release;
692 }
693
694 regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr);
695 regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET,
696 &firmware->data[0], firmware->size / sizeof(u32));
697
698 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK);
699 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0);
700
701 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val,
702 (val & CS42L43_PATCH_APPLIED_INT_MASK),
703 CS42L43_MCU_POLL_US, CS42L43_MCU_UPDATE_TIMEOUT_US);
704 if (ret) {
705 dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val);
706 cs42l43->firmware_error = ret;
707 goto err_release;
708 }
709
710err_release:
711 release_firmware(firmware);
712err:
713 complete(&cs42l43->firmware_download);
714}
715
716static int cs42l43_mcu_is_hw_compatible(struct cs42l43 *cs42l43,
717 unsigned int mcu_rev,
718 unsigned int bios_rev)
719{
720 /*
721 * The firmware has two revision numbers bringing either of them up to a
722 * supported version will provide the disable the driver requires.
723 */
724 if (mcu_rev < CS42L43_MCU_SUPPORTED_REV &&
725 bios_rev < CS42L43_MCU_SUPPORTED_BIOS_REV) {
726 dev_err(cs42l43->dev, "Firmware too old to support disable\n");
727 return -EINVAL;
728 }
729
730 return 0;
731}
732
733/*
734 * The process of updating the firmware is split into a series of steps, at the
735 * end of each step a soft reset of the device might be required which will
736 * require the driver to wait for the device to re-attach on the SoundWire bus,
737 * if that control bus is being used.
738 */
739static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43)
740{
741 unsigned int mcu_rev, bios_rev, boot_status, secure_cfg;
742 bool patched, shadow;
743 int ret;
744
745 /* Clear any stale software interrupt bits. */
746 regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev);
747
748 ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_STATUS, &boot_status);
749 if (ret) {
750 dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret);
751 return ret;
752 }
753
754 ret = regmap_read(cs42l43->regmap, CS42L43_MCU_SW_REV, &mcu_rev);
755 if (ret) {
756 dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret);
757 return ret;
758 }
759
760 bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) |
761 ((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) |
762 ((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >>
763 CS42L43_BIOS_MAJOR_REV_SHIFT;
764 mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) |
765 ((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) |
766 ((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8);
767
768 /*
769 * The firmware has two revision numbers both of them being at the ROM
770 * revision indicates no patch has been applied.
771 */
772 patched = mcu_rev != CS42L43_MCU_ROM_REV || bios_rev != CS42L43_MCU_ROM_BIOS_REV;
773 /*
774 * Later versions of the firmwware require the driver to access some
775 * features through a set of shadow registers.
776 */
777 shadow = (mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV) ||
778 (bios_rev >= CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV);
779
780 ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg);
781 if (ret) {
782 dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret);
783 return ret;
784 }
785
786 cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK;
787
788 if (!patched && cs42l43->hw_lock) {
789 dev_err(cs42l43->dev, "Unpatched secure device\n");
790 return -EPERM;
791 }
792
793 dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n",
794 mcu_rev, bios_rev, boot_status);
795
796 switch (boot_status) {
797 case CS42L43_MCU_BOOT_STAGE2:
798 if (!patched) {
799 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
800 "cs42l43.bin", cs42l43->dev,
801 GFP_KERNEL, cs42l43,
802 cs42l43_mcu_load_firmware);
803 if (ret) {
804 dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret);
805 return ret;
806 }
807
808 wait_for_completion(&cs42l43->firmware_download);
809
810 if (cs42l43->firmware_error)
811 return cs42l43->firmware_error;
812
813 return -EAGAIN;
814 } else {
815 return cs42l43_mcu_stage_2_3(cs42l43, shadow);
816 }
817 case CS42L43_MCU_BOOT_STAGE3:
818 if (patched) {
819 ret = cs42l43_mcu_is_hw_compatible(cs42l43, mcu_rev, bios_rev);
820 if (ret)
821 return ret;
822
823 return cs42l43_mcu_disable(cs42l43);
824 } else {
825 return cs42l43_mcu_stage_3_2(cs42l43);
826 }
827 case CS42L43_MCU_BOOT_STAGE4:
828 return 0;
829 default:
830 dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status);
831 return -EINVAL;
832 }
833}
834
835/*
836 * Update the firmware running on the device.
837 */
838static int cs42l43_mcu_update(struct cs42l43 *cs42l43)
839{
840 int i, ret;
841
842 for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) {
843 ret = cs42l43_mcu_update_step(cs42l43);
844 if (ret != -EAGAIN)
845 return ret;
846
847 ret = cs42l43_wait_for_attach(cs42l43);
848 if (ret)
849 return ret;
850 }
851
852 dev_err(cs42l43->dev, "Failed retrying update\n");
853 return -ETIMEDOUT;
854}
855
856static int cs42l43_irq_config(struct cs42l43 *cs42l43)
857{
858 struct irq_data *irq_data;
859 unsigned long irq_flags;
860 int ret;
861
862 if (cs42l43->sdw)
863 cs42l43->irq = cs42l43->sdw->irq;
864
865 cs42l43->irq_chip = cs42l43_irq_chip;
866 cs42l43->irq_chip.irq_drv_data = cs42l43;
867
868 irq_data = irq_get_irq_data(cs42l43->irq);
869 if (!irq_data) {
870 dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq);
871 return -EINVAL;
872 }
873
874 irq_flags = irqd_get_trigger_type(irq_data);
875 switch (irq_flags) {
876 case IRQF_TRIGGER_LOW:
877 case IRQF_TRIGGER_HIGH:
878 case IRQF_TRIGGER_RISING:
879 case IRQF_TRIGGER_FALLING:
880 break;
881 case IRQ_TYPE_NONE:
882 default:
883 irq_flags = IRQF_TRIGGER_LOW;
884 break;
885 }
886
887 irq_flags |= IRQF_ONESHOT;
888
889 ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap,
890 cs42l43->irq, irq_flags, 0,
891 &cs42l43->irq_chip, &cs42l43->irq_data);
892 if (ret) {
893 dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret);
894 return ret;
895 }
896
897 dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n",
898 cs42l43->irq, irq_flags);
899
900 return 0;
901}
902
903static void cs42l43_boot_work(struct work_struct *work)
904{
905 struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work);
906 unsigned int devid, revid, otp;
907 int ret;
908
909 ret = cs42l43_wait_for_attach(cs42l43);
910 if (ret)
911 goto err;
912
913 ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid);
914 if (ret) {
915 dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret);
916 goto err;
917 }
918
919 switch (devid) {
920 case CS42L43_DEVID_VAL:
921 break;
922 default:
923 dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid);
924 goto err;
925 }
926
927 ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid);
928 if (ret) {
929 dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret);
930 goto err;
931 }
932
933 ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp);
934 if (ret) {
935 dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret);
936 goto err;
937 }
938
939 dev_info(cs42l43->dev,
940 "devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp);
941
942 ret = cs42l43_mcu_update(cs42l43);
943 if (ret)
944 goto err;
945
946 ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch,
947 ARRAY_SIZE(cs42l43_reva_patch));
948 if (ret) {
949 dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret);
950 goto err;
951 }
952
953 ret = cs42l43_irq_config(cs42l43);
954 if (ret)
955 goto err;
956
957 ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE,
958 cs42l43_devs, ARRAY_SIZE(cs42l43_devs),
959 NULL, 0, NULL);
960 if (ret) {
961 dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret);
962 goto err;
963 }
964
965 pm_runtime_put_autosuspend(cs42l43->dev);
966
967 return;
968
969err:
970 pm_runtime_put_sync(cs42l43->dev);
971}
972
973static int cs42l43_power_up(struct cs42l43 *cs42l43)
974{
975 int ret;
976
977 ret = regulator_enable(cs42l43->vdd_p);
978 if (ret) {
979 dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret);
980 return ret;
981 }
982
983 /* vdd-p must be on for 50uS before any other supply */
984 usleep_range(CS42L43_VDDP_DELAY_US, 2 * CS42L43_VDDP_DELAY_US);
985
986 gpiod_set_raw_value_cansleep(cs42l43->reset, 1);
987
988 ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
989 if (ret) {
990 dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret);
991 goto err_reset;
992 }
993
994 ret = regulator_enable(cs42l43->vdd_d);
995 if (ret) {
996 dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret);
997 goto err_core_supplies;
998 }
999
1000 usleep_range(CS42L43_VDDD_DELAY_US, 2 * CS42L43_VDDD_DELAY_US);
1001
1002 return 0;
1003
1004err_core_supplies:
1005 regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
1006err_reset:
1007 gpiod_set_raw_value_cansleep(cs42l43->reset, 0);
1008 regulator_disable(cs42l43->vdd_p);
1009
1010 return ret;
1011}
1012
1013static int cs42l43_power_down(struct cs42l43 *cs42l43)
1014{
1015 int ret;
1016
1017 ret = regulator_disable(cs42l43->vdd_d);
1018 if (ret) {
1019 dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret);
1020 return ret;
1021 }
1022
1023 ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies);
1024 if (ret) {
1025 dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret);
1026 return ret;
1027 }
1028
1029 gpiod_set_raw_value_cansleep(cs42l43->reset, 0);
1030
1031 ret = regulator_disable(cs42l43->vdd_p);
1032 if (ret) {
1033 dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret);
1034 return ret;
1035 }
1036
1037 return 0;
1038}
1039
1040static void cs42l43_dev_remove(void *data)
1041{
1042 struct cs42l43 *cs42l43 = data;
1043
1044 cancel_work_sync(&cs42l43->boot_work);
1045
1046 cs42l43_power_down(cs42l43);
1047}
1048
1049int cs42l43_dev_probe(struct cs42l43 *cs42l43)
1050{
1051 int i, ret;
1052
1053 dev_set_drvdata(cs42l43->dev, cs42l43);
1054
1055 mutex_init(&cs42l43->pll_lock);
1056 init_completion(&cs42l43->device_attach);
1057 init_completion(&cs42l43->device_detach);
1058 init_completion(&cs42l43->firmware_download);
1059 INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work);
1060
1061 regcache_cache_only(cs42l43->regmap, true);
1062
1063 cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_HIGH);
1064 if (IS_ERR(cs42l43->reset))
1065 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset),
1066 "Failed to get reset\n");
1067
1068 gpiod_set_raw_value_cansleep(cs42l43->reset, 0);
1069
1070 cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p");
1071 if (IS_ERR(cs42l43->vdd_p))
1072 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p),
1073 "Failed to get vdd-p\n");
1074
1075 cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d");
1076 if (IS_ERR(cs42l43->vdd_d))
1077 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d),
1078 "Failed to get vdd-d\n");
1079
1080 BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES);
1081
1082 for (i = 0; i < CS42L43_N_SUPPLIES; i++)
1083 cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i];
1084
1085 ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES,
1086 cs42l43->core_supplies);
1087 if (ret)
1088 return dev_err_probe(cs42l43->dev, ret,
1089 "Failed to get core supplies\n");
1090
1091 ret = cs42l43_power_up(cs42l43);
1092 if (ret)
1093 return ret;
1094
1095 ret = devm_add_action_or_reset(cs42l43->dev, cs42l43_dev_remove, cs42l43);
1096 if (ret)
1097 return ret;
1098
1099 pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME_MS);
1100 pm_runtime_use_autosuspend(cs42l43->dev);
1101 pm_runtime_set_active(cs42l43->dev);
1102 /*
1103 * The device is already powered up, but keep it from suspending until
1104 * the boot work runs.
1105 */
1106 pm_runtime_get_noresume(cs42l43->dev);
1107 ret = devm_pm_runtime_enable(cs42l43->dev);
1108 if (ret)
1109 return ret;
1110
1111 queue_work(system_long_wq, &cs42l43->boot_work);
1112
1113 return 0;
1114}
1115EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, "MFD_CS42L43");
1116
1117static int cs42l43_suspend(struct device *dev)
1118{
1119 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1120 int ret;
1121
1122 ret = pm_runtime_resume_and_get(dev);
1123 if (ret) {
1124 dev_err(cs42l43->dev, "Failed to resume for suspend: %d\n", ret);
1125 return ret;
1126 }
1127
1128 disable_irq(cs42l43->irq);
1129
1130 ret = pm_runtime_force_suspend(dev);
1131 if (ret) {
1132 dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret);
1133 pm_runtime_put_noidle(dev);
1134 return ret;
1135 }
1136
1137 pm_runtime_put_noidle(dev);
1138
1139 ret = cs42l43_power_down(cs42l43);
1140 if (ret)
1141 return ret;
1142
1143 return 0;
1144}
1145
1146static int cs42l43_suspend_noirq(struct device *dev)
1147{
1148 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1149
1150 enable_irq(cs42l43->irq);
1151
1152 return 0;
1153}
1154
1155static int cs42l43_resume_noirq(struct device *dev)
1156{
1157 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1158
1159 disable_irq(cs42l43->irq);
1160
1161 return 0;
1162}
1163
1164static int cs42l43_resume(struct device *dev)
1165{
1166 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1167 int ret;
1168
1169 ret = cs42l43_power_up(cs42l43);
1170 if (ret)
1171 return ret;
1172
1173 ret = pm_runtime_force_resume(dev);
1174 if (ret) {
1175 dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret);
1176 return ret;
1177 }
1178
1179 enable_irq(cs42l43->irq);
1180
1181 return 0;
1182}
1183
1184static int cs42l43_runtime_suspend(struct device *dev)
1185{
1186 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1187
1188 /*
1189 * Whilst the driver doesn't power the chip down here, going into runtime
1190 * suspend lets the SoundWire bus power down, which means the driver
1191 * can't communicate with the device any more.
1192 */
1193 regcache_cache_only(cs42l43->regmap, true);
1194
1195 return 0;
1196}
1197
1198static int cs42l43_runtime_resume(struct device *dev)
1199{
1200 struct cs42l43 *cs42l43 = dev_get_drvdata(dev);
1201 unsigned int reset_canary;
1202 int ret;
1203
1204 ret = cs42l43_wait_for_attach(cs42l43);
1205 if (ret)
1206 return ret;
1207
1208 ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary);
1209 if (ret) {
1210 dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret);
1211 goto err;
1212 }
1213
1214 if (!reset_canary) {
1215 /*
1216 * If the canary has cleared the chip has reset, re-handle the
1217 * MCU and mark the cache as dirty to indicate the chip reset.
1218 */
1219 ret = cs42l43_mcu_update(cs42l43);
1220 if (ret)
1221 goto err;
1222
1223 regcache_mark_dirty(cs42l43->regmap);
1224 }
1225
1226 ret = regcache_sync(cs42l43->regmap);
1227 if (ret) {
1228 dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret);
1229 goto err;
1230 }
1231
1232 return 0;
1233
1234err:
1235 regcache_cache_only(cs42l43->regmap, true);
1236
1237 return ret;
1238}
1239
1240EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = {
1241 SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume)
1242 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend_noirq, cs42l43_resume_noirq)
1243 RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL)
1244};
1245
1246MODULE_DESCRIPTION("CS42L43 Core Driver");
1247MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1248MODULE_LICENSE("GPL");
1249MODULE_FIRMWARE("cs42l43.bin");