Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#ifndef __IRIS_VPU_BUFFER_H__
7#define __IRIS_VPU_BUFFER_H__
8
9struct iris_inst;
10
11#define MIN_BUFFERS 4
12
13#define DMA_ALIGNMENT 256
14
15#define NUM_HW_PIC_BUF 32
16#define LCU_MAX_SIZE_PELS 64
17#define LCU_MIN_SIZE_PELS 16
18#define HDR10_HIST_EXTRADATA_SIZE (4 * 1024)
19
20#define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf))
21
22#define MAX_TILE_COLUMNS 32
23#define BIN_BUFFER_THRESHOLD (1280 * 736)
24#define VPP_CMD_MAX_SIZE (BIT(20))
25#define H264D_MAX_SLICE 1800
26
27#define SIZE_H264D_BUFTAB_T 256
28#define SIZE_H264D_BSE_CMD_PER_BUF (32 * 4)
29#define SIZE_H264D_VPP_CMD_PER_BUF 512
30
31#define NUM_SLIST_BUF_H264 (256 + 32)
32#define SIZE_SLIST_BUF_H264 512
33#define H264_DISPLAY_BUF_SIZE 3328
34#define H264_NUM_FRM_INFO 66
35#define H265_NUM_TILE_COL 32
36#define H265_NUM_TILE_ROW 128
37#define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1)
38#define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32))
39
40#define NUM_SLIST_BUF_H265 (80 + 20)
41#define SIZE_SLIST_BUF_H265 (BIT(10))
42#define H265_DISPLAY_BUF_SIZE (3072)
43#define H265_NUM_FRM_INFO (48)
44#define SIZE_ONE_SLICE_BUF 256
45
46#define VP9_NUM_FRAME_INFO_BUF 32
47#define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4)
48#define VP9_PROB_TABLE_SIZE (3840)
49#define VP9_FRAME_INFO_BUF_SIZE (6144)
50#define BUFFER_ALIGNMENT_32_BYTES 32
51#define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
52#define MAX_SUPERFRAME_HEADER_LEN (34)
53#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
54#define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64
55#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64
56#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8)
57#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8)
58#define VP9_UDC_HEADER_BUF_SIZE (3 * 128)
59
60#define SIZE_SEI_USERDATA 4096
61#define SIZE_DOLBY_RPU_METADATA (41 * 1024)
62#define H264_CABAC_HDR_RATIO_HD_TOT 1
63#define H264_CABAC_RES_RATIO_HD_TOT 3
64#define H265D_MAX_SLICE 1200
65#define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T
66#define H265_CABAC_HDR_RATIO_HD_TOT 2
67#define H265_CABAC_RES_RATIO_HD_TOT 2
68#define SIZE_H265D_VPP_CMD_PER_BUF (256)
69
70#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
71#define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1
72#define VPX_DECODER_FRAME_BIN_RES_BUDGET 3
73#define VPX_DECODER_FRAME_BIN_DENOMINATOR 2
74
75#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
76
77#define SIZE_H264D_HW_PIC_T (BIT(11))
78
79#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
80#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16
81#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384
82#define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640
83
84#define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256))
85#define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096)
86#define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3)
87#define SIZE_LAMBDA_LUT (256 * 11)
88
89#define HFI_COL_FMT_NV12C_Y_TILE_HEIGHT (8)
90#define HFI_COL_FMT_NV12C_Y_TILE_WIDTH (32)
91#define HFI_COL_FMT_TP10C_Y_TILE_HEIGHT (4)
92#define HFI_COL_FMT_TP10C_Y_TILE_WIDTH (48)
93
94#define IRIS_METADATA_STRIDE_MULTIPLE 64
95#define IRIS_METADATA_HEIGHT_MULTIPLE 16
96
97#define HFI_BUFFER_ARP_ENC 204800
98
99#define MAX_WIDTH 4096
100#define MAX_HEIGHT 2304
101#define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16))
102#define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4))
103
104static inline u32 size_h264d_lb_fe_top_data(u32 frame_width)
105{
106 return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3;
107}
108
109static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width)
110{
111 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
112}
113
114static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height)
115{
116 return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
117}
118
119static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width)
120{
121 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
122}
123
124static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height)
125{
126 return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
127}
128
129static inline u32 size_h264d_lb_pe_top_data(u32 frame_width)
130{
131 return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
132}
133
134static inline u32 size_h264d_lb_vsp_top(u32 frame_width)
135{
136 return (DIV_ROUND_UP(frame_width, 16) << 7);
137}
138
139static inline u32 size_h264d_lb_recon_dma_metadata_wr(u32 frame_height)
140{
141 return ALIGN(frame_height, 16) * 32;
142}
143
144static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height)
145{
146 return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128;
147}
148
149u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
150u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
151int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
152
153#endif