Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#ifndef __IRIS_PLATFORM_COMMON_H__
7#define __IRIS_PLATFORM_COMMON_H__
8
9#include <linux/bits.h>
10#include "iris_buffer.h"
11
12struct iris_core;
13struct iris_inst;
14
15#define IRIS_PAS_ID 9
16#define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */
17#define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */
18
19#define REGISTER_BIT_DEPTH(luma, chroma) ((luma) << 16 | (chroma))
20#define BIT_DEPTH_8 REGISTER_BIT_DEPTH(8, 8)
21#define CODED_FRAMES_PROGRESSIVE 0x0
22#define DEFAULT_MAX_HOST_BUF_COUNT 64
23#define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256
24#define DEFAULT_FPS 30
25#define MAXIMUM_FPS 480
26#define NUM_MBS_8K ((8192 * 4352) / 256)
27#define MIN_QP_8BIT 1
28#define MAX_QP 51
29#define MAX_QP_HEVC 63
30#define DEFAULT_QP 20
31#define BITRATE_DEFAULT 20000000
32
33enum stage_type {
34 STAGE_1 = 1,
35 STAGE_2 = 2,
36};
37
38enum pipe_type {
39 PIPE_1 = 1,
40 PIPE_2 = 2,
41 PIPE_4 = 4,
42};
43
44extern const struct iris_platform_data qcs8300_data;
45extern const struct iris_platform_data sc7280_data;
46extern const struct iris_platform_data sm8250_data;
47extern const struct iris_platform_data sm8550_data;
48extern const struct iris_platform_data sm8650_data;
49extern const struct iris_platform_data sm8750_data;
50
51enum platform_clk_type {
52 IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
53 IRIS_CTRL_CLK,
54 IRIS_AHB_CLK,
55 IRIS_HW_CLK,
56 IRIS_HW_AHB_CLK,
57 IRIS_AXI1_CLK,
58 IRIS_CTRL_FREERUN_CLK,
59 IRIS_HW_FREERUN_CLK,
60};
61
62struct platform_clk_data {
63 enum platform_clk_type clk_type;
64 const char *clk_name;
65};
66
67struct tz_cp_config {
68 u32 cp_start;
69 u32 cp_size;
70 u32 cp_nonpixel_start;
71 u32 cp_nonpixel_size;
72};
73
74struct ubwc_config_data {
75 u32 max_channels;
76 u32 mal_length;
77 u32 highest_bank_bit;
78 u32 bank_swzl_level;
79 u32 bank_swz2_level;
80 u32 bank_swz3_level;
81 u32 bank_spreading;
82};
83
84struct platform_inst_caps {
85 u32 min_frame_width;
86 u32 max_frame_width;
87 u32 min_frame_height;
88 u32 max_frame_height;
89 u32 max_mbpf;
90 u32 mb_cycles_vsp;
91 u32 mb_cycles_vpp;
92 u32 mb_cycles_fw;
93 u32 mb_cycles_fw_vpp;
94 u32 num_comv;
95 u32 max_frame_rate;
96 u32 max_operating_rate;
97};
98
99enum platform_inst_fw_cap_type {
100 PROFILE_H264 = 1,
101 PROFILE_HEVC,
102 PROFILE_VP9,
103 LEVEL_H264,
104 LEVEL_HEVC,
105 LEVEL_VP9,
106 INPUT_BUF_HOST_MAX_COUNT,
107 OUTPUT_BUF_HOST_MAX_COUNT,
108 STAGE,
109 PIPE,
110 POC,
111 CODED_FRAMES,
112 BIT_DEPTH,
113 RAP_FRAME,
114 TIER,
115 HEADER_MODE,
116 PREPEND_SPSPPS_TO_IDR,
117 BITRATE,
118 BITRATE_PEAK,
119 BITRATE_MODE,
120 FRAME_SKIP_MODE,
121 FRAME_RC_ENABLE,
122 GOP_SIZE,
123 ENTROPY_MODE,
124 MIN_FRAME_QP_H264,
125 MIN_FRAME_QP_HEVC,
126 MAX_FRAME_QP_H264,
127 MAX_FRAME_QP_HEVC,
128 I_FRAME_MIN_QP_H264,
129 I_FRAME_MIN_QP_HEVC,
130 P_FRAME_MIN_QP_H264,
131 P_FRAME_MIN_QP_HEVC,
132 B_FRAME_MIN_QP_H264,
133 B_FRAME_MIN_QP_HEVC,
134 I_FRAME_MAX_QP_H264,
135 I_FRAME_MAX_QP_HEVC,
136 P_FRAME_MAX_QP_H264,
137 P_FRAME_MAX_QP_HEVC,
138 B_FRAME_MAX_QP_H264,
139 B_FRAME_MAX_QP_HEVC,
140 I_FRAME_QP_H264,
141 I_FRAME_QP_HEVC,
142 P_FRAME_QP_H264,
143 P_FRAME_QP_HEVC,
144 B_FRAME_QP_H264,
145 B_FRAME_QP_HEVC,
146 INST_FW_CAP_MAX,
147};
148
149enum platform_inst_fw_cap_flags {
150 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0),
151 CAP_FLAG_MENU = BIT(1),
152 CAP_FLAG_INPUT_PORT = BIT(2),
153 CAP_FLAG_OUTPUT_PORT = BIT(3),
154 CAP_FLAG_CLIENT_SET = BIT(4),
155 CAP_FLAG_BITMASK = BIT(5),
156 CAP_FLAG_VOLATILE = BIT(6),
157};
158
159struct platform_inst_fw_cap {
160 enum platform_inst_fw_cap_type cap_id;
161 s64 min;
162 s64 max;
163 s64 step_or_mask;
164 s64 value;
165 u32 hfi_id;
166 enum platform_inst_fw_cap_flags flags;
167 int (*set)(struct iris_inst *inst,
168 enum platform_inst_fw_cap_type cap_id);
169};
170
171struct bw_info {
172 u32 mbs_per_sec;
173 u32 bw_ddr;
174};
175
176struct iris_core_power {
177 u64 clk_freq;
178 u64 icc_bw;
179};
180
181struct iris_inst_power {
182 u64 min_freq;
183 u32 icc_bw;
184};
185
186struct icc_vote_data {
187 u32 height, width;
188 u32 fps;
189};
190
191enum platform_pm_domain_type {
192 IRIS_CTRL_POWER_DOMAIN,
193 IRIS_HW_POWER_DOMAIN,
194};
195
196struct iris_platform_data {
197 void (*init_hfi_command_ops)(struct iris_core *core);
198 void (*init_hfi_response_ops)(struct iris_core *core);
199 struct iris_inst *(*get_instance)(void);
200 u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type);
201 const struct vpu_ops *vpu_ops;
202 void (*set_preset_registers)(struct iris_core *core);
203 const struct icc_info *icc_tbl;
204 unsigned int icc_tbl_size;
205 const struct bw_info *bw_tbl_dec;
206 unsigned int bw_tbl_dec_size;
207 const char * const *pmdomain_tbl;
208 unsigned int pmdomain_tbl_size;
209 const char * const *opp_pd_tbl;
210 unsigned int opp_pd_tbl_size;
211 const struct platform_clk_data *clk_tbl;
212 unsigned int clk_tbl_size;
213 const char * const *clk_rst_tbl;
214 unsigned int clk_rst_tbl_size;
215 const char * const *controller_rst_tbl;
216 unsigned int controller_rst_tbl_size;
217 u64 dma_mask;
218 const char *fwname;
219 u32 pas_id;
220 struct platform_inst_caps *inst_caps;
221 const struct platform_inst_fw_cap *inst_fw_caps_dec;
222 u32 inst_fw_caps_dec_size;
223 const struct platform_inst_fw_cap *inst_fw_caps_enc;
224 u32 inst_fw_caps_enc_size;
225 struct tz_cp_config *tz_cp_config_data;
226 u32 core_arch;
227 u32 hw_response_timeout;
228 struct ubwc_config_data *ubwc_config;
229 u32 num_vpp_pipe;
230 bool no_aon;
231 u32 max_session_count;
232 /* max number of macroblocks per frame supported */
233 u32 max_core_mbpf;
234 /* max number of macroblocks per second supported */
235 u32 max_core_mbps;
236 const u32 *dec_input_config_params_default;
237 unsigned int dec_input_config_params_default_size;
238 const u32 *dec_input_config_params_hevc;
239 unsigned int dec_input_config_params_hevc_size;
240 const u32 *dec_input_config_params_vp9;
241 unsigned int dec_input_config_params_vp9_size;
242 const u32 *dec_output_config_params;
243 unsigned int dec_output_config_params_size;
244 const u32 *enc_input_config_params;
245 unsigned int enc_input_config_params_size;
246 const u32 *enc_output_config_params;
247 unsigned int enc_output_config_params_size;
248 const u32 *dec_input_prop;
249 unsigned int dec_input_prop_size;
250 const u32 *dec_output_prop_avc;
251 unsigned int dec_output_prop_avc_size;
252 const u32 *dec_output_prop_hevc;
253 unsigned int dec_output_prop_hevc_size;
254 const u32 *dec_output_prop_vp9;
255 unsigned int dec_output_prop_vp9_size;
256 const u32 *dec_ip_int_buf_tbl;
257 unsigned int dec_ip_int_buf_tbl_size;
258 const u32 *dec_op_int_buf_tbl;
259 unsigned int dec_op_int_buf_tbl_size;
260 const u32 *enc_ip_int_buf_tbl;
261 unsigned int enc_ip_int_buf_tbl_size;
262 const u32 *enc_op_int_buf_tbl;
263 unsigned int enc_op_int_buf_tbl_size;
264};
265
266#endif