tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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kernel / drivers / irqchip / Kconfig
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1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V3_ITS_FSL_MC 55 bool 56 depends on ARM_GIC_V3_ITS 57 depends on FSL_MC_BUS 58 default ARM_GIC_V3_ITS 59 60config ARM_GIC_V5 61 bool 62 select IRQ_DOMAIN_HIERARCHY 63 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 64 select GENERIC_MSI_IRQ 65 select IRQ_MSI_LIB 66 select ARM_GIC_ITS_PARENT 67 68config ARM_NVIC 69 bool 70 select IRQ_DOMAIN_HIERARCHY 71 select GENERIC_IRQ_CHIP 72 73config ARM_VIC 74 bool 75 select IRQ_DOMAIN 76 77config ARM_VIC_NR 78 int 79 default 4 if ARCH_S5PV210 80 default 2 81 depends on ARM_VIC 82 help 83 The maximum number of VICs available in the system, for 84 power management. 85 86config IRQ_MSI_LIB 87 bool 88 select GENERIC_MSI_IRQ 89 90config ARMADA_370_XP_IRQ 91 bool 92 select GENERIC_IRQ_CHIP 93 select PCI_MSI if PCI 94 select IRQ_MSI_LIB if PCI 95 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 96 97config ALPINE_MSI 98 bool 99 depends on PCI 100 select PCI_MSI 101 select IRQ_MSI_LIB 102 select GENERIC_IRQ_CHIP 103 104config AL_FIC 105 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 106 depends on OF 107 depends on HAS_IOMEM 108 select GENERIC_IRQ_CHIP 109 select IRQ_DOMAIN 110 help 111 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 112 113config ATMEL_AIC_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select SPARSE_IRQ 118 119config ATMEL_AIC5_IRQ 120 bool 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select SPARSE_IRQ 124 125config I8259 126 bool 127 select IRQ_DOMAIN 128 129config BCM2712_MIP 130 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 131 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 132 default m if ARCH_BRCMSTB || ARCH_BCM2835 133 depends on ARM_GIC 134 select GENERIC_IRQ_CHIP 135 select IRQ_DOMAIN_HIERARCHY 136 select GENERIC_MSI_IRQ 137 select IRQ_MSI_LIB 138 help 139 Enable support for the Broadcom BCM2712 MSI-X target peripheral 140 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 141 Raspberry Pi 5. 142 143 If unsure say n. 144 145config BCM6345_L1_IRQ 146 bool 147 select GENERIC_IRQ_CHIP 148 select IRQ_DOMAIN 149 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 150 151config BCM7038_L1_IRQ 152 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 153 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 154 default ARCH_BRCMSTB || BMIPS_GENERIC 155 select GENERIC_IRQ_CHIP 156 select IRQ_DOMAIN 157 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 158 159config BCM7120_L2_IRQ 160 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 161 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 162 default ARCH_BRCMSTB || BMIPS_GENERIC 163 select GENERIC_IRQ_CHIP 164 select IRQ_DOMAIN 165 166config BRCMSTB_L2_IRQ 167 tristate "Broadcom STB generic L2 interrupt controller driver" 168 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 169 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 170 select GENERIC_IRQ_CHIP 171 select IRQ_DOMAIN 172 173config DAVINCI_CP_INTC 174 bool 175 select GENERIC_IRQ_CHIP 176 select IRQ_DOMAIN 177 178config DW_APB_ICTL 179 bool 180 select GENERIC_IRQ_CHIP 181 select IRQ_DOMAIN_HIERARCHY 182 183config ECONET_EN751221_INTC 184 bool 185 select GENERIC_IRQ_CHIP 186 select IRQ_DOMAIN 187 188config FARADAY_FTINTC010 189 bool 190 select IRQ_DOMAIN 191 select SPARSE_IRQ 192 193config HISILICON_IRQ_MBIGEN 194 bool 195 select ARM_GIC_V3 196 select ARM_GIC_V3_ITS 197 198config IMGPDC_IRQ 199 bool 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 203config IXP4XX_IRQ 204 bool 205 select IRQ_DOMAIN 206 select SPARSE_IRQ 207 208config LAN966X_OIC 209 tristate "Microchip LAN966x OIC Support" 210 depends on MCHP_LAN966X_PCI || COMPILE_TEST 211 select GENERIC_IRQ_CHIP 212 select IRQ_DOMAIN 213 help 214 Enable support for the LAN966x Outbound Interrupt Controller. 215 This controller is present on the Microchip LAN966x PCI device and 216 maps the internal interrupts sources to PCIe interrupt. 217 218 To compile this driver as a module, choose M here: the module 219 will be called irq-lan966x-oic. 220 221config MADERA_IRQ 222 tristate 223 224config IRQ_MIPS_CPU 225 bool 226 select GENERIC_IRQ_CHIP 227 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 228 select IRQ_DOMAIN 229 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 230 231config CLPS711X_IRQCHIP 232 bool 233 depends on ARCH_CLPS711X 234 select IRQ_DOMAIN 235 select SPARSE_IRQ 236 default y 237 238config OMPIC 239 bool 240 241config OR1K_PIC 242 bool 243 select IRQ_DOMAIN 244 245config OMAP_IRQCHIP 246 bool 247 select GENERIC_IRQ_CHIP 248 select IRQ_DOMAIN 249 250config ORION_IRQCHIP 251 bool 252 select IRQ_DOMAIN 253 254config PIC32_EVIC 255 bool 256 select GENERIC_IRQ_CHIP 257 select IRQ_DOMAIN 258 259config JCORE_AIC 260 bool "J-Core integrated AIC" if COMPILE_TEST 261 depends on OF 262 select IRQ_DOMAIN 263 help 264 Support for the J-Core integrated AIC. 265 266config RDA_INTC 267 bool 268 select IRQ_DOMAIN 269 270config RENESAS_INTC_IRQPIN 271 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 272 select IRQ_DOMAIN 273 help 274 Enable support for the Renesas Interrupt Controller for external 275 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 276 277config RENESAS_IRQC 278 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 279 select GENERIC_IRQ_CHIP 280 select IRQ_DOMAIN 281 help 282 Enable support for the Renesas Interrupt Controller for external 283 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 284 285config RENESAS_RZA1_IRQC 286 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 287 select IRQ_DOMAIN_HIERARCHY 288 help 289 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 290 to 8 external interrupts with configurable sense select. 291 292config RENESAS_RZG2L_IRQC 293 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 294 select GENERIC_IRQ_CHIP 295 select IRQ_DOMAIN_HIERARCHY 296 help 297 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 298 for external devices. 299 300config RENESAS_RZV2H_ICU 301 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 302 select GENERIC_IRQ_CHIP 303 select IRQ_DOMAIN_HIERARCHY 304 help 305 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 306 307config SL28CPLD_INTC 308 bool "Kontron sl28cpld IRQ controller" 309 depends on MFD_SL28CPLD=y || COMPILE_TEST 310 select REGMAP_IRQ 311 help 312 Interrupt controller driver for the board management controller 313 found on the Kontron sl28 CPLD. 314 315config ST_IRQCHIP 316 bool 317 select REGMAP 318 select MFD_SYSCON 319 help 320 Enables SysCfg Controlled IRQs on STi based platforms. 321 322config SUN4I_INTC 323 bool 324 325config SUN6I_R_INTC 326 bool 327 select IRQ_DOMAIN_HIERARCHY 328 select IRQ_FASTEOI_HIERARCHY_HANDLERS 329 330config SUNXI_NMI_INTC 331 bool 332 select GENERIC_IRQ_CHIP 333 334config TB10X_IRQC 335 bool 336 select IRQ_DOMAIN 337 select GENERIC_IRQ_CHIP 338 339config TS4800_IRQ 340 tristate "TS-4800 IRQ controller" 341 select IRQ_DOMAIN 342 depends on HAS_IOMEM 343 depends on SOC_IMX51 || COMPILE_TEST 344 help 345 Support for the TS-4800 FPGA IRQ controller 346 347config VERSATILE_FPGA_IRQ 348 bool 349 select IRQ_DOMAIN 350 351config VERSATILE_FPGA_IRQ_NR 352 int 353 default 4 354 depends on VERSATILE_FPGA_IRQ 355 356config XTENSA_MX 357 bool 358 select IRQ_DOMAIN 359 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 360 361config XILINX_INTC 362 bool "Xilinx Interrupt Controller IP" 363 depends on OF_ADDRESS 364 select IRQ_DOMAIN 365 help 366 Support for the Xilinx Interrupt Controller IP core. 367 This is used as a primary controller with MicroBlaze and can also 368 be used as a secondary chained controller on other platforms. 369 370config IRQ_CROSSBAR 371 bool 372 help 373 Support for a CROSSBAR ip that precedes the main interrupt controller. 374 The primary irqchip invokes the crossbar's callback which inturn allocates 375 a free irq and configures the IP. Thus the peripheral interrupts are 376 routed to one of the free irqchip interrupt lines. 377 378config KEYSTONE_IRQ 379 tristate "Keystone 2 IRQ controller IP" 380 depends on ARCH_KEYSTONE 381 help 382 Support for Texas Instruments Keystone 2 IRQ controller IP which 383 is part of the Keystone 2 IPC mechanism 384 385config MIPS_GIC 386 bool 387 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 388 select GENERIC_IRQ_IPI if SMP 389 select IRQ_DOMAIN_HIERARCHY 390 select MIPS_CM 391 392config INGENIC_IRQ 393 bool 394 depends on MACH_INGENIC 395 default y 396 397config INGENIC_TCU_IRQ 398 bool "Ingenic JZ47xx TCU interrupt controller" 399 default MACH_INGENIC 400 depends on MIPS || COMPILE_TEST 401 select MFD_SYSCON 402 select GENERIC_IRQ_CHIP 403 help 404 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 405 JZ47xx SoCs. 406 407 If unsure, say N. 408 409config IMX_GPCV2 410 bool 411 select IRQ_DOMAIN 412 help 413 Enables the wakeup IRQs for IMX platforms with GPCv2 block 414 415config IRQ_MXS 416 def_bool y if MACH_ASM9260 || ARCH_MXS 417 select IRQ_DOMAIN 418 select STMP_DEVICE 419 420config MSCC_OCELOT_IRQ 421 bool 422 select IRQ_DOMAIN 423 select GENERIC_IRQ_CHIP 424 425config MVEBU_GICP 426 select IRQ_MSI_LIB 427 bool 428 429config MVEBU_ICU 430 bool 431 432config MVEBU_ODMI 433 bool 434 select IRQ_MSI_LIB 435 select GENERIC_MSI_IRQ 436 437config MVEBU_PIC 438 bool 439 440config MVEBU_SEI 441 bool 442 443config LS_EXTIRQ 444 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 445 select MFD_SYSCON 446 447config LS_SCFG_MSI 448 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 449 select IRQ_MSI_IOMMU 450 depends on PCI_MSI 451 select IRQ_MSI_LIB 452 453config STM32MP_EXTI 454 tristate "STM32MP extended interrupts and event controller" 455 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 456 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 457 select IRQ_DOMAIN_HIERARCHY 458 select GENERIC_IRQ_CHIP 459 help 460 Support STM32MP EXTI (extended interrupts and event) controller. 461 462config STM32_EXTI 463 bool 464 select IRQ_DOMAIN 465 select GENERIC_IRQ_CHIP 466 467config QCOM_IRQ_COMBINER 468 bool "QCOM IRQ combiner support" 469 depends on ARCH_QCOM && ACPI 470 select IRQ_DOMAIN_HIERARCHY 471 help 472 Say yes here to add support for the IRQ combiner devices embedded 473 in Qualcomm Technologies chips. 474 475config IRQ_UNIPHIER_AIDET 476 bool "UniPhier AIDET support" if COMPILE_TEST 477 depends on ARCH_UNIPHIER || COMPILE_TEST 478 default ARCH_UNIPHIER 479 select IRQ_DOMAIN_HIERARCHY 480 help 481 Support for the UniPhier AIDET (ARM Interrupt Detector). 482 483config MESON_IRQ_GPIO 484 tristate "Meson GPIO Interrupt Multiplexer" 485 depends on ARCH_MESON || COMPILE_TEST 486 default ARCH_MESON 487 select IRQ_DOMAIN_HIERARCHY 488 help 489 Support Meson SoC Family GPIO Interrupt Multiplexer 490 491config GOLDFISH_PIC 492 bool "Goldfish programmable interrupt controller" 493 depends on MIPS && (GOLDFISH || COMPILE_TEST) 494 select GENERIC_IRQ_CHIP 495 select IRQ_DOMAIN 496 help 497 Say yes here to enable Goldfish interrupt controller driver used 498 for Goldfish based virtual platforms. 499 500config QCOM_PDC 501 tristate "QCOM PDC" 502 depends on ARCH_QCOM 503 select IRQ_DOMAIN_HIERARCHY 504 help 505 Power Domain Controller driver to manage and configure wakeup 506 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 507 508config QCOM_MPM 509 tristate "QCOM MPM" 510 depends on ARCH_QCOM 511 depends on MAILBOX 512 select IRQ_DOMAIN_HIERARCHY 513 help 514 MSM Power Manager driver to manage and configure wakeup 515 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 516 517config CSKY_MPINTC 518 bool 519 depends on CSKY 520 help 521 Say yes here to enable C-SKY SMP interrupt controller driver used 522 for C-SKY SMP system. 523 In fact it's not mmio map in hardware and it uses ld/st to visit the 524 controller's register inside CPU. 525 526config CSKY_APB_INTC 527 bool "C-SKY APB Interrupt Controller" 528 depends on CSKY 529 help 530 Say yes here to enable C-SKY APB interrupt controller driver used 531 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 532 the controller's register. 533 534config IMX_IRQSTEER 535 bool "i.MX IRQSTEER support" 536 depends on ARCH_MXC || COMPILE_TEST 537 default ARCH_MXC 538 select IRQ_DOMAIN 539 help 540 Support for the i.MX IRQSTEER interrupt multiplexer/remapper. 541 542config IMX_INTMUX 543 bool "i.MX INTMUX support" if COMPILE_TEST 544 default y if ARCH_MXC 545 select IRQ_DOMAIN 546 help 547 Support for the i.MX INTMUX interrupt multiplexer. 548 549config IMX_MU_MSI 550 tristate "i.MX MU used as MSI controller" 551 depends on OF && HAS_IOMEM 552 depends on ARCH_MXC || COMPILE_TEST 553 depends on ARM || ARM64 554 default m if ARCH_MXC 555 select IRQ_DOMAIN 556 select IRQ_DOMAIN_HIERARCHY 557 select GENERIC_MSI_IRQ 558 select IRQ_MSI_LIB 559 help 560 Provide a driver for the i.MX Messaging Unit block used as a 561 CPU-to-CPU MSI controller. This requires a specially crafted DT 562 to make use of this driver. 563 564 If unsure, say N 565 566config LS1X_IRQ 567 bool "Loongson-1 Interrupt Controller" 568 depends on MACH_LOONGSON32 569 default y 570 select IRQ_DOMAIN 571 select GENERIC_IRQ_CHIP 572 help 573 Support for the Loongson-1 platform Interrupt Controller. 574 575config TI_SCI_INTR_IRQCHIP 576 tristate "TI SCI INTR Interrupt Controller" 577 depends on TI_SCI_PROTOCOL 578 depends on ARCH_K3 || COMPILE_TEST 579 select IRQ_DOMAIN_HIERARCHY 580 help 581 This enables the irqchip driver support for K3 Interrupt router 582 over TI System Control Interface available on some new TI's SoCs. 583 If you wish to use interrupt router irq resources managed by the 584 TI System Controller, say Y here. Otherwise, say N. 585 586config TI_SCI_INTA_IRQCHIP 587 tristate "TI SCI INTA Interrupt Controller" 588 depends on TI_SCI_PROTOCOL 589 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 590 select IRQ_DOMAIN_HIERARCHY 591 select TI_SCI_INTA_MSI_DOMAIN 592 help 593 This enables the irqchip driver support for K3 Interrupt aggregator 594 over TI System Control Interface available on some new TI's SoCs. 595 If you wish to use interrupt aggregator irq resources managed by the 596 TI System Controller, say Y here. Otherwise, say N. 597 598config TI_PRUSS_INTC 599 tristate 600 depends on TI_PRUSS 601 default TI_PRUSS 602 select IRQ_DOMAIN 603 help 604 This enables support for the PRU-ICSS Local Interrupt Controller 605 present within a PRU-ICSS subsystem present on various TI SoCs. 606 The PRUSS INTC enables various interrupts to be routed to multiple 607 different processors within the SoC. 608 609config RISCV_INTC 610 bool 611 depends on RISCV 612 select IRQ_DOMAIN_HIERARCHY 613 614config RISCV_APLIC 615 bool 616 depends on RISCV 617 select IRQ_DOMAIN_HIERARCHY 618 619config RISCV_APLIC_MSI 620 bool 621 depends on RISCV_APLIC 622 select GENERIC_MSI_IRQ 623 default RISCV_APLIC 624 625config RISCV_IMSIC 626 bool 627 depends on RISCV 628 select IRQ_DOMAIN_HIERARCHY 629 select GENERIC_IRQ_MATRIX_ALLOCATOR 630 select GENERIC_MSI_IRQ 631 select IRQ_MSI_LIB 632 633config RISCV_RPMI_SYSMSI 634 bool 635 depends on RISCV && MAILBOX 636 select IRQ_DOMAIN_HIERARCHY 637 select GENERIC_MSI_IRQ 638 default RISCV 639 640config SIFIVE_PLIC 641 bool 642 depends on RISCV 643 select IRQ_DOMAIN_HIERARCHY 644 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 645 646config STARFIVE_JH8100_INTC 647 bool "StarFive JH8100 External Interrupt Controller" 648 depends on ARCH_STARFIVE || COMPILE_TEST 649 default ARCH_STARFIVE 650 select IRQ_DOMAIN_HIERARCHY 651 help 652 This enables support for the INTC chip found in StarFive JH8100 653 SoC. 654 655 If you don't know what to do here, say Y. 656 657config ACLINT_SSWI 658 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 659 depends on RISCV 660 depends on SMP 661 select IRQ_DOMAIN_HIERARCHY 662 select GENERIC_IRQ_IPI_MUX 663 help 664 This enables support for variants of the RISC-V ACLINT-SSWI device. 665 Supported variants are: 666 - T-HEAD, with compatible "thead,c900-aclint-sswi" 667 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 668 669 If you don't know what to do here, say Y. 670 671# Backwards compatibility so oldconfig does not drop it. 672config THEAD_C900_ACLINT_SSWI 673 bool 674 select ACLINT_SSWI 675 676config EXYNOS_IRQ_COMBINER 677 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 678 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 679 help 680 Say yes here to add support for the IRQ combiner devices embedded 681 in Samsung Exynos chips. 682 683config IRQ_LOONGARCH_CPU 684 bool 685 select GENERIC_IRQ_CHIP 686 select IRQ_DOMAIN 687 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 688 select LOONGSON_HTVEC 689 select LOONGSON_LIOINTC 690 select LOONGSON_EIOINTC 691 select LOONGSON_PCH_PIC 692 select LOONGSON_PCH_MSI 693 select LOONGSON_PCH_LPC 694 help 695 Support for the LoongArch CPU Interrupt Controller. For details of 696 irq chip hierarchy on LoongArch platforms please read the document 697 Documentation/arch/loongarch/irq-chip-model.rst. 698 699config LOONGSON_LIOINTC 700 bool "Loongson Local I/O Interrupt Controller" 701 depends on MACH_LOONGSON64 702 default y 703 select IRQ_DOMAIN 704 select GENERIC_IRQ_CHIP 705 help 706 Support for the Loongson Local I/O Interrupt Controller. 707 708config LOONGSON_EIOINTC 709 bool "Loongson Extend I/O Interrupt Controller" 710 depends on LOONGARCH 711 depends on MACH_LOONGSON64 712 default MACH_LOONGSON64 713 select IRQ_DOMAIN_HIERARCHY 714 select GENERIC_IRQ_CHIP 715 help 716 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 717 718config LOONGSON_HTPIC 719 bool "Loongson3 HyperTransport PIC Controller" 720 depends on MACH_LOONGSON64 && MIPS 721 default y 722 select IRQ_DOMAIN 723 select GENERIC_IRQ_CHIP 724 help 725 Support for the Loongson-3 HyperTransport PIC Controller. 726 727config LOONGSON_HTVEC 728 bool "Loongson HyperTransport Interrupt Vector Controller" 729 depends on MACH_LOONGSON64 730 default MACH_LOONGSON64 731 select IRQ_DOMAIN_HIERARCHY 732 help 733 Support for the Loongson HyperTransport Interrupt Vector Controller. 734 735config LOONGSON_PCH_PIC 736 bool "Loongson PCH PIC Controller" 737 depends on MACH_LOONGSON64 738 default MACH_LOONGSON64 739 select IRQ_DOMAIN_HIERARCHY 740 select IRQ_FASTEOI_HIERARCHY_HANDLERS 741 help 742 Support for the Loongson PCH PIC Controller. 743 744config LOONGSON_PCH_MSI 745 bool "Loongson PCH MSI Controller" 746 depends on MACH_LOONGSON64 747 depends on PCI 748 default MACH_LOONGSON64 749 select IRQ_DOMAIN_HIERARCHY 750 select IRQ_MSI_LIB 751 select PCI_MSI 752 help 753 Support for the Loongson PCH MSI Controller. 754 755config LOONGSON_PCH_LPC 756 bool "Loongson PCH LPC Controller" 757 depends on LOONGARCH 758 depends on MACH_LOONGSON64 759 default MACH_LOONGSON64 760 select IRQ_DOMAIN_HIERARCHY 761 help 762 Support for the Loongson PCH LPC Controller. 763 764config MST_IRQ 765 bool "MStar Interrupt Controller" 766 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 767 default ARCH_MEDIATEK 768 select IRQ_DOMAIN 769 select IRQ_DOMAIN_HIERARCHY 770 help 771 Support MStar Interrupt Controller. 772 773config WPCM450_AIC 774 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 775 depends on ARCH_WPCM450 776 help 777 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 778 779config IRQ_IDT3243X 780 bool 781 select GENERIC_IRQ_CHIP 782 select IRQ_DOMAIN 783 784config APPLE_AIC 785 bool "Apple Interrupt Controller (AIC)" 786 depends on ARM64 787 depends on ARCH_APPLE || COMPILE_TEST 788 select GENERIC_IRQ_IPI_MUX 789 help 790 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 791 such as the M1. 792 793config MCHP_EIC 794 bool "Microchip External Interrupt Controller" 795 depends on ARCH_AT91 || COMPILE_TEST 796 select IRQ_DOMAIN 797 select IRQ_DOMAIN_HIERARCHY 798 help 799 Support for Microchip External Interrupt Controller. 800 801config SOPHGO_SG2042_MSI 802 bool "Sophgo SG2042 MSI Controller" 803 depends on ARCH_SOPHGO || COMPILE_TEST 804 depends on PCI 805 select IRQ_DOMAIN_HIERARCHY 806 select IRQ_MSI_LIB 807 select PCI_MSI 808 help 809 Support for the Sophgo SG2042 MSI Controller. 810 This on-chip interrupt controller enables MSI sources to be 811 routed to the primary PLIC controller on SoC. 812 813config SUNPLUS_SP7021_INTC 814 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 815 default SOC_SP7021 816 help 817 Support for the Sunplus SP7021 Interrupt Controller IP core. 818 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 819 chained controller, routing all interrupt source in P-Chip to 820 the primary controller on C-Chip. 821 822endmenu