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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
4 * - BMI088
5 * - BMI085
6 * - BMI090L
7 *
8 * Copyright (c) 2018-2021, Topic Embedded Products
9 */
10
11#include <linux/bitfield.h>
12#include <linux/delay.h>
13#include <linux/iio/iio.h>
14#include <linux/iio/sysfs.h>
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20#include <linux/slab.h>
21#include <linux/unaligned.h>
22
23#include "bmi088-accel.h"
24
25#define BMI088_ACCEL_REG_CHIP_ID 0x00
26#define BMI088_ACCEL_REG_ERROR 0x02
27
28#define BMI088_ACCEL_REG_INT_STATUS 0x1D
29#define BMI088_ACCEL_INT_STATUS_BIT_DRDY BIT(7)
30
31#define BMI088_ACCEL_REG_RESET 0x7E
32#define BMI088_ACCEL_RESET_VAL 0xB6
33
34#define BMI088_ACCEL_REG_PWR_CTRL 0x7D
35#define BMI088_ACCEL_REG_PWR_CONF 0x7C
36
37#define BMI088_ACCEL_REG_INT_MAP_DATA 0x58
38#define BMI088_ACCEL_INT_MAP_DATA_BIT_INT1_DRDY BIT(2)
39#define BMI088_ACCEL_INT_MAP_DATA_BIT_INT2_FWM BIT(5)
40
41#define BMI088_ACCEL_REG_INT1_IO_CONF 0x53
42#define BMI088_ACCEL_INT1_IO_CONF_BIT_ENABLE_OUT BIT(3)
43#define BMI088_ACCEL_INT1_IO_CONF_BIT_LVL BIT(1)
44
45#define BMI088_ACCEL_REG_INT2_IO_CONF 0x54
46#define BMI088_ACCEL_INT2_IO_CONF_BIT_ENABLE_OUT BIT(3)
47#define BMI088_ACCEL_INT2_IO_CONF_BIT_LVL BIT(1)
48
49#define BMI088_ACCEL_REG_ACC_CONF 0x40
50#define BMI088_ACCEL_MODE_ODR_MASK 0x0f
51
52#define BMI088_ACCEL_REG_ACC_RANGE 0x41
53#define BMI088_ACCEL_RANGE_3G 0x00
54#define BMI088_ACCEL_RANGE_6G 0x01
55#define BMI088_ACCEL_RANGE_12G 0x02
56#define BMI088_ACCEL_RANGE_24G 0x03
57
58#define BMI088_ACCEL_REG_TEMP 0x22
59#define BMI088_ACCEL_REG_TEMP_SHIFT 5
60#define BMI088_ACCEL_TEMP_UNIT 125
61#define BMI088_ACCEL_TEMP_OFFSET 23000
62
63#define BMI088_ACCEL_REG_XOUT_L 0x12
64#define BMI088_ACCEL_AXIS_TO_REG(axis) \
65 (BMI088_ACCEL_REG_XOUT_L + (axis * 2))
66
67#define BMI088_ACCEL_MAX_STARTUP_TIME_US 1000
68#define BMI088_AUTO_SUSPEND_DELAY_MS 2000
69
70#define BMI088_ACCEL_REG_FIFO_STATUS 0x0E
71#define BMI088_ACCEL_REG_FIFO_CONFIG0 0x48
72#define BMI088_ACCEL_REG_FIFO_CONFIG1 0x49
73#define BMI088_ACCEL_REG_FIFO_DATA 0x3F
74#define BMI088_ACCEL_FIFO_LENGTH 100
75
76#define BMI088_ACCEL_FIFO_MODE_FIFO 0x40
77#define BMI088_ACCEL_FIFO_MODE_STREAM 0x80
78
79#define BMIO088_ACCEL_ACC_RANGE_MSK GENMASK(1, 0)
80
81enum bmi088_accel_axis {
82 AXIS_X,
83 AXIS_Y,
84 AXIS_Z,
85};
86
87static const int bmi088_sample_freqs[] = {
88 12, 500000,
89 25, 0,
90 50, 0,
91 100, 0,
92 200, 0,
93 400, 0,
94 800, 0,
95 1600, 0,
96};
97
98/* Available OSR (over sampling rate) sets the 3dB cut-off frequency */
99enum bmi088_osr_modes {
100 BMI088_ACCEL_MODE_OSR_NORMAL = 0xA,
101 BMI088_ACCEL_MODE_OSR_2 = 0x9,
102 BMI088_ACCEL_MODE_OSR_4 = 0x8,
103};
104
105/* Available ODR (output data rates) in Hz */
106enum bmi088_odr_modes {
107 BMI088_ACCEL_MODE_ODR_12_5 = 0x5,
108 BMI088_ACCEL_MODE_ODR_25 = 0x6,
109 BMI088_ACCEL_MODE_ODR_50 = 0x7,
110 BMI088_ACCEL_MODE_ODR_100 = 0x8,
111 BMI088_ACCEL_MODE_ODR_200 = 0x9,
112 BMI088_ACCEL_MODE_ODR_400 = 0xa,
113 BMI088_ACCEL_MODE_ODR_800 = 0xb,
114 BMI088_ACCEL_MODE_ODR_1600 = 0xc,
115};
116
117struct bmi088_accel_chip_info {
118 const char *name;
119 u8 chip_id;
120 const struct iio_chan_spec *channels;
121 int num_channels;
122 const int scale_table[4][2];
123};
124
125struct bmi088_accel_data {
126 struct regmap *regmap;
127 const struct bmi088_accel_chip_info *chip_info;
128 u8 buffer[2] __aligned(IIO_DMA_MINALIGN); /* shared DMA safe buffer */
129};
130
131static const struct regmap_range bmi088_volatile_ranges[] = {
132 /* All registers below 0x40 are volatile, except the CHIP ID. */
133 regmap_reg_range(BMI088_ACCEL_REG_ERROR, 0x3f),
134 /* Mark the RESET as volatile too, it is self-clearing */
135 regmap_reg_range(BMI088_ACCEL_REG_RESET, BMI088_ACCEL_REG_RESET),
136};
137
138static const struct regmap_access_table bmi088_volatile_table = {
139 .yes_ranges = bmi088_volatile_ranges,
140 .n_yes_ranges = ARRAY_SIZE(bmi088_volatile_ranges),
141};
142
143const struct regmap_config bmi088_regmap_conf = {
144 .reg_bits = 8,
145 .val_bits = 8,
146 .max_register = 0x7E,
147 .volatile_table = &bmi088_volatile_table,
148 .cache_type = REGCACHE_MAPLE,
149};
150EXPORT_SYMBOL_NS_GPL(bmi088_regmap_conf, "IIO_BMI088");
151
152static int bmi088_accel_power_up(struct bmi088_accel_data *data)
153{
154 int ret;
155
156 /* Enable accelerometer and temperature sensor */
157 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x4);
158 if (ret)
159 return ret;
160
161 /* Datasheet recommends to wait at least 5ms before communication */
162 usleep_range(5000, 6000);
163
164 /* Disable suspend mode */
165 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x0);
166 if (ret)
167 return ret;
168
169 /* Recommended at least 1ms before further communication */
170 usleep_range(1000, 1200);
171
172 return 0;
173}
174
175static int bmi088_accel_power_down(struct bmi088_accel_data *data)
176{
177 int ret;
178
179 /* Enable suspend mode */
180 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x3);
181 if (ret)
182 return ret;
183
184 /* Recommended at least 1ms before further communication */
185 usleep_range(1000, 1200);
186
187 /* Disable accelerometer and temperature sensor */
188 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x0);
189 if (ret)
190 return ret;
191
192 /* Datasheet recommends to wait at least 5ms before communication */
193 usleep_range(5000, 6000);
194
195 return 0;
196}
197
198static int bmi088_accel_get_sample_freq(struct bmi088_accel_data *data,
199 int *val, int *val2)
200{
201 unsigned int value;
202 int ret;
203
204 ret = regmap_read(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
205 &value);
206 if (ret)
207 return ret;
208
209 value &= BMI088_ACCEL_MODE_ODR_MASK;
210 value -= BMI088_ACCEL_MODE_ODR_12_5;
211 value <<= 1;
212
213 if (value >= ARRAY_SIZE(bmi088_sample_freqs) - 1)
214 return -EINVAL;
215
216 *val = bmi088_sample_freqs[value];
217 *val2 = bmi088_sample_freqs[value + 1];
218
219 return IIO_VAL_INT_PLUS_MICRO;
220}
221
222static int bmi088_accel_set_sample_freq(struct bmi088_accel_data *data, int val)
223{
224 unsigned int regval;
225 int index = 0;
226
227 while (index < ARRAY_SIZE(bmi088_sample_freqs) &&
228 bmi088_sample_freqs[index] != val)
229 index += 2;
230
231 if (index >= ARRAY_SIZE(bmi088_sample_freqs))
232 return -EINVAL;
233
234 regval = (index >> 1) + BMI088_ACCEL_MODE_ODR_12_5;
235
236 return regmap_update_bits(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
237 BMI088_ACCEL_MODE_ODR_MASK, regval);
238}
239
240static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2)
241{
242 unsigned int i;
243
244 for (i = 0; i < 4; i++)
245 if (val == data->chip_info->scale_table[i][0] &&
246 val2 == data->chip_info->scale_table[i][1])
247 break;
248
249 if (i == 4)
250 return -EINVAL;
251
252 return regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE, i);
253}
254
255static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val)
256{
257 int ret;
258 s16 temp;
259
260 ret = regmap_bulk_read(data->regmap, BMI088_ACCEL_REG_TEMP,
261 &data->buffer, sizeof(__be16));
262 if (ret)
263 return ret;
264
265 /* data->buffer is cacheline aligned */
266 temp = be16_to_cpu(*(__be16 *)data->buffer);
267
268 *val = temp >> BMI088_ACCEL_REG_TEMP_SHIFT;
269
270 return IIO_VAL_INT;
271}
272
273static int bmi088_accel_get_axis(struct bmi088_accel_data *data,
274 struct iio_chan_spec const *chan,
275 int *val)
276{
277 int ret;
278 s16 raw_val;
279
280 ret = regmap_bulk_read(data->regmap,
281 BMI088_ACCEL_AXIS_TO_REG(chan->scan_index),
282 data->buffer, sizeof(__le16));
283 if (ret)
284 return ret;
285
286 raw_val = le16_to_cpu(*(__le16 *)data->buffer);
287 *val = raw_val;
288
289 return IIO_VAL_INT;
290}
291
292static int bmi088_accel_read_raw(struct iio_dev *indio_dev,
293 struct iio_chan_spec const *chan,
294 int *val, int *val2, long mask)
295{
296 struct bmi088_accel_data *data = iio_priv(indio_dev);
297 struct device *dev = regmap_get_device(data->regmap);
298 int ret;
299 int reg;
300
301 switch (mask) {
302 case IIO_CHAN_INFO_RAW:
303 switch (chan->type) {
304 case IIO_TEMP:
305 ret = pm_runtime_resume_and_get(dev);
306 if (ret)
307 return ret;
308
309 ret = bmi088_accel_get_temp(data, val);
310 goto out_read_raw_pm_put;
311 case IIO_ACCEL:
312 ret = pm_runtime_resume_and_get(dev);
313 if (ret)
314 return ret;
315
316 if (!iio_device_claim_direct(indio_dev)) {
317 ret = -EBUSY;
318 goto out_read_raw_pm_put;
319 }
320
321 ret = bmi088_accel_get_axis(data, chan, val);
322 iio_device_release_direct(indio_dev);
323 if (!ret)
324 ret = IIO_VAL_INT;
325
326 goto out_read_raw_pm_put;
327 default:
328 return -EINVAL;
329 }
330 case IIO_CHAN_INFO_OFFSET:
331 switch (chan->type) {
332 case IIO_TEMP:
333 /* Offset applies before scale */
334 *val = BMI088_ACCEL_TEMP_OFFSET/BMI088_ACCEL_TEMP_UNIT;
335 return IIO_VAL_INT;
336 default:
337 return -EINVAL;
338 }
339 case IIO_CHAN_INFO_SCALE:
340 switch (chan->type) {
341 case IIO_TEMP:
342 /* 0.125 degrees per LSB */
343 *val = BMI088_ACCEL_TEMP_UNIT;
344 return IIO_VAL_INT;
345 case IIO_ACCEL:
346 ret = pm_runtime_resume_and_get(dev);
347 if (ret)
348 return ret;
349
350 ret = regmap_read(data->regmap,
351 BMI088_ACCEL_REG_ACC_RANGE, ®);
352 if (ret)
353 goto out_read_raw_pm_put;
354
355 reg = FIELD_GET(BMIO088_ACCEL_ACC_RANGE_MSK, reg);
356 *val = data->chip_info->scale_table[reg][0];
357 *val2 = data->chip_info->scale_table[reg][1];
358 ret = IIO_VAL_INT_PLUS_MICRO;
359
360 goto out_read_raw_pm_put;
361 default:
362 return -EINVAL;
363 }
364 case IIO_CHAN_INFO_SAMP_FREQ:
365 ret = pm_runtime_resume_and_get(dev);
366 if (ret)
367 return ret;
368
369 ret = bmi088_accel_get_sample_freq(data, val, val2);
370 goto out_read_raw_pm_put;
371 default:
372 break;
373 }
374
375 return -EINVAL;
376
377out_read_raw_pm_put:
378 pm_runtime_put_autosuspend(dev);
379
380 return ret;
381}
382
383static int bmi088_accel_read_avail(struct iio_dev *indio_dev,
384 struct iio_chan_spec const *chan,
385 const int **vals, int *type, int *length,
386 long mask)
387{
388 struct bmi088_accel_data *data = iio_priv(indio_dev);
389
390 switch (mask) {
391 case IIO_CHAN_INFO_SCALE:
392 *vals = (const int *)data->chip_info->scale_table;
393 *length = 8;
394 *type = IIO_VAL_INT_PLUS_MICRO;
395 return IIO_AVAIL_LIST;
396 case IIO_CHAN_INFO_SAMP_FREQ:
397 *type = IIO_VAL_INT_PLUS_MICRO;
398 *vals = bmi088_sample_freqs;
399 *length = ARRAY_SIZE(bmi088_sample_freqs);
400 return IIO_AVAIL_LIST;
401 default:
402 return -EINVAL;
403 }
404}
405
406static int bmi088_accel_write_raw(struct iio_dev *indio_dev,
407 struct iio_chan_spec const *chan,
408 int val, int val2, long mask)
409{
410 struct bmi088_accel_data *data = iio_priv(indio_dev);
411 struct device *dev = regmap_get_device(data->regmap);
412 int ret;
413
414 switch (mask) {
415 case IIO_CHAN_INFO_SCALE:
416 ret = pm_runtime_resume_and_get(dev);
417 if (ret)
418 return ret;
419
420 ret = bmi088_accel_set_scale(data, val, val2);
421 pm_runtime_put_autosuspend(dev);
422 return ret;
423 case IIO_CHAN_INFO_SAMP_FREQ:
424 ret = pm_runtime_resume_and_get(dev);
425 if (ret)
426 return ret;
427
428 ret = bmi088_accel_set_sample_freq(data, val);
429 pm_runtime_put_autosuspend(dev);
430 return ret;
431 default:
432 return -EINVAL;
433 }
434}
435
436#define BMI088_ACCEL_CHANNEL(_axis) { \
437 .type = IIO_ACCEL, \
438 .modified = 1, \
439 .channel2 = IIO_MOD_##_axis, \
440 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
441 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
442 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
443 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
444 BIT(IIO_CHAN_INFO_SCALE), \
445 .scan_index = AXIS_##_axis, \
446}
447
448static const struct iio_chan_spec bmi088_accel_channels[] = {
449 {
450 .type = IIO_TEMP,
451 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
452 BIT(IIO_CHAN_INFO_SCALE) |
453 BIT(IIO_CHAN_INFO_OFFSET),
454 .scan_index = -1,
455 },
456 BMI088_ACCEL_CHANNEL(X),
457 BMI088_ACCEL_CHANNEL(Y),
458 BMI088_ACCEL_CHANNEL(Z),
459 IIO_CHAN_SOFT_TIMESTAMP(3),
460};
461
462static const struct bmi088_accel_chip_info bmi088_accel_chip_info_tbl[] = {
463 [BOSCH_BMI085] = {
464 .name = "bmi085-accel",
465 .chip_id = 0x1F,
466 .channels = bmi088_accel_channels,
467 .num_channels = ARRAY_SIZE(bmi088_accel_channels),
468 .scale_table = {{0, 598}, {0, 1196}, {0, 2393}, {0, 4785}},
469 },
470 [BOSCH_BMI088] = {
471 .name = "bmi088-accel",
472 .chip_id = 0x1E,
473 .channels = bmi088_accel_channels,
474 .num_channels = ARRAY_SIZE(bmi088_accel_channels),
475 .scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
476 },
477 [BOSCH_BMI090L] = {
478 .name = "bmi090l-accel",
479 .chip_id = 0x1A,
480 .channels = bmi088_accel_channels,
481 .num_channels = ARRAY_SIZE(bmi088_accel_channels),
482 .scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
483 },
484};
485
486static const struct iio_info bmi088_accel_info = {
487 .read_raw = bmi088_accel_read_raw,
488 .write_raw = bmi088_accel_write_raw,
489 .read_avail = bmi088_accel_read_avail,
490};
491
492static const unsigned long bmi088_accel_scan_masks[] = {
493 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
494 0
495};
496
497static int bmi088_accel_chip_init(struct bmi088_accel_data *data, enum bmi_device_type type)
498{
499 struct device *dev = regmap_get_device(data->regmap);
500 int ret, i;
501 unsigned int val;
502
503 if (type >= BOSCH_UNKNOWN)
504 return -ENODEV;
505
506 /* Do a dummy read to enable SPI interface, won't harm I2C */
507 regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
508
509 /*
510 * Reset chip to get it in a known good state. A delay of 1ms after
511 * reset is required according to the data sheet
512 */
513 ret = regmap_write(data->regmap, BMI088_ACCEL_REG_RESET,
514 BMI088_ACCEL_RESET_VAL);
515 if (ret)
516 return ret;
517
518 usleep_range(1000, 2000);
519
520 /* Do a dummy read again after a reset to enable the SPI interface */
521 regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
522
523 /* Read chip ID */
524 ret = regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
525 if (ret) {
526 dev_err(dev, "Error: Reading chip id\n");
527 return ret;
528 }
529
530 /* Validate chip ID */
531 for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++)
532 if (bmi088_accel_chip_info_tbl[i].chip_id == val)
533 break;
534
535 if (i == ARRAY_SIZE(bmi088_accel_chip_info_tbl))
536 data->chip_info = &bmi088_accel_chip_info_tbl[type];
537 else
538 data->chip_info = &bmi088_accel_chip_info_tbl[i];
539
540 if (i != type)
541 dev_warn(dev, "unexpected chip id 0x%X\n", val);
542
543 return 0;
544}
545
546int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap,
547 int irq, enum bmi_device_type type)
548{
549 struct bmi088_accel_data *data;
550 struct iio_dev *indio_dev;
551 int ret;
552
553 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
554 if (!indio_dev)
555 return -ENOMEM;
556
557 data = iio_priv(indio_dev);
558 dev_set_drvdata(dev, indio_dev);
559
560 data->regmap = regmap;
561
562 ret = bmi088_accel_chip_init(data, type);
563 if (ret)
564 return ret;
565
566 indio_dev->channels = data->chip_info->channels;
567 indio_dev->num_channels = data->chip_info->num_channels;
568 indio_dev->name = data->chip_info->name;
569 indio_dev->available_scan_masks = bmi088_accel_scan_masks;
570 indio_dev->modes = INDIO_DIRECT_MODE;
571 indio_dev->info = &bmi088_accel_info;
572
573 /* Enable runtime PM */
574 pm_runtime_get_noresume(dev);
575 pm_runtime_set_suspended(dev);
576 pm_runtime_enable(dev);
577 /* We need ~6ms to startup, so set the delay to 6 seconds */
578 pm_runtime_set_autosuspend_delay(dev, 6000);
579 pm_runtime_use_autosuspend(dev);
580 pm_runtime_put(dev);
581
582 ret = iio_device_register(indio_dev);
583 if (ret)
584 dev_err(dev, "Unable to register iio device\n");
585
586 return ret;
587}
588EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_probe, "IIO_BMI088");
589
590
591void bmi088_accel_core_remove(struct device *dev)
592{
593 struct iio_dev *indio_dev = dev_get_drvdata(dev);
594 struct bmi088_accel_data *data = iio_priv(indio_dev);
595
596 iio_device_unregister(indio_dev);
597
598 pm_runtime_disable(dev);
599 pm_runtime_set_suspended(dev);
600 bmi088_accel_power_down(data);
601}
602EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_remove, "IIO_BMI088");
603
604static int bmi088_accel_runtime_suspend(struct device *dev)
605{
606 struct iio_dev *indio_dev = dev_get_drvdata(dev);
607 struct bmi088_accel_data *data = iio_priv(indio_dev);
608
609 return bmi088_accel_power_down(data);
610}
611
612static int bmi088_accel_runtime_resume(struct device *dev)
613{
614 struct iio_dev *indio_dev = dev_get_drvdata(dev);
615 struct bmi088_accel_data *data = iio_priv(indio_dev);
616
617 return bmi088_accel_power_up(data);
618}
619
620EXPORT_NS_GPL_RUNTIME_DEV_PM_OPS(bmi088_accel_pm_ops,
621 bmi088_accel_runtime_suspend,
622 bmi088_accel_runtime_resume, NULL,
623 IIO_BMI088);
624
625MODULE_AUTHOR("Niek van Agt <niek.van.agt@topicproducts.com>");
626MODULE_LICENSE("GPL v2");
627MODULE_DESCRIPTION("BMI088 accelerometer driver (core)");