Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Broadcom
4 */
5
6/**
7 * DOC: VC4 SDTV module
8 *
9 * The VEC encoder generates PAL or NTSC composite video output.
10 *
11 * TV mode selection is done by an atomic property on the encoder,
12 * because a drm_mode_modeinfo is insufficient to distinguish between
13 * PAL and PAL-M or NTSC and NTSC-J.
14 */
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_drv.h>
18#include <drm/drm_edid.h>
19#include <drm/drm_panel.h>
20#include <drm/drm_print.h>
21#include <drm/drm_probe_helper.h>
22#include <drm/drm_simple_kms_helper.h>
23#include <linux/clk.h>
24#include <linux/component.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
28
29#include "vc4_drv.h"
30#include "vc4_regs.h"
31
32/* WSE Registers */
33#define VEC_WSE_RESET 0xc0
34
35#define VEC_WSE_CONTROL 0xc4
36#define VEC_WSE_WSS_ENABLE BIT(7)
37
38#define VEC_WSE_WSS_DATA 0xc8
39#define VEC_WSE_VPS_DATA1 0xcc
40#define VEC_WSE_VPS_CONTROL 0xd0
41
42/* VEC Registers */
43#define VEC_REVID 0x100
44
45#define VEC_CONFIG0 0x104
46#define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26)
47#define VEC_CONFIG0_YDEL(x) ((x) << 26)
48#define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24)
49#define VEC_CONFIG0_CDEL(x) ((x) << 24)
50#define VEC_CONFIG0_SECAM_STD BIT(21)
51#define VEC_CONFIG0_PBPR_FIL BIT(18)
52#define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)
53#define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16)
54#define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16)
55#define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16)
56#define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16)
57#define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13)
58#define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13)
59#define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13)
60#define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13)
61#define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13)
62#define VEC_CONFIG0_CHRBW1 BIT(11)
63#define VEC_CONFIG0_CHRBW0 BIT(10)
64#define VEC_CONFIG0_SYNCDIS BIT(9)
65#define VEC_CONFIG0_BURDIS BIT(8)
66#define VEC_CONFIG0_CHRDIS BIT(7)
67#define VEC_CONFIG0_PDEN BIT(6)
68#define VEC_CONFIG0_YCDELAY BIT(4)
69#define VEC_CONFIG0_RAMPEN BIT(2)
70#define VEC_CONFIG0_YCDIS BIT(2)
71#define VEC_CONFIG0_STD_MASK GENMASK(1, 0)
72#define VEC_CONFIG0_NTSC_STD 0
73#define VEC_CONFIG0_PAL_BDGHI_STD 1
74#define VEC_CONFIG0_PAL_M_STD 2
75#define VEC_CONFIG0_PAL_N_STD 3
76
77#define VEC_SCHPH 0x108
78#define VEC_SOFT_RESET 0x10c
79#define VEC_CLMP0_START 0x144
80#define VEC_CLMP0_END 0x148
81
82/*
83 * These set the color subcarrier frequency
84 * if VEC_CONFIG1_CUSTOM_FREQ is enabled.
85 *
86 * VEC_FREQ1_0 contains the most significant 16-bit half-word,
87 * VEC_FREQ3_2 contains the least significant 16-bit half-word.
88 * 0x80000000 seems to be equivalent to the pixel clock
89 * (which itself is the VEC clock divided by 8).
90 *
91 * Reference values (with the default pixel clock of 13.5 MHz):
92 *
93 * NTSC (3579545.[45] Hz) - 0x21F07C1F
94 * PAL (4433618.75 Hz) - 0x2A098ACB
95 * PAL-M (3575611.[888111] Hz) - 0x21E6EFE3
96 * PAL-N (3582056.25 Hz) - 0x21F69446
97 *
98 * NOTE: For SECAM, it is used as the Dr center frequency,
99 * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;
100 * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.
101 */
102#define VEC_FREQ3_2 0x180
103#define VEC_FREQ1_0 0x184
104
105#define VEC_CONFIG1 0x188
106#define VEC_CONFIG_VEC_RESYNC_OFF BIT(18)
107#define VEC_CONFIG_RGB219 BIT(17)
108#define VEC_CONFIG_CBAR_EN BIT(16)
109#define VEC_CONFIG_TC_OBB BIT(15)
110#define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10)
111#define VEC_CONFIG1_C_Y_CVBS (0 << 10)
112#define VEC_CONFIG1_CVBS_Y_C (1 << 10)
113#define VEC_CONFIG1_PR_Y_PB (2 << 10)
114#define VEC_CONFIG1_RGB (4 << 10)
115#define VEC_CONFIG1_Y_C_CVBS (5 << 10)
116#define VEC_CONFIG1_C_CVBS_Y (6 << 10)
117#define VEC_CONFIG1_C_CVBS_CVBS (7 << 10)
118#define VEC_CONFIG1_DIS_CHR BIT(9)
119#define VEC_CONFIG1_DIS_LUMA BIT(8)
120#define VEC_CONFIG1_YCBCR_IN BIT(6)
121#define VEC_CONFIG1_DITHER_TYPE_LFSR 0
122#define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)
123#define VEC_CONFIG1_DITHER_EN BIT(4)
124#define VEC_CONFIG1_CYDELAY BIT(3)
125#define VEC_CONFIG1_LUMADIS BIT(2)
126#define VEC_CONFIG1_COMPDIS BIT(1)
127#define VEC_CONFIG1_CUSTOM_FREQ BIT(0)
128
129#define VEC_CONFIG2 0x18c
130#define VEC_CONFIG2_PROG_SCAN BIT(15)
131#define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12)
132#define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12)
133#define VEC_CONFIG2_PBPR_EN BIT(10)
134#define VEC_CONFIG2_UV_DIG_DIS BIT(6)
135#define VEC_CONFIG2_RGB_DIG_DIS BIT(5)
136#define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2)
137#define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2)
138#define VEC_CONFIG2_TMUX_RG_COMP (1 << 2)
139#define VEC_CONFIG2_TMUX_UV_YC (2 << 2)
140#define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2)
141
142#define VEC_INTERRUPT_CONTROL 0x190
143#define VEC_INTERRUPT_STATUS 0x194
144
145/*
146 * Db center frequency for SECAM; the clock for this is the same as for
147 * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.
148 *
149 * This is specified as 4250000 Hz, which corresponds to 0x284BDA13.
150 * That is also the default value, so no need to set it explicitly.
151 */
152#define VEC_FCW_SECAM_B 0x198
153#define VEC_SECAM_GAIN_VAL 0x19c
154
155#define VEC_CONFIG3 0x1a0
156#define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0)
157#define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)
158#define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1)
159
160#define VEC_STATUS0 0x200
161#define VEC_MASK0 0x204
162
163#define VEC_CFG 0x208
164#define VEC_CFG_SG_MODE_MASK GENMASK(6, 5)
165#define VEC_CFG_SG_MODE(x) ((x) << 5)
166#define VEC_CFG_SG_EN BIT(4)
167#define VEC_CFG_VEC_EN BIT(3)
168#define VEC_CFG_MB_EN BIT(2)
169#define VEC_CFG_ENABLE BIT(1)
170#define VEC_CFG_TB_EN BIT(0)
171
172#define VEC_DAC_TEST 0x20c
173
174#define VEC_DAC_CONFIG 0x210
175#define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)
176#define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16)
177#define VEC_DAC_CONFIG_DAC_CTRL(x) (x)
178
179#define VEC_DAC_MISC 0x214
180#define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16)
181#define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16)
182#define VEC_DAC_MISC_VID_ACT BIT(8)
183#define VEC_DAC_MISC_VCD_PWRDN BIT(6)
184#define VEC_DAC_MISC_BIAS_PWRDN BIT(5)
185#define VEC_DAC_MISC_DAC_PWRDN BIT(2)
186#define VEC_DAC_MISC_LDO_PWRDN BIT(1)
187#define VEC_DAC_MISC_DAC_RST_N BIT(0)
188
189
190struct vc4_vec_variant {
191 u32 dac_config;
192};
193
194/* General VEC hardware state. */
195struct vc4_vec {
196 struct vc4_encoder encoder;
197 struct drm_connector connector;
198
199 struct platform_device *pdev;
200 const struct vc4_vec_variant *variant;
201
202 void __iomem *regs;
203
204 struct clk *clock;
205
206 struct drm_property *legacy_tv_mode_property;
207
208 struct debugfs_regset32 regset;
209};
210
211#define VEC_READ(offset) \
212 ({ \
213 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
214 readl(vec->regs + (offset)); \
215 })
216
217#define VEC_WRITE(offset, val) \
218 do { \
219 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
220 writel(val, vec->regs + (offset)); \
221 } while (0)
222
223#define encoder_to_vc4_vec(_encoder) \
224 container_of_const(_encoder, struct vc4_vec, encoder.base)
225
226#define connector_to_vc4_vec(_connector) \
227 container_of_const(_connector, struct vc4_vec, connector)
228
229enum vc4_vec_tv_mode_id {
230 VC4_VEC_TV_MODE_NTSC,
231 VC4_VEC_TV_MODE_NTSC_J,
232 VC4_VEC_TV_MODE_PAL,
233 VC4_VEC_TV_MODE_PAL_M,
234 VC4_VEC_TV_MODE_NTSC_443,
235 VC4_VEC_TV_MODE_PAL_60,
236 VC4_VEC_TV_MODE_PAL_N,
237 VC4_VEC_TV_MODE_SECAM,
238 VC4_VEC_TV_MODE_MONOCHROME,
239};
240
241struct vc4_vec_tv_mode {
242 unsigned int mode;
243 u16 expected_htotal;
244 u32 config0;
245 u32 config1;
246 u32 custom_freq;
247};
248
249static const struct debugfs_reg32 vec_regs[] = {
250 VC4_REG32(VEC_WSE_CONTROL),
251 VC4_REG32(VEC_WSE_WSS_DATA),
252 VC4_REG32(VEC_WSE_VPS_DATA1),
253 VC4_REG32(VEC_WSE_VPS_CONTROL),
254 VC4_REG32(VEC_REVID),
255 VC4_REG32(VEC_CONFIG0),
256 VC4_REG32(VEC_SCHPH),
257 VC4_REG32(VEC_CLMP0_START),
258 VC4_REG32(VEC_CLMP0_END),
259 VC4_REG32(VEC_FREQ3_2),
260 VC4_REG32(VEC_FREQ1_0),
261 VC4_REG32(VEC_CONFIG1),
262 VC4_REG32(VEC_CONFIG2),
263 VC4_REG32(VEC_INTERRUPT_CONTROL),
264 VC4_REG32(VEC_INTERRUPT_STATUS),
265 VC4_REG32(VEC_FCW_SECAM_B),
266 VC4_REG32(VEC_SECAM_GAIN_VAL),
267 VC4_REG32(VEC_CONFIG3),
268 VC4_REG32(VEC_STATUS0),
269 VC4_REG32(VEC_MASK0),
270 VC4_REG32(VEC_CFG),
271 VC4_REG32(VEC_DAC_TEST),
272 VC4_REG32(VEC_DAC_CONFIG),
273 VC4_REG32(VEC_DAC_MISC),
274};
275
276static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {
277 {
278 .mode = DRM_MODE_TV_MODE_NTSC,
279 .expected_htotal = 858,
280 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,
281 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
282 },
283 {
284 .mode = DRM_MODE_TV_MODE_NTSC_443,
285 .expected_htotal = 858,
286 .config0 = VEC_CONFIG0_NTSC_STD,
287 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
288 .custom_freq = 0x2a098acb,
289 },
290 {
291 .mode = DRM_MODE_TV_MODE_NTSC_J,
292 .expected_htotal = 858,
293 .config0 = VEC_CONFIG0_NTSC_STD,
294 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
295 },
296 {
297 .mode = DRM_MODE_TV_MODE_PAL,
298 .expected_htotal = 864,
299 .config0 = VEC_CONFIG0_PAL_BDGHI_STD,
300 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
301 },
302 {
303 /* PAL-60 */
304 .mode = DRM_MODE_TV_MODE_PAL,
305 .expected_htotal = 858,
306 .config0 = VEC_CONFIG0_PAL_M_STD,
307 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,
308 .custom_freq = 0x2a098acb,
309 },
310 {
311 .mode = DRM_MODE_TV_MODE_PAL_M,
312 .expected_htotal = 858,
313 .config0 = VEC_CONFIG0_PAL_M_STD,
314 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
315 },
316 {
317 .mode = DRM_MODE_TV_MODE_PAL_N,
318 .expected_htotal = 864,
319 .config0 = VEC_CONFIG0_PAL_N_STD,
320 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
321 },
322 {
323 .mode = DRM_MODE_TV_MODE_SECAM,
324 .expected_htotal = 864,
325 .config0 = VEC_CONFIG0_SECAM_STD,
326 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
327 .custom_freq = 0x29c71c72,
328 },
329 {
330 /* 50Hz mono */
331 .mode = DRM_MODE_TV_MODE_MONOCHROME,
332 .expected_htotal = 864,
333 .config0 = VEC_CONFIG0_PAL_BDGHI_STD | VEC_CONFIG0_BURDIS |
334 VEC_CONFIG0_CHRDIS,
335 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
336 },
337 {
338 /* 60Hz mono */
339 .mode = DRM_MODE_TV_MODE_MONOCHROME,
340 .expected_htotal = 858,
341 .config0 = VEC_CONFIG0_PAL_M_STD | VEC_CONFIG0_BURDIS |
342 VEC_CONFIG0_CHRDIS,
343 .config1 = VEC_CONFIG1_C_CVBS_CVBS,
344 },
345};
346
347static inline const struct vc4_vec_tv_mode *
348vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal)
349{
350 unsigned int i;
351
352 for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {
353 const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i];
354
355 if (tv_mode->mode == mode &&
356 tv_mode->expected_htotal == htotal)
357 return tv_mode;
358 }
359
360 return NULL;
361}
362
363static const struct drm_prop_enum_list legacy_tv_mode_names[] = {
364 { VC4_VEC_TV_MODE_NTSC, "NTSC", },
365 { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", },
366 { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },
367 { VC4_VEC_TV_MODE_PAL, "PAL", },
368 { VC4_VEC_TV_MODE_PAL_60, "PAL-60", },
369 { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },
370 { VC4_VEC_TV_MODE_PAL_N, "PAL-N", },
371 { VC4_VEC_TV_MODE_SECAM, "SECAM", },
372 { VC4_VEC_TV_MODE_MONOCHROME, "Mono", },
373};
374
375static enum drm_connector_status
376vc4_vec_connector_detect(struct drm_connector *connector, bool force)
377{
378 return connector_status_unknown;
379}
380
381static void vc4_vec_connector_reset(struct drm_connector *connector)
382{
383 drm_atomic_helper_connector_reset(connector);
384 drm_atomic_helper_connector_tv_reset(connector);
385}
386
387static int
388vc4_vec_connector_set_property(struct drm_connector *connector,
389 struct drm_connector_state *state,
390 struct drm_property *property,
391 uint64_t val)
392{
393 struct vc4_vec *vec = connector_to_vc4_vec(connector);
394
395 if (property != vec->legacy_tv_mode_property)
396 return -EINVAL;
397
398 switch (val) {
399 case VC4_VEC_TV_MODE_NTSC:
400 state->tv.mode = DRM_MODE_TV_MODE_NTSC;
401 break;
402
403 case VC4_VEC_TV_MODE_NTSC_443:
404 state->tv.mode = DRM_MODE_TV_MODE_NTSC_443;
405 break;
406
407 case VC4_VEC_TV_MODE_NTSC_J:
408 state->tv.mode = DRM_MODE_TV_MODE_NTSC_J;
409 break;
410
411 case VC4_VEC_TV_MODE_PAL:
412 case VC4_VEC_TV_MODE_PAL_60:
413 state->tv.mode = DRM_MODE_TV_MODE_PAL;
414 break;
415
416 case VC4_VEC_TV_MODE_PAL_M:
417 state->tv.mode = DRM_MODE_TV_MODE_PAL_M;
418 break;
419
420 case VC4_VEC_TV_MODE_PAL_N:
421 state->tv.mode = DRM_MODE_TV_MODE_PAL_N;
422 break;
423
424 case VC4_VEC_TV_MODE_SECAM:
425 state->tv.mode = DRM_MODE_TV_MODE_SECAM;
426 break;
427
428 case VC4_VEC_TV_MODE_MONOCHROME:
429 state->tv.mode = DRM_MODE_TV_MODE_MONOCHROME;
430 break;
431
432 default:
433 return -EINVAL;
434 }
435
436 return 0;
437}
438
439static int
440vc4_vec_connector_get_property(struct drm_connector *connector,
441 const struct drm_connector_state *state,
442 struct drm_property *property,
443 uint64_t *val)
444{
445 struct vc4_vec *vec = connector_to_vc4_vec(connector);
446
447 if (property != vec->legacy_tv_mode_property)
448 return -EINVAL;
449
450 switch (state->tv.mode) {
451 case DRM_MODE_TV_MODE_NTSC:
452 *val = VC4_VEC_TV_MODE_NTSC;
453 break;
454
455 case DRM_MODE_TV_MODE_NTSC_443:
456 *val = VC4_VEC_TV_MODE_NTSC_443;
457 break;
458
459 case DRM_MODE_TV_MODE_NTSC_J:
460 *val = VC4_VEC_TV_MODE_NTSC_J;
461 break;
462
463 case DRM_MODE_TV_MODE_PAL:
464 *val = VC4_VEC_TV_MODE_PAL;
465 break;
466
467 case DRM_MODE_TV_MODE_PAL_M:
468 *val = VC4_VEC_TV_MODE_PAL_M;
469 break;
470
471 case DRM_MODE_TV_MODE_PAL_N:
472 *val = VC4_VEC_TV_MODE_PAL_N;
473 break;
474
475 case DRM_MODE_TV_MODE_SECAM:
476 *val = VC4_VEC_TV_MODE_SECAM;
477 break;
478
479 case DRM_MODE_TV_MODE_MONOCHROME:
480 *val = VC4_VEC_TV_MODE_MONOCHROME;
481 break;
482
483 default:
484 return -EINVAL;
485 }
486
487 return 0;
488}
489
490static const struct drm_connector_funcs vc4_vec_connector_funcs = {
491 .detect = vc4_vec_connector_detect,
492 .fill_modes = drm_helper_probe_single_connector_modes,
493 .reset = vc4_vec_connector_reset,
494 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
495 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
496 .atomic_get_property = vc4_vec_connector_get_property,
497 .atomic_set_property = vc4_vec_connector_set_property,
498};
499
500static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {
501 .atomic_check = drm_atomic_helper_connector_tv_check,
502 .get_modes = drm_connector_helper_tv_get_modes,
503};
504
505static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec)
506{
507 struct drm_connector *connector = &vec->connector;
508 struct drm_property *prop;
509 int ret;
510
511 connector->interlace_allowed = true;
512
513 ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs,
514 DRM_MODE_CONNECTOR_Composite, NULL);
515 if (ret)
516 return ret;
517
518 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);
519
520 drm_object_attach_property(&connector->base,
521 dev->mode_config.tv_mode_property,
522 DRM_MODE_TV_MODE_NTSC);
523
524 prop = drm_property_create_enum(dev, 0, "mode",
525 legacy_tv_mode_names,
526 ARRAY_SIZE(legacy_tv_mode_names));
527 if (!prop)
528 return -ENOMEM;
529 vec->legacy_tv_mode_property = prop;
530
531 drm_object_attach_property(&connector->base, prop, VC4_VEC_TV_MODE_NTSC);
532
533 drm_connector_attach_tv_margin_properties(connector);
534
535 drm_connector_attach_encoder(connector, &vec->encoder.base);
536
537 return 0;
538}
539
540static void vc4_vec_encoder_disable(struct drm_encoder *encoder,
541 struct drm_atomic_state *state)
542{
543 struct drm_device *drm = encoder->dev;
544 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
545 int idx, ret;
546
547 if (!drm_dev_enter(drm, &idx))
548 return;
549
550 VEC_WRITE(VEC_CFG, 0);
551 VEC_WRITE(VEC_DAC_MISC,
552 VEC_DAC_MISC_VCD_PWRDN |
553 VEC_DAC_MISC_BIAS_PWRDN |
554 VEC_DAC_MISC_DAC_PWRDN |
555 VEC_DAC_MISC_LDO_PWRDN);
556
557 clk_disable_unprepare(vec->clock);
558
559 ret = pm_runtime_put(&vec->pdev->dev);
560 if (ret < 0) {
561 drm_err(drm, "Failed to release power domain: %d\n", ret);
562 goto err_dev_exit;
563 }
564
565 drm_dev_exit(idx);
566 return;
567
568err_dev_exit:
569 drm_dev_exit(idx);
570}
571
572static void vc4_vec_encoder_enable(struct drm_encoder *encoder,
573 struct drm_atomic_state *state)
574{
575 struct drm_device *drm = encoder->dev;
576 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
577 struct drm_connector *connector = &vec->connector;
578 struct drm_connector_state *conn_state =
579 drm_atomic_get_new_connector_state(state, connector);
580 struct drm_display_mode *adjusted_mode =
581 &encoder->crtc->state->adjusted_mode;
582 const struct vc4_vec_tv_mode *tv_mode;
583 int idx, ret;
584
585 if (!drm_dev_enter(drm, &idx))
586 return;
587
588 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode,
589 adjusted_mode->htotal);
590 if (!tv_mode)
591 goto err_dev_exit;
592
593 ret = pm_runtime_resume_and_get(&vec->pdev->dev);
594 if (ret < 0) {
595 drm_err(drm, "Failed to retain power domain: %d\n", ret);
596 goto err_dev_exit;
597 }
598
599 /*
600 * We need to set the clock rate each time we enable the encoder
601 * because there's a chance we share the same parent with the HDMI
602 * clock, and both drivers are requesting different rates.
603 * The good news is, these 2 encoders cannot be enabled at the same
604 * time, thus preventing incompatible rate requests.
605 */
606 ret = clk_set_rate(vec->clock, 108000000);
607 if (ret) {
608 drm_err(drm, "Failed to set clock rate: %d\n", ret);
609 goto err_put_runtime_pm;
610 }
611
612 ret = clk_prepare_enable(vec->clock);
613 if (ret) {
614 drm_err(drm, "Failed to turn on core clock: %d\n", ret);
615 goto err_put_runtime_pm;
616 }
617
618 /* Reset the different blocks */
619 VEC_WRITE(VEC_WSE_RESET, 1);
620 VEC_WRITE(VEC_SOFT_RESET, 1);
621
622 /* Disable the CGSM-A and WSE blocks */
623 VEC_WRITE(VEC_WSE_CONTROL, 0);
624
625 /* Write config common to all modes. */
626
627 /*
628 * Color subcarrier phase: phase = 360 * SCHPH / 256.
629 * 0x28 <=> 39.375 deg.
630 */
631 VEC_WRITE(VEC_SCHPH, 0x28);
632
633 /*
634 * Reset to default values.
635 */
636 VEC_WRITE(VEC_CLMP0_START, 0xac);
637 VEC_WRITE(VEC_CLMP0_END, 0xec);
638 VEC_WRITE(VEC_CONFIG2,
639 VEC_CONFIG2_UV_DIG_DIS |
640 VEC_CONFIG2_RGB_DIG_DIS |
641 ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN));
642 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);
643 VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config);
644
645 /* Mask all interrupts. */
646 VEC_WRITE(VEC_MASK0, 0);
647
648 VEC_WRITE(VEC_CONFIG0, tv_mode->config0);
649 VEC_WRITE(VEC_CONFIG1, tv_mode->config1);
650
651 if (tv_mode->custom_freq) {
652 VEC_WRITE(VEC_FREQ3_2,
653 (tv_mode->custom_freq >> 16) & 0xffff);
654 VEC_WRITE(VEC_FREQ1_0,
655 tv_mode->custom_freq & 0xffff);
656 }
657
658 VEC_WRITE(VEC_DAC_MISC,
659 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);
660 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);
661
662 drm_dev_exit(idx);
663 return;
664
665err_put_runtime_pm:
666 pm_runtime_put(&vec->pdev->dev);
667err_dev_exit:
668 drm_dev_exit(idx);
669}
670
671static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,
672 struct drm_crtc_state *crtc_state,
673 struct drm_connector_state *conn_state)
674{
675 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
676 const struct vc4_vec_tv_mode *tv_mode;
677
678 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, mode->htotal);
679 if (!tv_mode)
680 return -EINVAL;
681
682 if (mode->crtc_hdisplay % 4)
683 return -EINVAL;
684
685 if (!(mode->crtc_hsync_end - mode->crtc_hsync_start))
686 return -EINVAL;
687
688 switch (mode->htotal) {
689 /* NTSC */
690 case 858:
691 if (mode->crtc_vtotal > 262)
692 return -EINVAL;
693
694 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 253)
695 return -EINVAL;
696
697 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))
698 return -EINVAL;
699
700 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)
701 return -EINVAL;
702
703 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 4)
704 return -EINVAL;
705
706 break;
707
708 /* PAL/SECAM */
709 case 864:
710 if (mode->crtc_vtotal > 312)
711 return -EINVAL;
712
713 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 305)
714 return -EINVAL;
715
716 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))
717 return -EINVAL;
718
719 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)
720 return -EINVAL;
721
722 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 2)
723 return -EINVAL;
724
725 break;
726
727 default:
728 return -EINVAL;
729 }
730
731 return 0;
732}
733
734static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {
735 .atomic_check = vc4_vec_encoder_atomic_check,
736 .atomic_disable = vc4_vec_encoder_disable,
737 .atomic_enable = vc4_vec_encoder_enable,
738};
739
740static int vc4_vec_late_register(struct drm_encoder *encoder)
741{
742 struct drm_device *drm = encoder->dev;
743 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);
744
745 vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset);
746
747 return 0;
748}
749
750static const struct drm_encoder_funcs vc4_vec_encoder_funcs = {
751 .late_register = vc4_vec_late_register,
752};
753
754static const struct vc4_vec_variant bcm2835_vec_variant = {
755 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) |
756 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |
757 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)
758};
759
760static const struct vc4_vec_variant bcm2711_vec_variant = {
761 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) |
762 VEC_DAC_CONFIG_DRIVER_CTRL(0x80) |
763 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61)
764};
765
766static const struct of_device_id vc4_vec_dt_match[] = {
767 { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant },
768 { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant },
769 { /* sentinel */ },
770};
771
772static int vc4_vec_bind(struct device *dev, struct device *master, void *data)
773{
774 struct platform_device *pdev = to_platform_device(dev);
775 struct drm_device *drm = dev_get_drvdata(master);
776 struct vc4_vec *vec;
777 int ret;
778
779 ret = drm_mode_create_tv_properties(drm,
780 BIT(DRM_MODE_TV_MODE_NTSC) |
781 BIT(DRM_MODE_TV_MODE_NTSC_443) |
782 BIT(DRM_MODE_TV_MODE_NTSC_J) |
783 BIT(DRM_MODE_TV_MODE_PAL) |
784 BIT(DRM_MODE_TV_MODE_PAL_M) |
785 BIT(DRM_MODE_TV_MODE_PAL_N) |
786 BIT(DRM_MODE_TV_MODE_SECAM) |
787 BIT(DRM_MODE_TV_MODE_MONOCHROME));
788 if (ret)
789 return ret;
790
791 vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL);
792 if (!vec)
793 return -ENOMEM;
794
795 vec->encoder.type = VC4_ENCODER_TYPE_VEC;
796 vec->pdev = pdev;
797 vec->variant = (const struct vc4_vec_variant *)
798 of_device_get_match_data(dev);
799 vec->regs = vc4_ioremap_regs(pdev, 0);
800 if (IS_ERR(vec->regs))
801 return PTR_ERR(vec->regs);
802 vec->regset.base = vec->regs;
803 vec->regset.regs = vec_regs;
804 vec->regset.nregs = ARRAY_SIZE(vec_regs);
805
806 vec->clock = devm_clk_get(dev, NULL);
807 if (IS_ERR(vec->clock)) {
808 ret = PTR_ERR(vec->clock);
809 if (ret != -EPROBE_DEFER)
810 drm_err(drm, "Failed to get clock: %d\n", ret);
811 return ret;
812 }
813
814 ret = devm_pm_runtime_enable(dev);
815 if (ret)
816 return ret;
817
818 ret = drmm_encoder_init(drm, &vec->encoder.base,
819 &vc4_vec_encoder_funcs,
820 DRM_MODE_ENCODER_TVDAC,
821 NULL);
822 if (ret)
823 return ret;
824
825 drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs);
826
827 ret = vc4_vec_connector_init(drm, vec);
828 if (ret)
829 return ret;
830
831 dev_set_drvdata(dev, vec);
832
833 return 0;
834}
835
836static const struct component_ops vc4_vec_ops = {
837 .bind = vc4_vec_bind,
838};
839
840static int vc4_vec_dev_probe(struct platform_device *pdev)
841{
842 return component_add(&pdev->dev, &vc4_vec_ops);
843}
844
845static void vc4_vec_dev_remove(struct platform_device *pdev)
846{
847 component_del(&pdev->dev, &vc4_vec_ops);
848}
849
850struct platform_driver vc4_vec_driver = {
851 .probe = vc4_vec_dev_probe,
852 .remove = vc4_vec_dev_remove,
853 .driver = {
854 .name = "vc4_vec",
855 .of_match_table = vc4_vec_dt_match,
856 },
857};