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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 * Fabien Dessenne <fabien.dessenne@st.com>
8 * Mickael Reulier <mickael.reulier@st.com>
9 */
10
11#ifndef _LTDC_H_
12#define _LTDC_H_
13
14struct ltdc_caps {
15 u32 hw_version; /* hardware version */
16 u32 nb_layers; /* number of supported layers */
17 u32 layer_ofs; /* layer offset for applicable regs */
18 const u32 *layer_regs; /* layer register offset */
19 u32 bus_width; /* bus width (32 or 64 bits) */
20 const u32 *pix_fmt_hw; /* supported hw pixel formats */
21 const u32 *pix_fmt_drm; /* supported drm pixel formats */
22 int pix_fmt_nb; /* number of pixel format */
23 bool pix_fmt_flex; /* pixel format flexibility supported */
24 bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
25 int pad_max_freq_hz; /* max frequency supported by pad */
26 int nb_irq; /* number of hardware interrupts */
27 bool ycbcr_input; /* ycbcr input converter supported */
28 bool ycbcr_output; /* ycbcr output converter supported */
29 bool plane_reg_shadow; /* plane shadow registers ability */
30 bool crc; /* cyclic redundancy check supported */
31 bool dynamic_zorder; /* dynamic z-order */
32 bool plane_rotation; /* plane rotation */
33 bool fifo_threshold; /* fifo underrun threshold supported */
34};
35
36#define LTDC_MAX_LAYER 4
37
38struct fps_info {
39 unsigned int counter;
40 ktime_t last_timestamp;
41};
42
43struct ltdc_plat_data {
44 int pad_max_freq_hz; /* max frequency supported by pad */
45};
46
47struct ltdc_device {
48 void __iomem *regs;
49 struct regmap *regmap;
50 struct clk *pixel_clk; /* lcd pixel clock */
51 struct clk *lvds_clk; /* lvds pixel clock */
52 struct clk *bus_clk; /* bus clock */
53 struct mutex err_lock; /* protecting error_status */
54 struct ltdc_caps caps;
55 u32 irq_status;
56 u32 fifo_err; /* fifo underrun error counter */
57 u32 fifo_warn; /* fifo underrun warning counter */
58 u32 fifo_threshold; /* fifo underrun threshold */
59 u32 transfer_err; /* transfer error counter */
60 struct fps_info plane_fpsi[LTDC_MAX_LAYER];
61 struct drm_atomic_state *suspend_state;
62 int crc_skip_count;
63 bool crc_active;
64};
65
66int ltdc_load(struct drm_device *ddev);
67void ltdc_unload(struct drm_device *ddev);
68void ltdc_suspend(struct drm_device *ddev);
69int ltdc_resume(struct drm_device *ddev);
70
71#endif