Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0-only
2menuconfig CXL_BUS
3 tristate "CXL (Compute Express Link) Devices Support"
4 depends on PCI
5 select FW_LOADER
6 select FW_UPLOAD
7 select PCI_DOE
8 select FIRMWARE_TABLE
9 select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS
10 select FWCTL if CXL_FEATURES
11 help
12 CXL is a bus that is electrically compatible with PCI Express, but
13 layers three protocols on that signalling (CXL.io, CXL.cache, and
14 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
15 locally, the CXL.mem protocol allows devices to be fully coherent
16 memory targets, the CXL.io protocol is equivalent to PCI Express.
17 Say 'y' to enable support for the configuration and management of
18 devices supporting these protocols.
19
20if CXL_BUS
21
22config CXL_PCI
23 tristate "PCI manageability"
24 default CXL_BUS
25 help
26 The CXL specification defines a "CXL memory device" sub-class in the
27 PCI "memory controller" base class of devices. Device's identified by
28 this class code provide support for volatile and / or persistent
29 memory to be mapped into the system address map (Host-managed Device
30 Memory (HDM)).
31
32 Say 'y/m' to enable a driver that will attach to CXL memory expander
33 devices enumerated by the memory device class code for configuration
34 and management primarily via the mailbox interface. See Chapter 2.3
35 Type 3 CXL Device in the CXL 2.0 specification for more details.
36
37 If unsure say 'm'.
38
39config CXL_MEM_RAW_COMMANDS
40 bool "RAW Command Interface for Memory Devices"
41 depends on CXL_PCI
42 help
43 Enable CXL RAW command interface.
44
45 The CXL driver ioctl interface may assign a kernel ioctl command
46 number for each specification defined opcode. At any given point in
47 time the number of opcodes that the specification defines and a device
48 may implement may exceed the kernel's set of associated ioctl function
49 numbers. The mismatch is either by omission, specification is too new,
50 or by design. When prototyping new hardware, or developing / debugging
51 the driver it is useful to be able to submit any possible command to
52 the hardware, even commands that may crash the kernel due to their
53 potential impact to memory currently in use by the kernel.
54
55 If developing CXL hardware or the driver say Y, otherwise say N.
56
57config CXL_ACPI
58 tristate "CXL ACPI: Platform Support"
59 depends on ACPI
60 depends on ACPI_NUMA
61 default CXL_BUS
62 select ACPI_TABLE_LIB
63 select ACPI_HMAT
64 select CXL_PORT
65 help
66 Enable support for host managed device memory (HDM) resources
67 published by a platform's ACPI CXL memory layout description. See
68 Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0
69 specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS)
70 (https://www.computeexpresslink.org/spec-landing). The CXL core
71 consumes these resource to publish the root of a cxl_port decode
72 hierarchy to map regions that represent System RAM, or Persistent
73 Memory regions to be managed by LIBNVDIMM.
74
75 If unsure say 'm'.
76
77config CXL_PMEM
78 tristate "CXL PMEM: Persistent Memory Support"
79 depends on LIBNVDIMM
80 default CXL_BUS
81 help
82 In addition to typical memory resources a platform may also advertise
83 support for persistent memory attached via CXL. This support is
84 managed via a bridge driver from CXL to the LIBNVDIMM system
85 subsystem. Say 'y/m' to enable support for enumerating and
86 provisioning the persistent memory capacity of CXL memory expanders.
87
88 If unsure say 'm'.
89
90config CXL_MEM
91 tristate "CXL: Memory Expansion"
92 depends on CXL_PCI
93 default CXL_BUS
94 help
95 The CXL.mem protocol allows a device to act as a provider of "System
96 RAM" and/or "Persistent Memory" that is fully coherent as if the
97 memory were attached to the typical CPU memory controller. This is
98 known as HDM "Host-managed Device Memory".
99
100 Say 'y/m' to enable a driver that will attach to CXL.mem devices for
101 memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0
102 specification for a detailed description of HDM.
103
104 If unsure say 'm'.
105
106config CXL_FEATURES
107 bool "CXL: Features"
108 depends on CXL_PCI
109 help
110 Enable support for CXL Features. A CXL device that includes a mailbox
111 supports commands that allows listing, getting, and setting of
112 optionally defined features such as memory sparing or post package
113 sparing. Vendors may define custom features for the device.
114
115 If unsure say 'n'
116
117config CXL_EDAC_MEM_FEATURES
118 bool "CXL: EDAC Memory Features"
119 depends on EXPERT
120 depends on CXL_MEM
121 depends on CXL_FEATURES
122 depends on EDAC >= CXL_BUS
123 help
124 The CXL EDAC memory feature is optional and allows host to
125 control the EDAC memory features configurations of CXL memory
126 expander devices.
127
128 Say 'y' if you have an expert need to change default settings
129 of a memory RAS feature established by the platform/device.
130 Otherwise say 'n'.
131
132config CXL_EDAC_SCRUB
133 bool "Enable CXL Patrol Scrub Control (Patrol Read)"
134 depends on CXL_EDAC_MEM_FEATURES
135 depends on EDAC_SCRUB
136 help
137 The CXL EDAC scrub control is optional and allows host to
138 control the scrub feature configurations of CXL memory expander
139 devices.
140
141 When enabled 'cxl_mem' and 'cxl_region' EDAC devices are
142 published with memory scrub control attributes as described by
143 Documentation/ABI/testing/sysfs-edac-scrub.
144
145 Say 'y' if you have an expert need to change default settings
146 of a memory scrub feature established by the platform/device
147 (e.g. scrub rates for the patrol scrub feature).
148 Otherwise say 'n'.
149
150config CXL_EDAC_ECS
151 bool "Enable CXL Error Check Scrub (Repair)"
152 depends on CXL_EDAC_MEM_FEATURES
153 depends on EDAC_ECS
154 help
155 The CXL EDAC ECS control is optional and allows host to
156 control the ECS feature configurations of CXL memory expander
157 devices.
158
159 When enabled 'cxl_mem' EDAC devices are published with memory
160 ECS control attributes as described by
161 Documentation/ABI/testing/sysfs-edac-ecs.
162
163 Say 'y' if you have an expert need to change default settings
164 of a memory ECS feature established by the platform/device.
165 Otherwise say 'n'.
166
167config CXL_EDAC_MEM_REPAIR
168 bool "Enable CXL Memory Repair"
169 depends on CXL_EDAC_MEM_FEATURES
170 depends on EDAC_MEM_REPAIR
171 help
172 The CXL EDAC memory repair control is optional and allows host
173 to control the memory repair features (e.g. sparing, PPR)
174 configurations of CXL memory expander devices.
175
176 When enabled, the memory repair feature requires an additional
177 memory of approximately 43KB to store CXL DRAM and CXL general
178 media event records.
179
180 When enabled 'cxl_mem' EDAC devices are published with memory
181 repair control attributes as described by
182 Documentation/ABI/testing/sysfs-edac-memory-repair.
183
184 Say 'y' if you have an expert need to change default settings
185 of a memory repair feature established by the platform/device.
186 Otherwise say 'n'.
187
188config CXL_PORT
189 default CXL_BUS
190 tristate
191
192config CXL_SUSPEND
193 def_bool y
194 depends on SUSPEND && CXL_MEM
195
196config CXL_REGION
197 bool "CXL: Region Support"
198 default CXL_BUS
199 # For MAX_PHYSMEM_BITS
200 depends on SPARSEMEM
201 select MEMREGION
202 select GET_FREE_REGION
203 help
204 Enable the CXL core to enumerate and provision CXL regions. A CXL
205 region is defined by one or more CXL expanders that decode a given
206 system-physical address range. For CXL regions established by
207 platform-firmware this option enables memory error handling to
208 identify the devices participating in a given interleaved memory
209 range. Otherwise, platform-firmware managed CXL is enabled by being
210 placed in the system address map and does not need a driver.
211
212 If unsure say 'y'
213
214config CXL_REGION_INVALIDATION_TEST
215 bool "CXL: Region Cache Management Bypass (TEST)"
216 depends on CXL_REGION
217 help
218 CXL Region management and security operations potentially invalidate
219 the content of CPU caches without notifying those caches to
220 invalidate the affected cachelines. The CXL Region driver attempts
221 to invalidate caches when those events occur. If that invalidation
222 fails the region will fail to enable. Reasons for cache
223 invalidation failure are due to the CPU not providing a cache
224 invalidation mechanism. For example usage of wbinvd is restricted to
225 bare metal x86. However, for testing purposes toggling this option
226 can disable that data integrity safety and proceed with enabling
227 regions when there might be conflicting contents in the CPU cache.
228
229 If unsure, or if this kernel is meant for production environments,
230 say N.
231
232config CXL_MCE
233 def_bool y
234 depends on X86_MCE && MEMORY_FAILURE
235
236endif