Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 * Copyright (C) 2011 Google, Inc.
5 *
6 * Author:
7 * Jay Cheng <jacheng@nvidia.com>
8 * James Wylder <james.wylder@motorola.com>
9 * Benoit Goby <benoit@android.com>
10 * Colin Cross <ccross@android.com>
11 * Hiroshi DOYU <hdoyu@nvidia.com>
12 */
13
14#include <linux/err.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/of.h>
20
21#include <soc/tegra/ahb.h>
22
23#define DRV_NAME "tegra-ahb"
24
25#define AHB_ARBITRATION_DISABLE 0x04
26#define AHB_ARBITRATION_PRIORITY_CTRL 0x08
27#define AHB_PRIORITY_WEIGHT(x) (((x) & 0x7) << 29)
28#define PRIORITY_SELECT_USB BIT(6)
29#define PRIORITY_SELECT_USB2 BIT(18)
30#define PRIORITY_SELECT_USB3 BIT(17)
31
32#define AHB_GIZMO_AHB_MEM 0x10
33#define ENB_FAST_REARBITRATE BIT(2)
34#define DONT_SPLIT_AHB_WR BIT(7)
35
36#define AHB_GIZMO_APB_DMA 0x14
37#define AHB_GIZMO_IDE 0x1c
38#define AHB_GIZMO_USB 0x20
39#define AHB_GIZMO_AHB_XBAR_BRIDGE 0x24
40#define AHB_GIZMO_CPU_AHB_BRIDGE 0x28
41#define AHB_GIZMO_COP_AHB_BRIDGE 0x2c
42#define AHB_GIZMO_XBAR_APB_CTLR 0x30
43#define AHB_GIZMO_VCP_AHB_BRIDGE 0x34
44#define AHB_GIZMO_NAND 0x40
45#define AHB_GIZMO_SDMMC4 0x48
46#define AHB_GIZMO_XIO 0x4c
47#define AHB_GIZMO_BSEV 0x64
48#define AHB_GIZMO_BSEA 0x74
49#define AHB_GIZMO_NOR 0x78
50#define AHB_GIZMO_USB2 0x7c
51#define AHB_GIZMO_USB3 0x80
52#define IMMEDIATE BIT(18)
53
54#define AHB_GIZMO_SDMMC1 0x84
55#define AHB_GIZMO_SDMMC2 0x88
56#define AHB_GIZMO_SDMMC3 0x8c
57#define AHB_MEM_PREFETCH_CFG_X 0xdc
58#define AHB_ARBITRATION_XBAR_CTRL 0xe0
59#define AHB_MEM_PREFETCH_CFG3 0xe4
60#define AHB_MEM_PREFETCH_CFG4 0xe8
61#define AHB_MEM_PREFETCH_CFG1 0xf0
62#define AHB_MEM_PREFETCH_CFG2 0xf4
63#define PREFETCH_ENB BIT(31)
64#define MST_ID(x) (((x) & 0x1f) << 26)
65#define AHBDMA_MST_ID MST_ID(5)
66#define USB_MST_ID MST_ID(6)
67#define USB2_MST_ID MST_ID(18)
68#define USB3_MST_ID MST_ID(17)
69#define ADDR_BNDRY(x) (((x) & 0xf) << 21)
70#define INACTIVITY_TIMEOUT(x) (((x) & 0xffff) << 0)
71
72#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xfc
73
74#define AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE BIT(17)
75
76/*
77 * INCORRECT_BASE_ADDR_LOW_BYTE: Legacy kernel DT files for Tegra SoCs
78 * prior to Tegra124 generally use a physical base address ending in
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
80 * should be 0x0. During device probing, this macro is used to detect
81 * whether the passed-in physical address is incorrect, and if so, to
82 * correct it.
83 */
84#define INCORRECT_BASE_ADDR_LOW_BYTE 0x4
85
86static struct platform_driver tegra_ahb_driver;
87
88static const u32 tegra_ahb_gizmo[] = {
89 AHB_ARBITRATION_DISABLE,
90 AHB_ARBITRATION_PRIORITY_CTRL,
91 AHB_GIZMO_AHB_MEM,
92 AHB_GIZMO_APB_DMA,
93 AHB_GIZMO_IDE,
94 AHB_GIZMO_USB,
95 AHB_GIZMO_AHB_XBAR_BRIDGE,
96 AHB_GIZMO_CPU_AHB_BRIDGE,
97 AHB_GIZMO_COP_AHB_BRIDGE,
98 AHB_GIZMO_XBAR_APB_CTLR,
99 AHB_GIZMO_VCP_AHB_BRIDGE,
100 AHB_GIZMO_NAND,
101 AHB_GIZMO_SDMMC4,
102 AHB_GIZMO_XIO,
103 AHB_GIZMO_BSEV,
104 AHB_GIZMO_BSEA,
105 AHB_GIZMO_NOR,
106 AHB_GIZMO_USB2,
107 AHB_GIZMO_USB3,
108 AHB_GIZMO_SDMMC1,
109 AHB_GIZMO_SDMMC2,
110 AHB_GIZMO_SDMMC3,
111 AHB_MEM_PREFETCH_CFG_X,
112 AHB_ARBITRATION_XBAR_CTRL,
113 AHB_MEM_PREFETCH_CFG3,
114 AHB_MEM_PREFETCH_CFG4,
115 AHB_MEM_PREFETCH_CFG1,
116 AHB_MEM_PREFETCH_CFG2,
117 AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID,
118};
119
120struct tegra_ahb {
121 void __iomem *regs;
122 struct device *dev;
123 u32 ctx[];
124};
125
126static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
127{
128 return readl(ahb->regs + offset);
129}
130
131static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
132{
133 writel(value, ahb->regs + offset);
134}
135
136#ifdef CONFIG_TEGRA_IOMMU_SMMU
137int tegra_ahb_enable_smmu(struct device_node *dn)
138{
139 struct device *dev;
140 u32 val;
141 struct tegra_ahb *ahb;
142
143 dev = driver_find_device_by_of_node(&tegra_ahb_driver.driver, dn);
144 if (!dev)
145 return -EPROBE_DEFER;
146 ahb = dev_get_drvdata(dev);
147 put_device(dev);
148 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
149 val |= AHB_ARBITRATION_XBAR_CTRL_SMMU_INIT_DONE;
150 gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
151 return 0;
152}
153EXPORT_SYMBOL(tegra_ahb_enable_smmu);
154#endif
155
156static int __maybe_unused tegra_ahb_suspend(struct device *dev)
157{
158 int i;
159 struct tegra_ahb *ahb = dev_get_drvdata(dev);
160
161 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
162 ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
163 return 0;
164}
165
166static int __maybe_unused tegra_ahb_resume(struct device *dev)
167{
168 int i;
169 struct tegra_ahb *ahb = dev_get_drvdata(dev);
170
171 for (i = 0; i < ARRAY_SIZE(tegra_ahb_gizmo); i++)
172 gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
173 return 0;
174}
175
176static UNIVERSAL_DEV_PM_OPS(tegra_ahb_pm,
177 tegra_ahb_suspend,
178 tegra_ahb_resume, NULL);
179
180static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
181{
182 u32 val;
183
184 val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
185 val |= ENB_FAST_REARBITRATE | IMMEDIATE | DONT_SPLIT_AHB_WR;
186 gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
187
188 val = gizmo_readl(ahb, AHB_GIZMO_USB);
189 val |= IMMEDIATE;
190 gizmo_writel(ahb, val, AHB_GIZMO_USB);
191
192 val = gizmo_readl(ahb, AHB_GIZMO_USB2);
193 val |= IMMEDIATE;
194 gizmo_writel(ahb, val, AHB_GIZMO_USB2);
195
196 val = gizmo_readl(ahb, AHB_GIZMO_USB3);
197 val |= IMMEDIATE;
198 gizmo_writel(ahb, val, AHB_GIZMO_USB3);
199
200 val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
201 val |= PRIORITY_SELECT_USB |
202 PRIORITY_SELECT_USB2 |
203 PRIORITY_SELECT_USB3 |
204 AHB_PRIORITY_WEIGHT(7);
205 gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
206
207 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
208 val &= ~MST_ID(~0);
209 val |= PREFETCH_ENB |
210 AHBDMA_MST_ID |
211 ADDR_BNDRY(0xc) |
212 INACTIVITY_TIMEOUT(0x1000);
213 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
214
215 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
216 val &= ~MST_ID(~0);
217 val |= PREFETCH_ENB |
218 USB_MST_ID |
219 ADDR_BNDRY(0xc) |
220 INACTIVITY_TIMEOUT(0x1000);
221 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
222
223 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
224 val &= ~MST_ID(~0);
225 val |= PREFETCH_ENB |
226 USB3_MST_ID |
227 ADDR_BNDRY(0xc) |
228 INACTIVITY_TIMEOUT(0x1000);
229 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
230
231 val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
232 val &= ~MST_ID(~0);
233 val |= PREFETCH_ENB |
234 USB2_MST_ID |
235 ADDR_BNDRY(0xc) |
236 INACTIVITY_TIMEOUT(0x1000);
237 gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
238}
239
240static int tegra_ahb_probe(struct platform_device *pdev)
241{
242 struct resource *res;
243 struct tegra_ahb *ahb;
244 size_t bytes;
245
246 bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
247 ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
248 if (!ahb)
249 return -ENOMEM;
250
251 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252
253 /* Correct the IP block base address if necessary */
254 if (res &&
255 (res->start & INCORRECT_BASE_ADDR_LOW_BYTE) ==
256 INCORRECT_BASE_ADDR_LOW_BYTE) {
257 dev_warn(&pdev->dev, "incorrect AHB base address in DT data - enabling workaround\n");
258 res->start -= INCORRECT_BASE_ADDR_LOW_BYTE;
259 }
260
261 ahb->regs = devm_ioremap_resource(&pdev->dev, res);
262 if (IS_ERR(ahb->regs))
263 return PTR_ERR(ahb->regs);
264
265 ahb->dev = &pdev->dev;
266 platform_set_drvdata(pdev, ahb);
267 tegra_ahb_gizmo_init(ahb);
268 return 0;
269}
270
271static const struct of_device_id tegra_ahb_of_match[] = {
272 { .compatible = "nvidia,tegra30-ahb", },
273 { .compatible = "nvidia,tegra20-ahb", },
274 {},
275};
276
277static struct platform_driver tegra_ahb_driver = {
278 .probe = tegra_ahb_probe,
279 .driver = {
280 .name = DRV_NAME,
281 .of_match_table = tegra_ahb_of_match,
282 .pm = &tegra_ahb_pm,
283 },
284};
285module_platform_driver(tegra_ahb_driver);
286
287MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
288MODULE_DESCRIPTION("Tegra AHB driver");
289MODULE_ALIAS("platform:" DRV_NAME);