tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * IPQ5424 device tree source
4 *
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
6 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/qcom,apss-ipq.h>
11#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
12#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
13#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
14#include <dt-bindings/interconnect/qcom,ipq5424.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/thermal/thermal.h>
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <2>;
21 interrupt-parent = <&intc>;
22
23 clocks {
24 ref_48mhz_clk: ref-48mhz-clk {
25 compatible = "fixed-factor-clock";
26 clocks = <&xo_clk>;
27 #clock-cells = <0>;
28 };
29
30 sleep_clk: sleep-clk {
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
33 };
34
35 xo_board: xo-board-clk {
36 compatible = "fixed-factor-clock";
37 clocks = <&ref_48mhz_clk>;
38 #clock-cells = <0>;
39 };
40
41 xo_clk: xo-clk {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 };
45 };
46
47 cpus: cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a55";
54 reg = <0x0>;
55 enable-method = "psci";
56 next-level-cache = <&l2_0>;
57 clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
58 clock-names = "cpu";
59 operating-points-v2 = <&cpu_opp_table>;
60 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
61 #cooling-cells = <2>;
62
63 l2_0: l2-cache {
64 compatible = "cache";
65 cache-level = <2>;
66 cache-unified;
67 next-level-cache = <&l3_0>;
68
69 l3_0: l3-cache {
70 compatible = "cache";
71 cache-level = <3>;
72 cache-unified;
73 };
74 };
75 };
76
77 cpu1: cpu@100 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a55";
80 enable-method = "psci";
81 reg = <0x100>;
82 next-level-cache = <&l2_100>;
83 clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
84 clock-names = "cpu";
85 operating-points-v2 = <&cpu_opp_table>;
86 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
87 #cooling-cells = <2>;
88
89 l2_100: l2-cache {
90 compatible = "cache";
91 cache-level = <2>;
92 cache-unified;
93 next-level-cache = <&l3_0>;
94 };
95 };
96
97 cpu2: cpu@200 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a55";
100 enable-method = "psci";
101 reg = <0x200>;
102 next-level-cache = <&l2_200>;
103 clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
104 clock-names = "cpu";
105 operating-points-v2 = <&cpu_opp_table>;
106 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
107 #cooling-cells = <2>;
108
109 l2_200: l2-cache {
110 compatible = "cache";
111 cache-level = <2>;
112 cache-unified;
113 next-level-cache = <&l3_0>;
114 };
115 };
116
117 cpu3: cpu@300 {
118 device_type = "cpu";
119 compatible = "arm,cortex-a55";
120 enable-method = "psci";
121 reg = <0x300>;
122 next-level-cache = <&l2_300>;
123 clocks = <&apss_clk APSS_SILVER_CORE_CLK>;
124 clock-names = "cpu";
125 operating-points-v2 = <&cpu_opp_table>;
126 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>;
127 #cooling-cells = <2>;
128
129 l2_300: l2-cache {
130 compatible = "cache";
131 cache-level = <2>;
132 cache-unified;
133 next-level-cache = <&l3_0>;
134 };
135 };
136 };
137
138 firmware {
139 scm {
140 compatible = "qcom,scm-ipq5424", "qcom,scm";
141 qcom,dload-mode = <&tcsr 0x25100>;
142 };
143 };
144
145 cpu_opp_table: opp-table-cpu {
146 compatible = "operating-points-v2-kryo-cpu";
147 opp-shared;
148 nvmem-cells = <&cpu_speed_bin>;
149
150 opp-816000000 {
151 opp-hz = /bits/ 64 <816000000>;
152 opp-microvolt = <850000>;
153 opp-supported-hw = <0x3>;
154 clock-latency-ns = <200000>;
155 opp-peak-kBps = <816000>;
156 };
157
158 opp-1416000000 {
159 opp-hz = /bits/ 64 <1416000000>;
160 opp-microvolt = <850000>;
161 opp-supported-hw = <0x3>;
162 clock-latency-ns = <200000>;
163 opp-peak-kBps = <984000>;
164 };
165
166 opp-1800000000 {
167 opp-hz = /bits/ 64 <1800000000>;
168 opp-microvolt = <1000000>;
169 opp-supported-hw = <0x1>;
170 clock-latency-ns = <200000>;
171 opp-peak-kBps = <1272000>;
172 };
173 };
174
175 memory@80000000 {
176 device_type = "memory";
177 /* We expect the bootloader to fill in the size */
178 reg = <0x0 0x80000000 0x0 0x0>;
179 };
180
181 pmu-a55 {
182 compatible = "arm,cortex-a55-pmu";
183 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
184 };
185
186 pmu-dsu {
187 compatible = "arm,dsu-pmu";
188 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
189 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
190 };
191
192 psci {
193 compatible = "arm,psci-1.0";
194 method = "smc";
195 };
196
197 reserved-memory {
198 #address-cells = <2>;
199 #size-cells = <2>;
200 ranges;
201
202 bootloader@8a200000 {
203 reg = <0x0 0x8a200000 0x0 0x400000>;
204 no-map;
205 };
206
207 tz@8a600000 {
208 reg = <0x0 0x8a600000 0x0 0x200000>;
209 no-map;
210 };
211
212 smem@8a800000 {
213 compatible = "qcom,smem";
214 reg = <0x0 0x8a800000 0x0 0x32000>;
215 no-map;
216
217 hwlocks = <&tcsr_mutex 3>;
218 };
219
220 tfa@8a832000 {
221 reg = <0x0 0x8a832000 0x0 0x80000>;
222 no-map;
223 status = "disabled";
224 };
225 };
226
227 soc@0 {
228 compatible = "simple-bus";
229 #address-cells = <2>;
230 #size-cells = <2>;
231 ranges = <0 0 0 0 0x10 0>;
232
233 pcie0_phy: phy@84000 {
234 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
235 "qcom,ipq9574-qmp-gen3x1-pcie-phy";
236 reg = <0x0 0x00084000 0x0 0x1000>;
237 clocks = <&gcc GCC_PCIE0_AUX_CLK>,
238 <&gcc GCC_PCIE0_AHB_CLK>,
239 <&gcc GCC_PCIE0_PIPE_CLK>;
240 clock-names = "aux",
241 "cfg_ahb",
242 "pipe";
243
244 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
245 assigned-clock-rates = <20000000>;
246
247 resets = <&gcc GCC_PCIE0_PHY_BCR>,
248 <&gcc GCC_PCIE0PHY_PHY_BCR>;
249 reset-names = "phy",
250 "common";
251
252 #clock-cells = <0>;
253 clock-output-names = "gcc_pcie0_pipe_clk_src";
254
255 #phy-cells = <0>;
256 status = "disabled";
257 };
258
259 pcie1_phy: phy@8c000 {
260 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
261 "qcom,ipq9574-qmp-gen3x1-pcie-phy";
262 reg = <0x0 0x0008c000 0x0 0x1000>;
263 clocks = <&gcc GCC_PCIE1_AUX_CLK>,
264 <&gcc GCC_PCIE1_AHB_CLK>,
265 <&gcc GCC_PCIE1_PIPE_CLK>;
266 clock-names = "aux",
267 "cfg_ahb",
268 "pipe";
269
270 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
271 assigned-clock-rates = <20000000>;
272
273 resets = <&gcc GCC_PCIE1_PHY_BCR>,
274 <&gcc GCC_PCIE1PHY_PHY_BCR>;
275 reset-names = "phy",
276 "common";
277
278 #clock-cells = <0>;
279 clock-output-names = "gcc_pcie1_pipe_clk_src";
280
281 #phy-cells = <0>;
282 status = "disabled";
283 };
284
285 cmn_pll: clock-controller@9b000 {
286 compatible = "qcom,ipq5424-cmn-pll";
287 reg = <0 0x0009b000 0 0x800>;
288 clocks = <&ref_48mhz_clk>,
289 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
290 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
291 clock-names = "ref", "ahb", "sys";
292 #clock-cells = <1>;
293 assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>;
294 assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
295 };
296
297 efuse@a4000 {
298 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
299 reg = <0 0x000a4000 0 0x741>;
300 #address-cells = <1>;
301 #size-cells = <1>;
302
303 tsens_sens9_off: s9@3dc {
304 reg = <0x3dc 0x1>;
305 bits = <4 4>;
306 };
307
308 tsens_sens10_off: s10@3dd {
309 reg = <0x3dd 0x1>;
310 bits = <0 4>;
311 };
312
313 tsens_sens11_off: s11@3dd {
314 reg = <0x3dd 0x1>;
315 bits = <4 4>;
316 };
317
318 tsens_sens12_off: s12@3de {
319 reg = <0x3de 0x1>;
320 bits = <0 4>;
321 };
322
323 tsens_sens13_off: s13@3de {
324 reg = <0x3de 0x1>;
325 bits = <4 4>;
326 };
327
328 tsens_sens14_off: s14@3e5 {
329 reg = <0x3e5 0x2>;
330 bits = <7 4>;
331 };
332
333 tsens_sens15_off: s15@3e6 {
334 reg = <0x3e6 0x1>;
335 bits = <3 4>;
336 };
337
338 tsens_mode: mode@419 {
339 reg = <0x419 0x1>;
340 bits = <0 3>;
341 };
342
343 tsens_base0: base0@419 {
344 reg = <0x419 0x2>;
345 bits = <3 10>;
346 };
347
348 tsens_base1: base1@41a {
349 reg = <0x41a 0x2>;
350 bits = <5 10>;
351 };
352 };
353
354 pcie2_phy: phy@f4000 {
355 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
356 "qcom,ipq9574-qmp-gen3x2-pcie-phy";
357 reg = <0x0 0x000f4000 0x0 0x2000>;
358 clocks = <&gcc GCC_PCIE2_AUX_CLK>,
359 <&gcc GCC_PCIE2_AHB_CLK>,
360 <&gcc GCC_PCIE2_PIPE_CLK>;
361 clock-names = "aux",
362 "cfg_ahb",
363 "pipe";
364
365 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
366 assigned-clock-rates = <20000000>;
367
368 resets = <&gcc GCC_PCIE2_PHY_BCR>,
369 <&gcc GCC_PCIE2PHY_PHY_BCR>;
370 reset-names = "phy",
371 "common";
372
373 #clock-cells = <0>;
374 clock-output-names = "gcc_pcie2_pipe_clk_src";
375
376 #phy-cells = <0>;
377 status = "disabled";
378 };
379
380 pcie3_phy: phy@fc000 {
381 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
382 "qcom,ipq9574-qmp-gen3x2-pcie-phy";
383 reg = <0x0 0x000fc000 0x0 0x2000>;
384 clocks = <&gcc GCC_PCIE3_AUX_CLK>,
385 <&gcc GCC_PCIE3_AHB_CLK>,
386 <&gcc GCC_PCIE3_PIPE_CLK>;
387 clock-names = "aux",
388 "cfg_ahb",
389 "pipe";
390
391 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
392 assigned-clock-rates = <20000000>;
393
394 resets = <&gcc GCC_PCIE3_PHY_BCR>,
395 <&gcc GCC_PCIE3PHY_PHY_BCR>;
396 reset-names = "phy",
397 "common";
398
399 #clock-cells = <0>;
400 clock-output-names = "gcc_pcie3_pipe_clk_src";
401
402 #phy-cells = <0>;
403 status = "disabled";
404 };
405
406 tsens: thermal-sensor@4a9000 {
407 compatible = "qcom,ipq5424-tsens";
408 reg = <0 0x004a9000 0 0x1000>,
409 <0 0x004a8000 0 0x1000>;
410 interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>;
411 interrupt-names = "combined";
412 nvmem-cells = <&tsens_mode>,
413 <&tsens_base0>,
414 <&tsens_base1>,
415 <&tsens_sens9_off>,
416 <&tsens_sens10_off>,
417 <&tsens_sens11_off>,
418 <&tsens_sens12_off>,
419 <&tsens_sens13_off>,
420 <&tsens_sens14_off>,
421 <&tsens_sens15_off>;
422 nvmem-cell-names = "mode",
423 "base0",
424 "base1",
425 "tsens_sens9_off",
426 "tsens_sens10_off",
427 "tsens_sens11_off",
428 "tsens_sens12_off",
429 "tsens_sens13_off",
430 "tsens_sens14_off",
431 "tsens_sens15_off";
432 #qcom,sensors = <7>;
433 #thermal-sensor-cells = <1>;
434 };
435
436 rng: rng@4c3000 {
437 compatible = "qcom,ipq5424-trng", "qcom,trng";
438 reg = <0 0x004c3000 0 0x1000>;
439 clocks = <&gcc GCC_PRNG_AHB_CLK>;
440 clock-names = "core";
441 };
442
443 system-cache-controller@800000 {
444 compatible = "qcom,ipq5424-llcc";
445 reg = <0 0x00800000 0 0x200000>;
446 reg-names = "llcc0_base";
447 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
448 };
449
450 qfprom@a6000 {
451 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom";
452 reg = <0x0 0x000a6000 0x0 0x1000>;
453 #address-cells = <1>;
454 #size-cells = <1>;
455
456 cpu_speed_bin: cpu-speed-bin@234 {
457 reg = <0x234 0x1>;
458 bits = <0 8>;
459 };
460 };
461
462 tlmm: pinctrl@1000000 {
463 compatible = "qcom,ipq5424-tlmm";
464 reg = <0 0x01000000 0 0x300000>;
465 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
466 gpio-controller;
467 #gpio-cells = <2>;
468 gpio-ranges = <&tlmm 0 0 50>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471
472 uart1_pins: uart1-state {
473 pins = "gpio43", "gpio44";
474 function = "uart1";
475 drive-strength = <8>;
476 bias-pull-up;
477 };
478 };
479
480 gcc: clock-controller@1800000 {
481 compatible = "qcom,ipq5424-gcc";
482 reg = <0 0x01800000 0 0x40000>;
483 clocks = <&xo_board>,
484 <&sleep_clk>,
485 <&pcie0_phy>,
486 <&pcie1_phy>,
487 <&pcie2_phy>,
488 <&pcie3_phy>,
489 <0>;
490 #clock-cells = <1>;
491 #reset-cells = <1>;
492 #interconnect-cells = <1>;
493 };
494
495 tcsr_mutex: hwlock@1905000 {
496 compatible = "qcom,tcsr-mutex";
497 reg = <0 0x01905000 0 0x20000>;
498 #hwlock-cells = <1>;
499 };
500
501 tcsr: syscon@1937000 {
502 compatible = "qcom,tcsr-ipq5424", "syscon";
503 reg = <0 0x01937000 0 0x2a000>;
504 };
505
506 qupv3: geniqup@1ac0000 {
507 compatible = "qcom,geni-se-qup";
508 reg = <0 0x01ac0000 0 0x2000>;
509 ranges;
510 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
511 <&gcc GCC_QUPV3_AHB_SLV_CLK>;
512 clock-names = "m-ahb", "s-ahb";
513 #address-cells = <2>;
514 #size-cells = <2>;
515
516 uart0: serial@1a80000 {
517 compatible = "qcom,geni-uart";
518 reg = <0 0x01a80000 0 0x4000>;
519 clocks = <&gcc GCC_QUPV3_UART0_CLK>;
520 clock-names = "se";
521 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
522 status = "disabled";
523 };
524
525 uart1: serial@1a84000 {
526 compatible = "qcom,geni-debug-uart";
527 reg = <0 0x01a84000 0 0x4000>;
528 clocks = <&gcc GCC_QUPV3_UART1_CLK>;
529 clock-names = "se";
530 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
531 };
532
533 spi0: spi@1a90000 {
534 compatible = "qcom,geni-spi";
535 reg = <0 0x01a90000 0 0x4000>;
536 clocks = <&gcc GCC_QUPV3_SPI0_CLK>;
537 clock-names = "se";
538 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
539 #address-cells = <1>;
540 #size-cells = <0>;
541 status = "disabled";
542 };
543
544 spi1: spi@1a94000 {
545 compatible = "qcom,geni-spi";
546 reg = <0 0x01a94000 0 0x4000>;
547 clocks = <&gcc GCC_QUPV3_SPI1_CLK>;
548 clock-names = "se";
549 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554 };
555
556 sdhc: mmc@7804000 {
557 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
558 reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
559 reg-names = "hc", "cqhci";
560
561 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
563 interrupt-names = "hc_irq", "pwr_irq";
564
565 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
566 <&gcc GCC_SDCC1_APPS_CLK>,
567 <&xo_board>;
568 clock-names = "iface", "core", "xo";
569
570 supports-cqe;
571
572 status = "disabled";
573 };
574
575 intc: interrupt-controller@f200000 {
576 compatible = "arm,gic-v3";
577 reg = <0 0xf200000 0 0x10000>, /* GICD */
578 <0 0xf240000 0 0x80000>; /* GICR * 4 regions */
579 #address-cells = <0>;
580 #interrupt-cells = <0x3>;
581 interrupt-controller;
582 #redistributor-regions = <1>;
583 redistributor-stride = <0x0 0x20000>;
584 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
585 mbi-ranges = <672 128>;
586 msi-controller;
587 };
588
589 watchdog@f410000 {
590 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt";
591 reg = <0 0x0f410000 0 0x1000>;
592 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
593 clocks = <&sleep_clk>;
594 };
595
596 qusb_phy_1: phy@71000 {
597 compatible = "qcom,ipq5424-qusb2-phy";
598 reg = <0 0x00071000 0 0x180>;
599 #phy-cells = <0>;
600
601 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
602 <&xo_board>;
603 clock-names = "cfg_ahb", "ref";
604
605 resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
606 status = "disabled";
607 };
608
609 usb2: usb2@1e00000 {
610 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
611 reg = <0 0x01ef8800 0 0x400>;
612 #address-cells = <2>;
613 #size-cells = <2>;
614 ranges;
615
616 clocks = <&gcc GCC_USB1_MASTER_CLK>,
617 <&gcc GCC_USB1_SLEEP_CLK>,
618 <&gcc GCC_USB1_MOCK_UTMI_CLK>,
619 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
620 <&gcc GCC_CNOC_USB_CLK>;
621
622 clock-names = "core",
623 "sleep",
624 "mock_utmi",
625 "iface",
626 "cfg_noc";
627
628 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
629 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
630 assigned-clock-rates = <200000000>,
631 <24000000>;
632
633 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
634 <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
635 <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
636 <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
637 interrupt-names = "pwr_event",
638 "qusb2_phy",
639 "dm_hs_phy_irq",
640 "dp_hs_phy_irq";
641
642 resets = <&gcc GCC_USB1_BCR>;
643 qcom,select-utmi-as-pipe-clk;
644 status = "disabled";
645
646 dwc_1: usb@1e00000 {
647 compatible = "snps,dwc3";
648 reg = <0 0x01e00000 0 0xe000>;
649 clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>;
650 clock-names = "ref";
651 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
652 phys = <&qusb_phy_1>;
653 phy-names = "usb2-phy";
654 tx-fifo-resize;
655 snps,is-utmi-l1-suspend;
656 snps,hird-threshold = /bits/ 8 <0x0>;
657 snps,dis_u2_susphy_quirk;
658 snps,dis_u3_susphy_quirk;
659 };
660 };
661
662 qusb_phy_0: phy@7b000 {
663 compatible = "qcom,ipq5424-qusb2-phy";
664 reg = <0 0x0007b000 0 0x180>;
665 #phy-cells = <0>;
666
667 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
668 <&xo_board>;
669 clock-names = "cfg_ahb", "ref";
670
671 resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
672 status = "disabled";
673 };
674
675 ssphy_0: phy@7d000 {
676 compatible = "qcom,ipq5424-qmp-usb3-phy";
677 reg = <0 0x0007d000 0 0xa00>;
678 #phy-cells = <0>;
679
680 clocks = <&gcc GCC_USB0_AUX_CLK>,
681 <&xo_board>,
682 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
683 <&gcc GCC_USB0_PIPE_CLK>;
684 clock-names = "aux",
685 "ref",
686 "cfg_ahb",
687 "pipe";
688
689 resets = <&gcc GCC_USB0_PHY_BCR>,
690 <&gcc GCC_USB3PHY_0_PHY_BCR>;
691 reset-names = "phy",
692 "phy_phy";
693
694 #clock-cells = <0>;
695 clock-output-names = "usb0_pipe_clk";
696
697 status = "disabled";
698 };
699
700 usb3: usb3@8a00000 {
701 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3";
702 reg = <0 0x08af8800 0 0x400>;
703
704 #address-cells = <2>;
705 #size-cells = <2>;
706 ranges;
707
708 clocks = <&gcc GCC_USB0_MASTER_CLK>,
709 <&gcc GCC_USB0_SLEEP_CLK>,
710 <&gcc GCC_USB0_MOCK_UTMI_CLK>,
711 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
712 <&gcc GCC_CNOC_USB_CLK>;
713
714 clock-names = "core",
715 "sleep",
716 "mock_utmi",
717 "iface",
718 "cfg_noc";
719
720 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
721 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
722 assigned-clock-rates = <200000000>,
723 <24000000>;
724
725 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
726 <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
727 <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
728 <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
729 interrupt-names = "pwr_event",
730 "qusb2_phy",
731 "dm_hs_phy_irq",
732 "dp_hs_phy_irq";
733
734 resets = <&gcc GCC_USB_BCR>;
735 status = "disabled";
736
737 dwc_0: usb@8a00000 {
738 compatible = "snps,dwc3";
739 reg = <0 0x08a00000 0 0xcd00>;
740 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
741 clock-names = "ref";
742 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
743 phys = <&qusb_phy_0>, <&ssphy_0>;
744 phy-names = "usb2-phy", "usb3-phy";
745 tx-fifo-resize;
746 snps,is-utmi-l1-suspend;
747 snps,hird-threshold = /bits/ 8 <0x0>;
748 snps,dis_u2_susphy_quirk;
749 snps,dis_u3_susphy_quirk;
750 snps,dis-u1-entry-quirk;
751 snps,dis-u2-entry-quirk;
752 };
753 };
754
755 timer@f420000 {
756 compatible = "arm,armv7-timer-mem";
757 reg = <0 0xf420000 0 0x1000>;
758 ranges = <0 0 0 0x10000000>;
759 #address-cells = <1>;
760 #size-cells = <1>;
761
762 frame@f421000 {
763 reg = <0xf421000 0x1000>,
764 <0xf422000 0x1000>;
765 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
767 frame-number = <0>;
768 };
769
770 frame@f423000 {
771 reg = <0xf423000 0x1000>;
772 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
773 frame-number = <1>;
774 status = "disabled";
775 };
776
777 frame@f425000 {
778 reg = <0xf425000 0x1000>,
779 <0xf426000 0x1000>;
780 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
781 frame-number = <2>;
782 status = "disabled";
783 };
784
785 frame@f427000 {
786 reg = <0xf427000 0x1000>;
787 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
788 frame-number = <3>;
789 status = "disabled";
790 };
791
792 frame@f429000 {
793 reg = <0xf429000 0x1000>;
794 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
795 frame-number = <4>;
796 status = "disabled";
797 };
798
799 frame@f42b000 {
800 reg = <0xf42b000 0x1000>;
801 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
802 frame-number = <5>;
803 status = "disabled";
804 };
805
806 frame@f42d000 {
807 reg = <0xf42d000 0x1000>;
808 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
809 frame-number = <6>;
810 status = "disabled";
811 };
812 };
813
814 apss_clk: clock-controller@fa80000 {
815 compatible = "qcom,ipq5424-apss-clk";
816 reg = <0x0 0x0fa80000 0x0 0x20000>;
817 clocks = <&xo_board>,
818 <&gcc GPLL0>;
819 #clock-cells = <1>;
820 #interconnect-cells = <1>;
821 };
822
823 clock-controller@39b00000 {
824 compatible = "qcom,ipq5424-nsscc";
825 reg = <0 0x39b00000 0 0x100000>;
826 clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>,
827 <&cmn_pll IPQ5424_NSS_300MHZ_CLK>,
828 <&cmn_pll IPQ5424_PPE_375MHZ_CLK>,
829 <&gcc GPLL0_OUT_AUX>,
830 <0>,
831 <0>,
832 <0>,
833 <0>,
834 <0>,
835 <0>,
836 <&gcc GCC_NSSCC_CLK>;
837 clock-names = "xo",
838 "nss",
839 "ppe",
840 "gpll0_out",
841 "uniphy0_rx",
842 "uniphy0_tx",
843 "uniphy1_rx",
844 "uniphy1_tx",
845 "uniphy2_rx",
846 "uniphy2_tx",
847 "bus";
848 #clock-cells = <1>;
849 #reset-cells = <1>;
850 #interconnect-cells = <1>;
851 };
852
853 pcie3: pcie@40000000 {
854 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
855 reg = <0x0 0x40000000 0x0 0xf1c>,
856 <0x0 0x40000f20 0x0 0xa8>,
857 <0x0 0x40001000 0x0 0x1000>,
858 <0x0 0x000f8000 0x0 0x3000>,
859 <0x0 0x40100000 0x0 0x1000>,
860 <0x0 0x000fe000 0x0 0x1000>;
861 reg-names = "dbi",
862 "elbi",
863 "atu",
864 "parf",
865 "config",
866 "mhi";
867 device_type = "pci";
868 linux,pci-domain = <3>;
869 num-lanes = <2>;
870 #address-cells = <3>;
871 #size-cells = <2>;
872
873 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>,
874 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>;
875
876 msi-map = <0x0 &intc 0x0 0x1000>;
877
878 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
879 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
887
888 interrupt-names = "msi0",
889 "msi1",
890 "msi2",
891 "msi3",
892 "msi4",
893 "msi5",
894 "msi6",
895 "msi7",
896 "global";
897
898 #interrupt-cells = <1>;
899 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
900 interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
901 <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>,
902 <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
903 <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>;
904
905 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>,
906 <&gcc GCC_PCIE3_AXI_S_CLK>,
907 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>,
908 <&gcc GCC_PCIE3_RCHNG_CLK>,
909 <&gcc GCC_PCIE3_AHB_CLK>,
910 <&gcc GCC_PCIE3_AUX_CLK>;
911 clock-names = "axi_m",
912 "axi_s",
913 "axi_bridge",
914 "rchng",
915 "ahb",
916 "aux";
917
918 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>;
919 assigned-clock-rates = <100000000>;
920
921 resets = <&gcc GCC_PCIE3_PIPE_ARES>,
922 <&gcc GCC_PCIE3_CORE_STICKY_RESET>,
923 <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>,
924 <&gcc GCC_PCIE3_AXI_S_ARES>,
925 <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>,
926 <&gcc GCC_PCIE3_AXI_M_ARES>,
927 <&gcc GCC_PCIE3_AUX_ARES>,
928 <&gcc GCC_PCIE3_AHB_ARES>;
929 reset-names = "pipe",
930 "sticky",
931 "axi_s_sticky",
932 "axi_s",
933 "axi_m_sticky",
934 "axi_m",
935 "aux",
936 "ahb";
937
938 phys = <&pcie3_phy>;
939 phy-names = "pciephy";
940 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
941 <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
942 interconnect-names = "pcie-mem", "cpu-pcie";
943
944 status = "disabled";
945
946 pcie@0 {
947 device_type = "pci";
948 reg = <0x0 0x0 0x0 0x0 0x0>;
949 bus-range = <0x01 0xff>;
950
951 #address-cells = <3>;
952 #size-cells = <2>;
953 ranges;
954 };
955 };
956
957 pcie2: pcie@50000000 {
958 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
959 reg = <0x0 0x50000000 0x0 0xf1c>,
960 <0x0 0x50000f20 0x0 0xa8>,
961 <0x0 0x50001000 0x0 0x1000>,
962 <0x0 0x000f0000 0x0 0x3000>,
963 <0x0 0x50100000 0x0 0x1000>,
964 <0x0 0x000f6000 0x0 0x1000>;
965 reg-names = "dbi",
966 "elbi",
967 "atu",
968 "parf",
969 "config",
970 "mhi";
971 device_type = "pci";
972 linux,pci-domain = <2>;
973 num-lanes = <2>;
974 #address-cells = <3>;
975 #size-cells = <2>;
976
977 ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>,
978 <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>;
979
980 msi-map = <0x0 &intc 0x0 0x1000>;
981
982 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "msi0",
992 "msi1",
993 "msi2",
994 "msi3",
995 "msi4",
996 "msi5",
997 "msi6",
998 "msi7",
999 "global";
1000
1001 #interrupt-cells = <1>;
1002 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1003 interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
1004 <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
1005 <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
1006 <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1007
1008 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>,
1009 <&gcc GCC_PCIE2_AXI_S_CLK>,
1010 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>,
1011 <&gcc GCC_PCIE2_RCHNG_CLK>,
1012 <&gcc GCC_PCIE2_AHB_CLK>,
1013 <&gcc GCC_PCIE2_AUX_CLK>;
1014 clock-names = "axi_m",
1015 "axi_s",
1016 "axi_bridge",
1017 "rchng",
1018 "ahb",
1019 "aux";
1020
1021 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>;
1022 assigned-clock-rates = <100000000>;
1023
1024 resets = <&gcc GCC_PCIE2_PIPE_ARES>,
1025 <&gcc GCC_PCIE2_CORE_STICKY_RESET>,
1026 <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>,
1027 <&gcc GCC_PCIE2_AXI_S_ARES>,
1028 <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>,
1029 <&gcc GCC_PCIE2_AXI_M_ARES>,
1030 <&gcc GCC_PCIE2_AUX_ARES>,
1031 <&gcc GCC_PCIE2_AHB_ARES>;
1032 reset-names = "pipe",
1033 "sticky",
1034 "axi_s_sticky",
1035 "axi_s",
1036 "axi_m_sticky",
1037 "axi_m",
1038 "aux",
1039 "ahb";
1040
1041 phys = <&pcie2_phy>;
1042 phy-names = "pciephy";
1043 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>,
1044 <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>;
1045 interconnect-names = "pcie-mem", "cpu-pcie";
1046
1047 status = "disabled";
1048
1049 pcie@0 {
1050 device_type = "pci";
1051 reg = <0x0 0x0 0x0 0x0 0x0>;
1052 bus-range = <0x01 0xff>;
1053
1054 #address-cells = <3>;
1055 #size-cells = <2>;
1056 ranges;
1057 };
1058 };
1059
1060 pcie1: pcie@60000000 {
1061 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
1062 reg = <0x0 0x60000000 0x0 0xf1c>,
1063 <0x0 0x60000f20 0x0 0xa8>,
1064 <0x0 0x60001000 0x0 0x1000>,
1065 <0x0 0x00088000 0x0 0x3000>,
1066 <0x0 0x60100000 0x0 0x1000>,
1067 <0x0 0x0008e000 0x0 0x1000>;
1068 reg-names = "dbi",
1069 "elbi",
1070 "atu",
1071 "parf",
1072 "config",
1073 "mhi";
1074 device_type = "pci";
1075 linux,pci-domain = <1>;
1076 num-lanes = <1>;
1077 #address-cells = <3>;
1078 #size-cells = <2>;
1079
1080 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>,
1081 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>;
1082
1083 msi-map = <0x0 &intc 0x0 0x1000>;
1084
1085 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
1086 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
1087 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
1094 interrupt-names = "msi0",
1095 "msi1",
1096 "msi2",
1097 "msi3",
1098 "msi4",
1099 "msi5",
1100 "msi6",
1101 "msi7",
1102 "global";
1103
1104 #interrupt-cells = <1>;
1105 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1106 interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
1107 <0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
1108 <0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
1109 <0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
1110
1111 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>,
1112 <&gcc GCC_PCIE1_AXI_S_CLK>,
1113 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>,
1114 <&gcc GCC_PCIE1_RCHNG_CLK>,
1115 <&gcc GCC_PCIE1_AHB_CLK>,
1116 <&gcc GCC_PCIE1_AUX_CLK>;
1117 clock-names = "axi_m",
1118 "axi_s",
1119 "axi_bridge",
1120 "rchng",
1121 "ahb",
1122 "aux";
1123
1124 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>;
1125 assigned-clock-rates = <100000000>;
1126
1127 resets = <&gcc GCC_PCIE1_PIPE_ARES>,
1128 <&gcc GCC_PCIE1_CORE_STICKY_RESET>,
1129 <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>,
1130 <&gcc GCC_PCIE1_AXI_S_ARES>,
1131 <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>,
1132 <&gcc GCC_PCIE1_AXI_M_ARES>,
1133 <&gcc GCC_PCIE1_AUX_ARES>,
1134 <&gcc GCC_PCIE1_AHB_ARES>;
1135 reset-names = "pipe",
1136 "sticky",
1137 "axi_s_sticky",
1138 "axi_s",
1139 "axi_m_sticky",
1140 "axi_m",
1141 "aux",
1142 "ahb";
1143
1144 phys = <&pcie1_phy>;
1145 phy-names = "pciephy";
1146 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>,
1147 <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>;
1148 interconnect-names = "pcie-mem", "cpu-pcie";
1149
1150 status = "disabled";
1151
1152 pcie@0 {
1153 device_type = "pci";
1154 reg = <0x0 0x0 0x0 0x0 0x0>;
1155 bus-range = <0x01 0xff>;
1156
1157 #address-cells = <3>;
1158 #size-cells = <2>;
1159 ranges;
1160 };
1161 };
1162
1163 pcie0: pcie@70000000 {
1164 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
1165 reg = <0x0 0x70000000 0x0 0xf1c>,
1166 <0x0 0x70000f20 0x0 0xa8>,
1167 <0x0 0x70001000 0x0 0x1000>,
1168 <0x0 0x00080000 0x0 0x3000>,
1169 <0x0 0x70100000 0x0 0x1000>,
1170 <0x0 0x00086000 0x0 0x1000>;
1171 reg-names = "dbi",
1172 "elbi",
1173 "atu",
1174 "parf",
1175 "config",
1176 "mhi";
1177 device_type = "pci";
1178 linux,pci-domain = <0>;
1179 num-lanes = <1>;
1180 #address-cells = <3>;
1181 #size-cells = <2>;
1182
1183 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>,
1184 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>;
1185
1186 msi-map = <0x0 &intc 0x0 0x1000>;
1187
1188 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1197 interrupt-names = "msi0",
1198 "msi1",
1199 "msi2",
1200 "msi3",
1201 "msi4",
1202 "msi5",
1203 "msi6",
1204 "msi7",
1205 "global";
1206
1207 #interrupt-cells = <1>;
1208 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1209 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1210 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1211 <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
1212 <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
1213
1214 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>,
1215 <&gcc GCC_PCIE0_AXI_S_CLK>,
1216 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
1217 <&gcc GCC_PCIE0_RCHNG_CLK>,
1218 <&gcc GCC_PCIE0_AHB_CLK>,
1219 <&gcc GCC_PCIE0_AUX_CLK>;
1220 clock-names = "axi_m",
1221 "axi_s",
1222 "axi_bridge",
1223 "rchng",
1224 "ahb",
1225 "aux";
1226
1227 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>;
1228 assigned-clock-rates = <100000000>;
1229
1230 resets = <&gcc GCC_PCIE0_PIPE_ARES>,
1231 <&gcc GCC_PCIE0_CORE_STICKY_RESET>,
1232 <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>,
1233 <&gcc GCC_PCIE0_AXI_S_ARES>,
1234 <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>,
1235 <&gcc GCC_PCIE0_AXI_M_ARES>,
1236 <&gcc GCC_PCIE0_AUX_ARES>,
1237 <&gcc GCC_PCIE0_AHB_ARES>;
1238 reset-names = "pipe",
1239 "sticky",
1240 "axi_s_sticky",
1241 "axi_s",
1242 "axi_m_sticky",
1243 "axi_m",
1244 "aux",
1245 "ahb";
1246
1247 phys = <&pcie0_phy>;
1248 phy-names = "pciephy";
1249 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>,
1250 <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>;
1251 interconnect-names = "pcie-mem", "cpu-pcie";
1252
1253 status = "disabled";
1254
1255 pcie@0 {
1256 device_type = "pci";
1257 reg = <0x0 0x0 0x0 0x0 0x0>;
1258 bus-range = <0x01 0xff>;
1259
1260 #address-cells = <3>;
1261 #size-cells = <2>;
1262 ranges;
1263 };
1264 };
1265 };
1266
1267 thermal_zones: thermal-zones {
1268 cpu0-thermal {
1269 polling-delay-passive = <100>;
1270 thermal-sensors = <&tsens 14>;
1271
1272 trips {
1273 cpu0_crit: cpu-critical {
1274 temperature = <120000>;
1275 hysteresis = <9000>;
1276 type = "critical";
1277 };
1278
1279 cpu0_alert: cpu-passive {
1280 temperature = <110000>;
1281 hysteresis = <9000>;
1282 type = "passive";
1283 };
1284 };
1285
1286 cooling-maps {
1287 map0 {
1288 trip = <&cpu0_alert>;
1289 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1290 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1291 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1292 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1293 };
1294 };
1295 };
1296
1297 cpu1-thermal {
1298 polling-delay-passive = <100>;
1299 thermal-sensors = <&tsens 12>;
1300
1301 trips {
1302 cpu1_crit: cpu-critical {
1303 temperature = <120000>;
1304 hysteresis = <9000>;
1305 type = "critical";
1306 };
1307
1308 cpu1_alert: cpu-passive {
1309 temperature = <110000>;
1310 hysteresis = <9000>;
1311 type = "passive";
1312 };
1313 };
1314
1315 cooling-maps {
1316 map0 {
1317 trip = <&cpu1_alert>;
1318 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1319 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1320 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1321 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1322 };
1323 };
1324 };
1325
1326 cpu2-thermal {
1327 polling-delay-passive = <100>;
1328 thermal-sensors = <&tsens 11>;
1329
1330 trips {
1331 cpu2_crit: cpu-critical {
1332 temperature = <120000>;
1333 hysteresis = <9000>;
1334 type = "critical";
1335 };
1336
1337 cpu2_alert: cpu-passive {
1338 temperature = <110000>;
1339 hysteresis = <9000>;
1340 type = "passive";
1341 };
1342 };
1343
1344 cooling-maps {
1345 map0 {
1346 trip = <&cpu2_alert>;
1347 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1348 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1349 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1350 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1351 };
1352 };
1353 };
1354
1355 cpu3-thermal {
1356 polling-delay-passive = <100>;
1357 thermal-sensors = <&tsens 13>;
1358
1359 trips {
1360 cpu3_crit: cpu-critical {
1361 temperature = <120000>;
1362 hysteresis = <9000>;
1363 type = "critical";
1364 };
1365
1366 cpu3_alert: cpu-passive {
1367 temperature = <110000>;
1368 hysteresis = <9000>;
1369 type = "passive";
1370 };
1371 };
1372
1373 cooling-maps {
1374 map0 {
1375 trip = <&cpu3_alert>;
1376 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1377 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1378 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1379 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1380 };
1381 };
1382 };
1383
1384 wcss-tile2-thermal {
1385 thermal-sensors = <&tsens 9>;
1386
1387 trips {
1388 wcss-tile2-critical {
1389 temperature = <125000>;
1390 hysteresis = <9000>;
1391 type = "critical";
1392 };
1393 };
1394 };
1395
1396 wcss-tile3-thermal {
1397 thermal-sensors = <&tsens 10>;
1398
1399 trips {
1400 wcss-tile3-critical {
1401 temperature = <125000>;
1402 hysteresis = <9000>;
1403 type = "critical";
1404 };
1405 };
1406 };
1407
1408 top-glue-thermal {
1409 thermal-sensors = <&tsens 15>;
1410
1411 trips {
1412 top-glue-critical {
1413 temperature = <125000>;
1414 hysteresis = <9000>;
1415 type = "critical";
1416 };
1417 };
1418 };
1419 };
1420
1421 timer {
1422 compatible = "arm,armv8-timer";
1423 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1424 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1425 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1426 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1427 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1428 };
1429};