tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019, Intel Corporation
4 */
5
6/dts-v1/;
7#include <dt-bindings/reset/altr,rst-mgr-s10.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/agilex-clock.h>
11
12/ {
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
20 ranges;
21
22 service_reserved: svcbuffer@0 {
23 compatible = "shared-dma-pool";
24 reg = <0x0 0x0 0x0 0x2000000>;
25 alignment = <0x1000>;
26 no-map;
27 };
28 };
29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 compatible = "arm,cortex-a53";
36 device_type = "cpu";
37 enable-method = "psci";
38 reg = <0x0>;
39 };
40
41 cpu1: cpu@1 {
42 compatible = "arm,cortex-a53";
43 device_type = "cpu";
44 enable-method = "psci";
45 reg = <0x1>;
46 };
47
48 cpu2: cpu@2 {
49 compatible = "arm,cortex-a53";
50 device_type = "cpu";
51 enable-method = "psci";
52 reg = <0x2>;
53 };
54
55 cpu3: cpu@3 {
56 compatible = "arm,cortex-a53";
57 device_type = "cpu";
58 enable-method = "psci";
59 reg = <0x3>;
60 };
61 };
62
63 firmware {
64 svc {
65 compatible = "intel,agilex-svc";
66 method = "smc";
67 memory-region = <&service_reserved>;
68
69 fpga_mgr: fpga-mgr {
70 compatible = "intel,agilex-soc-fpga-mgr";
71 };
72 };
73 };
74
75 fpga-region {
76 compatible = "fpga-region";
77 #address-cells = <0x2>;
78 #size-cells = <0x2>;
79 fpga-mgr = <&fpga_mgr>;
80 };
81
82 pmu {
83 compatible = "arm,cortex-a53-pmu";
84 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
88 interrupt-affinity = <&cpu0>,
89 <&cpu1>,
90 <&cpu2>,
91 <&cpu3>;
92 interrupt-parent = <&intc>;
93 };
94
95 psci {
96 compatible = "arm,psci-0.2";
97 method = "smc";
98 };
99
100 intc: interrupt-controller@fffc1000 {
101 compatible = "arm,gic-400", "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&intc>;
105 reg = <0x0 0xfffc1000 0x0 0x1000>,
106 <0x0 0xfffc2000 0x0 0x2000>,
107 <0x0 0xfffc4000 0x0 0x2000>,
108 <0x0 0xfffc6000 0x0 0x2000>;
109 /* VGIC maintenance interrupt */
110 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
111 };
112
113 clocks {
114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
117 clock-frequency = <200000000>;
118 };
119
120 cb_intosc_ls_clk: cb-intosc-ls-clk {
121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 clock-frequency = <400000000>;
124 };
125
126 f2s_free_clk: f2s-free-clk {
127 #clock-cells = <0>;
128 compatible = "fixed-clock";
129 clock-frequency = <100000000>;
130 };
131
132 osc1: osc1 {
133 #clock-cells = <0>;
134 compatible = "fixed-clock";
135 };
136
137 qspi_clk: qspi-clk {
138 #clock-cells = <0>;
139 compatible = "fixed-clock";
140 clock-frequency = <200000000>;
141 };
142 };
143
144 timer {
145 compatible = "arm,armv8-timer";
146 interrupt-parent = <&intc>;
147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
151 };
152
153 usbphy0: usbphy {
154 #phy-cells = <0>;
155 compatible = "usb-nop-xceiv";
156 };
157
158 soc@0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "simple-bus";
162 device_type = "soc";
163 interrupt-parent = <&intc>;
164 ranges = <0 0 0 0xffffffff>;
165
166 clkmgr: clock-controller@ffd10000 {
167 compatible = "intel,agilex-clkmgr";
168 reg = <0xffd10000 0x1000>;
169 #clock-cells = <1>;
170 clocks = <&osc1>;
171 };
172
173 gmac0: ethernet@ff800000 {
174 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
175 reg = <0xff800000 0x2000>;
176 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "macirq";
178 mac-address = [00 00 00 00 00 00];
179 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
180 reset-names = "stmmaceth", "ahb";
181 tx-fifo-depth = <16384>;
182 rx-fifo-depth = <16384>;
183 snps,multicast-filter-bins = <256>;
184 iommus = <&smmu 1>;
185 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
186 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
187 clock-names = "stmmaceth", "ptp_ref";
188 status = "disabled";
189 };
190
191 gmac1: ethernet@ff802000 {
192 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
193 reg = <0xff802000 0x2000>;
194 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
195 interrupt-names = "macirq";
196 mac-address = [00 00 00 00 00 00];
197 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
198 reset-names = "stmmaceth", "ahb";
199 tx-fifo-depth = <16384>;
200 rx-fifo-depth = <16384>;
201 snps,multicast-filter-bins = <256>;
202 iommus = <&smmu 2>;
203 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
204 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
205 clock-names = "stmmaceth", "ptp_ref";
206 status = "disabled";
207 };
208
209 gmac2: ethernet@ff804000 {
210 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
211 reg = <0xff804000 0x2000>;
212 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
213 interrupt-names = "macirq";
214 mac-address = [00 00 00 00 00 00];
215 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
216 reset-names = "stmmaceth", "ahb";
217 tx-fifo-depth = <16384>;
218 rx-fifo-depth = <16384>;
219 snps,multicast-filter-bins = <256>;
220 iommus = <&smmu 3>;
221 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
222 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>;
223 clock-names = "stmmaceth", "ptp_ref";
224 status = "disabled";
225 };
226
227 gpio0: gpio@ffc03200 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "snps,dw-apb-gpio";
231 reg = <0xffc03200 0x100>;
232 resets = <&rst GPIO0_RESET>;
233 status = "disabled";
234
235 porta: gpio-controller@0 {
236 compatible = "snps,dw-apb-gpio-port";
237 gpio-controller;
238 #gpio-cells = <2>;
239 snps,nr-gpios = <24>;
240 reg = <0>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
244 };
245 };
246
247 gpio1: gpio@ffc03300 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "snps,dw-apb-gpio";
251 reg = <0xffc03300 0x100>;
252 resets = <&rst GPIO1_RESET>;
253 status = "disabled";
254
255 portb: gpio-controller@0 {
256 compatible = "snps,dw-apb-gpio-port";
257 gpio-controller;
258 #gpio-cells = <2>;
259 snps,nr-gpios = <24>;
260 reg = <0>;
261 interrupt-controller;
262 #interrupt-cells = <2>;
263 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
264 };
265 };
266
267 i2c0: i2c@ffc02800 {
268 #address-cells = <1>;
269 #size-cells = <0>;
270 compatible = "snps,designware-i2c";
271 reg = <0xffc02800 0x100>;
272 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
273 resets = <&rst I2C0_RESET>;
274 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
275 status = "disabled";
276 };
277
278 i2c1: i2c@ffc02900 {
279 #address-cells = <1>;
280 #size-cells = <0>;
281 compatible = "snps,designware-i2c";
282 reg = <0xffc02900 0x100>;
283 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
284 resets = <&rst I2C1_RESET>;
285 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
286 status = "disabled";
287 };
288
289 i2c2: i2c@ffc02a00 {
290 #address-cells = <1>;
291 #size-cells = <0>;
292 compatible = "snps,designware-i2c";
293 reg = <0xffc02a00 0x100>;
294 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
295 resets = <&rst I2C2_RESET>;
296 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
297 status = "disabled";
298 };
299
300 i2c3: i2c@ffc02b00 {
301 #address-cells = <1>;
302 #size-cells = <0>;
303 compatible = "snps,designware-i2c";
304 reg = <0xffc02b00 0x100>;
305 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
306 resets = <&rst I2C3_RESET>;
307 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
308 status = "disabled";
309 };
310
311 i2c4: i2c@ffc02c00 {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 compatible = "snps,designware-i2c";
315 reg = <0xffc02c00 0x100>;
316 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
317 resets = <&rst I2C4_RESET>;
318 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
319 status = "disabled";
320 };
321
322 mmc: mmc@ff808000 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "altr,socfpga-dw-mshc";
326 reg = <0xff808000 0x1000>;
327 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
328 fifo-depth = <0x400>;
329 resets = <&rst SDMMC_RESET>;
330 reset-names = "reset";
331 clocks = <&clkmgr AGILEX_L4_MP_CLK>,
332 <&clkmgr AGILEX_SDMMC_CLK>;
333 clock-names = "biu", "ciu";
334 iommus = <&smmu 5>;
335 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
336 status = "disabled";
337 };
338
339 nand: nand-controller@ffb90000 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 compatible = "altr,socfpga-denali-nand";
343 reg = <0xffb90000 0x10000>,
344 <0xffb80000 0x1000>;
345 reg-names = "nand_data", "denali_reg";
346 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&clkmgr AGILEX_NAND_CLK>,
348 <&clkmgr AGILEX_NAND_X_CLK>,
349 <&clkmgr AGILEX_NAND_ECC_CLK>;
350 clock-names = "nand", "nand_x", "ecc";
351 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>;
352 status = "disabled";
353 };
354
355 ocram: sram@ffe00000 {
356 compatible = "mmio-sram";
357 reg = <0xffe00000 0x40000>;
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges = <0 0xffe00000 0x40000>;
361 };
362
363 pdma: dma-controller@ffda0000 {
364 compatible = "arm,pl330", "arm,primecell";
365 reg = <0xffda0000 0x1000>;
366 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
375 #dma-cells = <1>;
376 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
377 reset-names = "dma", "dma-ocp";
378 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
379 clock-names = "apb_pclk";
380 };
381
382 pinctrl0: pinctrl@ffd13000 {
383 compatible = "pinctrl-single";
384 #pinctrl-cells = <1>;
385 reg = <0xffd13000 0xa0>;
386 pinctrl-single,register-width = <32>;
387 pinctrl-single,function-mask = <0x0000000f>;
388 };
389
390 pinctrl1: pinctrl@ffd13100 {
391 compatible = "pinctrl-single";
392 #pinctrl-cells = <1>;
393 reg = <0xffd13100 0x20>;
394 pinctrl-single,register-width = <32>;
395 };
396
397 rst: rstmgr@ffd11000 {
398 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
399 reg = <0xffd11000 0x100>;
400 #reset-cells = <1>;
401 };
402
403 smmu: iommu@fa000000 {
404 compatible = "arm,mmu-500", "arm,smmu-v2";
405 reg = <0xfa000000 0x40000>;
406 #global-interrupts = <2>;
407 #iommu-cells = <1>;
408 interrupt-parent = <&intc>;
409 /* Global Secure Fault */
410 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
411 /* Global Non-secure Fault */
412 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
413 /* Non-secure Context Interrupts (32) */
414 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
446 stream-match-mask = <0x7ff0>;
447 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
448 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
449 <&clkmgr AGILEX_L4_MAIN_CLK>;
450 status = "disabled";
451 };
452
453 spi0: spi@ffda4000 {
454 compatible = "snps,dw-apb-ssi";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 reg = <0xffda4000 0x1000>;
458 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
459 resets = <&rst SPIM0_RESET>;
460 reset-names = "spi";
461 reg-io-width = <4>;
462 num-cs = <4>;
463 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
464 dmas = <&pdma 16>, <&pdma 17>;
465 dma-names = "tx", "rx";
466 status = "disabled";
467 };
468
469 spi1: spi@ffda5000 {
470 compatible = "snps,dw-apb-ssi";
471 #address-cells = <1>;
472 #size-cells = <0>;
473 reg = <0xffda5000 0x1000>;
474 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
475 resets = <&rst SPIM1_RESET>;
476 reset-names = "spi";
477 reg-io-width = <4>;
478 num-cs = <4>;
479 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
480 dmas = <&pdma 20>, <&pdma 21>;
481 dma-names = "tx", "rx";
482 status = "disabled";
483 };
484
485 sysmgr: sysmgr@ffd12000 {
486 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
487 reg = <0xffd12000 0x500>;
488 };
489
490 timer0: timer0@ffc03000 {
491 compatible = "snps,dw-apb-timer";
492 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
493 reg = <0xffc03000 0x100>;
494 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
495 clock-names = "timer";
496 };
497
498 timer1: timer1@ffc03100 {
499 compatible = "snps,dw-apb-timer";
500 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
501 reg = <0xffc03100 0x100>;
502 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
503 clock-names = "timer";
504 };
505
506 timer2: timer2@ffd00000 {
507 compatible = "snps,dw-apb-timer";
508 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
509 reg = <0xffd00000 0x100>;
510 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
511 clock-names = "timer";
512 };
513
514 timer3: timer3@ffd00100 {
515 compatible = "snps,dw-apb-timer";
516 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
517 reg = <0xffd00100 0x100>;
518 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
519 clock-names = "timer";
520 };
521
522 uart0: serial@ffc02000 {
523 compatible = "snps,dw-apb-uart";
524 reg = <0xffc02000 0x100>;
525 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
526 reg-shift = <2>;
527 reg-io-width = <4>;
528 resets = <&rst UART0_RESET>;
529 status = "disabled";
530 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
531 };
532
533 uart1: serial@ffc02100 {
534 compatible = "snps,dw-apb-uart";
535 reg = <0xffc02100 0x100>;
536 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
537 reg-shift = <2>;
538 reg-io-width = <4>;
539 resets = <&rst UART1_RESET>;
540 clocks = <&clkmgr AGILEX_L4_SP_CLK>;
541 status = "disabled";
542 };
543
544 usb0: usb@ffb00000 {
545 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
546 reg = <0xffb00000 0x40000>;
547 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
548 phys = <&usbphy0>;
549 phy-names = "usb2-phy";
550 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
551 reset-names = "dwc2", "dwc2-ecc";
552 clocks = <&clkmgr AGILEX_USB_CLK>;
553 clock-names = "otg";
554 iommus = <&smmu 6>;
555 status = "disabled";
556 };
557
558 usb1: usb@ffb40000 {
559 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
560 reg = <0xffb40000 0x40000>;
561 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
562 phys = <&usbphy0>;
563 phy-names = "usb2-phy";
564 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
565 reset-names = "dwc2", "dwc2-ecc";
566 iommus = <&smmu 7>;
567 clocks = <&clkmgr AGILEX_USB_CLK>;
568 status = "disabled";
569 };
570
571 watchdog0: watchdog@ffd00200 {
572 compatible = "snps,dw-wdt";
573 reg = <0xffd00200 0x100>;
574 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
575 resets = <&rst WATCHDOG0_RESET>;
576 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
577 status = "disabled";
578 };
579
580 watchdog1: watchdog@ffd00300 {
581 compatible = "snps,dw-wdt";
582 reg = <0xffd00300 0x100>;
583 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
584 resets = <&rst WATCHDOG1_RESET>;
585 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
586 status = "disabled";
587 };
588
589 watchdog2: watchdog@ffd00400 {
590 compatible = "snps,dw-wdt";
591 reg = <0xffd00400 0x100>;
592 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
593 resets = <&rst WATCHDOG2_RESET>;
594 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
595 status = "disabled";
596 };
597
598 watchdog3: watchdog@ffd00500 {
599 compatible = "snps,dw-wdt";
600 reg = <0xffd00500 0x100>;
601 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
602 resets = <&rst WATCHDOG3_RESET>;
603 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
604 status = "disabled";
605 };
606
607 sdr: sdr@f8011100 {
608 compatible = "altr,sdr-ctl", "syscon";
609 reg = <0xf8011100 0xc0>;
610 };
611
612 eccmgr {
613 compatible = "altr,socfpga-s10-ecc-manager",
614 "altr,socfpga-a10-ecc-manager";
615 altr,sysmgr-syscon = <&sysmgr>;
616 #address-cells = <1>;
617 #size-cells = <1>;
618 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
619 interrupt-controller;
620 #interrupt-cells = <2>;
621 ranges;
622
623 sdramedac {
624 compatible = "altr,sdram-edac-s10";
625 altr,sdr-syscon = <&sdr>;
626 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
627 };
628
629 ocram-ecc@ff8cc000 {
630 compatible = "altr,socfpga-s10-ocram-ecc",
631 "altr,socfpga-a10-ocram-ecc";
632 reg = <0xff8cc000 0x100>;
633 altr,ecc-parent = <&ocram>;
634 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
635 };
636
637 usb0-ecc@ff8c4000 {
638 compatible = "altr,socfpga-s10-usb-ecc",
639 "altr,socfpga-usb-ecc";
640 reg = <0xff8c4000 0x100>;
641 altr,ecc-parent = <&usb0>;
642 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
643 };
644
645 emac0-rx-ecc@ff8c0000 {
646 compatible = "altr,socfpga-s10-eth-mac-ecc",
647 "altr,socfpga-eth-mac-ecc";
648 reg = <0xff8c0000 0x100>;
649 altr,ecc-parent = <&gmac0>;
650 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
651 };
652
653 emac0-tx-ecc@ff8c0400 {
654 compatible = "altr,socfpga-s10-eth-mac-ecc",
655 "altr,socfpga-eth-mac-ecc";
656 reg = <0xff8c0400 0x100>;
657 altr,ecc-parent = <&gmac0>;
658 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
659 };
660
661 sdmmca-ecc@ff8c8c00 {
662 compatible = "altr,socfpga-s10-sdmmc-ecc",
663 "altr,socfpga-sdmmc-ecc";
664 reg = <0xff8c8c00 0x100>;
665 altr,ecc-parent = <&mmc>;
666 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
667 <15 IRQ_TYPE_LEVEL_HIGH>;
668 };
669 };
670
671 qspi: spi@ff8d2000 {
672 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
673 #address-cells = <1>;
674 #size-cells = <0>;
675 reg = <0xff8d2000 0x100>,
676 <0xff900000 0x100000>;
677 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
678 cdns,fifo-depth = <128>;
679 cdns,fifo-width = <4>;
680 cdns,trigger-address = <0x00000000>;
681 clocks = <&qspi_clk>;
682
683 status = "disabled";
684 };
685 };
686};