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Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8/ {
9 interrupt-parent = <&gic>;
10
11 #address-cells = <2>;
12 #size-cells = <2>;
13
14 soc_refclk50mhz: clock-50000000 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <50000000>;
18 clock-output-names = "apb_pclk";
19 };
20
21 soc_refclk85mhz: clock-85000000 {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <85000000>;
25 clock-output-names = "iofpga:aclk";
26 };
27
28 cpus {
29 #address-cells = <2>;
30 #size-cells = <0>;
31
32 cpu0: cpu@0 {
33 compatible = "arm,rainier";
34 reg = <0x0 0x0>;
35 device_type = "cpu";
36 enable-method = "psci";
37 /* 4 ways set associative */
38 i-cache-size = <0x10000>;
39 i-cache-line-size = <64>;
40 i-cache-sets = <512>;
41 d-cache-size = <0x10000>;
42 d-cache-line-size = <64>;
43 d-cache-sets = <512>;
44 next-level-cache = <&l2_0>;
45 clocks = <&scmi_dvfs 0>;
46
47 l2_0: l2-cache {
48 compatible = "cache";
49 cache-level = <2>;
50 /* 8 ways set associative */
51 cache-size = <0x100000>;
52 cache-line-size = <64>;
53 cache-sets = <2048>;
54 cache-unified;
55 next-level-cache = <&l3_0>;
56 };
57 };
58
59 cpu1: cpu@100 {
60 compatible = "arm,rainier";
61 reg = <0x0 0x100>;
62 device_type = "cpu";
63 enable-method = "psci";
64 /* 4 ways set associative */
65 i-cache-size = <0x10000>;
66 i-cache-line-size = <64>;
67 i-cache-sets = <512>;
68 d-cache-size = <0x10000>;
69 d-cache-line-size = <64>;
70 d-cache-sets = <512>;
71 next-level-cache = <&l2_1>;
72 clocks = <&scmi_dvfs 0>;
73
74 l2_1: l2-cache {
75 compatible = "cache";
76 cache-level = <2>;
77 /* 8 ways set associative */
78 cache-size = <0x100000>;
79 cache-line-size = <64>;
80 cache-sets = <2048>;
81 cache-unified;
82 next-level-cache = <&l3_0>;
83 };
84 };
85
86 cpu2: cpu@10000 {
87 compatible = "arm,rainier";
88 reg = <0x0 0x10000>;
89 device_type = "cpu";
90 enable-method = "psci";
91 /* 4 ways set associative */
92 i-cache-size = <0x10000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <512>;
95 d-cache-size = <0x10000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <512>;
98 next-level-cache = <&l2_2>;
99 clocks = <&scmi_dvfs 1>;
100
101 l2_2: l2-cache {
102 compatible = "cache";
103 cache-level = <2>;
104 /* 8 ways set associative */
105 cache-size = <0x100000>;
106 cache-line-size = <64>;
107 cache-sets = <2048>;
108 cache-unified;
109 next-level-cache = <&l3_0>;
110 };
111 };
112
113 cpu3: cpu@10100 {
114 compatible = "arm,rainier";
115 reg = <0x0 0x10100>;
116 device_type = "cpu";
117 enable-method = "psci";
118 /* 4 ways set associative */
119 i-cache-size = <0x10000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <512>;
122 d-cache-size = <0x10000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <512>;
125 next-level-cache = <&l2_3>;
126 clocks = <&scmi_dvfs 1>;
127
128 l2_3: l2-cache {
129 compatible = "cache";
130 cache-level = <2>;
131 /* 8 ways set associative */
132 cache-size = <0x100000>;
133 cache-line-size = <64>;
134 cache-sets = <2048>;
135 cache-unified;
136 next-level-cache = <&l3_0>;
137 };
138 };
139
140 l3_0: l3-cache {
141 compatible = "cache";
142 cache-level = <3>;
143 cache-size = <0x100000>;
144 cache-unified;
145 };
146 };
147
148 firmware {
149 interrupt-parent = <&gic>;
150
151 scmi {
152 compatible = "arm,scmi";
153 mbox-names = "tx", "rx";
154 mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
155 shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 scmi_dvfs: protocol@13 {
160 reg = <0x13>;
161 #clock-cells = <1>;
162 };
163
164 scmi_clk: protocol@14 {
165 reg = <0x14>;
166 #clock-cells = <1>;
167 };
168 };
169 };
170
171 /* The first bank of memory, memory map is actually provided by UEFI. */
172 memory@80000000 {
173 device_type = "memory";
174 /* [0x80000000-0xffffffff] */
175 reg = <0x00000000 0x80000000 0x0 0x7f000000>;
176 };
177
178 memory@8080000000 {
179 device_type = "memory";
180 /* [0x8080000000-0x83f7ffffff] */
181 reg = <0x00000080 0x80000000 0x3 0x78000000>;
182 };
183
184 pmu {
185 compatible = "arm,rainier-pmu";
186 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
187 };
188
189 psci {
190 compatible = "arm,psci-0.2";
191 method = "smc";
192 };
193
194 reserved-memory {
195 #address-cells = <2>;
196 #size-cells = <2>;
197 ranges;
198
199 secure-firmware@ff000000 {
200 reg = <0x0 0xff000000 0x0 0x01000000>;
201 no-map;
202 };
203 };
204
205 spe-pmu {
206 compatible = "arm,statistical-profiling-extension-v1";
207 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
208 };
209
210 soc: soc {
211 compatible = "simple-bus";
212 #address-cells = <2>;
213 #size-cells = <2>;
214 interrupt-parent = <&gic>;
215 ranges;
216
217 uart0: serial@2a400000 {
218 compatible = "arm,pl011", "arm,primecell";
219 reg = <0x0 0x2a400000 0x0 0x1000>;
220 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>;
222 clock-names = "uartclk", "apb_pclk";
223
224 status = "disabled";
225 };
226
227 gic: interrupt-controller@30000000 {
228 compatible = "arm,gic-v3";
229 reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */
230 <0x0 0x300c0000 0x0 0x80000>; /* GICR */
231
232 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
233
234 #interrupt-cells = <3>;
235 interrupt-controller;
236
237 #address-cells = <2>;
238 #size-cells = <2>;
239 ranges;
240
241 its1: msi-controller@30040000 {
242 compatible = "arm,gic-v3-its";
243 reg = <0x0 0x30040000 0x0 0x20000>;
244
245 msi-controller;
246 #msi-cells = <1>;
247 };
248
249 its2: msi-controller@30060000 {
250 compatible = "arm,gic-v3-its";
251 reg = <0x0 0x30060000 0x0 0x20000>;
252
253 msi-controller;
254 #msi-cells = <1>;
255 };
256
257 its_ccix: msi-controller@30080000 {
258 compatible = "arm,gic-v3-its";
259 reg = <0x0 0x30080000 0x0 0x20000>;
260
261 msi-controller;
262 #msi-cells = <1>;
263 };
264
265 its_pcie: msi-controller@300a0000 {
266 compatible = "arm,gic-v3-its";
267 reg = <0x0 0x300a0000 0x0 0x20000>;
268
269 msi-controller;
270 #msi-cells = <1>;
271 };
272 };
273
274 smmu_dp: iommu@2ce00000 {
275 compatible = "arm,smmu-v3";
276 reg = <0x0 0x2ce00000 0x0 0x40000>;
277
278 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
279 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
280 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
281 interrupt-names = "eventq", "gerror", "cmdq-sync";
282 #iommu-cells = <1>;
283 };
284
285 mailbox: mhu@45000000 {
286 compatible = "arm,mhu-doorbell", "arm,primecell";
287 reg = <0x0 0x45000000 0x0 0x1000>;
288
289 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
291 #mbox-cells = <2>;
292 clocks = <&soc_refclk50mhz>;
293 clock-names = "apb_pclk";
294 };
295
296 sram: sram@6000000 {
297 compatible = "mmio-sram";
298 reg = <0x0 0x06000000 0x0 0x8000>;
299 ranges = <0 0x0 0x06000000 0x8000>;
300
301 #address-cells = <1>;
302 #size-cells = <1>;
303
304 cpu_scp_hpri0: scp-sram@0 {
305 compatible = "arm,scmi-shmem";
306 reg = <0x0 0x80>;
307 };
308
309 cpu_scp_hpri1: scp-sram@80 {
310 compatible = "arm,scmi-shmem";
311 reg = <0x80 0x80>;
312 };
313 };
314 };
315
316 timer {
317 compatible = "arm,armv8-timer";
318 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
319 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
320 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
321 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
322 };
323};