tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Apple T7001 "A8X" SoC
4 *
5 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org>
6 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts.
7 */
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/apple-aic.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/pinctrl/apple.h>
13
14/ {
15 interrupt-parent = <&aic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 serial0 = &serial0;
21 };
22
23 clkref: clock-ref {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <24000000>;
27 clock-output-names = "clkref";
28 };
29
30 cpus {
31 #address-cells = <2>;
32 #size-cells = <0>;
33
34 cpu0: cpu@0 {
35 compatible = "apple,typhoon";
36 reg = <0x0 0x0>;
37 cpu-release-addr = <0 0>; /* To be filled in by loader */
38 performance-domains = <&cpufreq>;
39 operating-points-v2 = <&typhoon_opp>;
40 enable-method = "spin-table";
41 device_type = "cpu";
42 next-level-cache = <&l2_cache>;
43 i-cache-size = <0x10000>;
44 d-cache-size = <0x10000>;
45 };
46
47 cpu1: cpu@1 {
48 compatible = "apple,typhoon";
49 reg = <0x0 0x1>;
50 cpu-release-addr = <0 0>; /* To be filled in by loader */
51 performance-domains = <&cpufreq>;
52 operating-points-v2 = <&typhoon_opp>;
53 enable-method = "spin-table";
54 device_type = "cpu";
55 next-level-cache = <&l2_cache>;
56 i-cache-size = <0x10000>;
57 d-cache-size = <0x10000>;
58 };
59
60 cpu2: cpu@2 {
61 compatible = "apple,typhoon";
62 reg = <0x0 0x2>;
63 cpu-release-addr = <0 0>; /* To be filled by loader */
64 performance-domains = <&cpufreq>;
65 operating-points-v2 = <&typhoon_opp>;
66 enable-method = "spin-table";
67 device_type = "cpu";
68 next-level-cache = <&l2_cache>;
69 i-cache-size = <0x10000>;
70 d-cache-size = <0x10000>;
71 };
72
73 l2_cache: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 cache-unified;
77 cache-size = <0x200000>;
78 };
79 };
80
81 typhoon_opp: opp-table {
82 compatible = "operating-points-v2";
83
84 opp01 {
85 opp-hz = /bits/ 64 <300000000>;
86 opp-level = <1>;
87 clock-latency-ns = <300>;
88 };
89 opp02 {
90 opp-hz = /bits/ 64 <396000000>;
91 opp-level = <2>;
92 clock-latency-ns = <49000>;
93 };
94 opp03 {
95 opp-hz = /bits/ 64 <600000000>;
96 opp-level = <3>;
97 clock-latency-ns = <31000>;
98 };
99 opp04 {
100 opp-hz = /bits/ 64 <840000000>;
101 opp-level = <4>;
102 clock-latency-ns = <32000>;
103 };
104 opp05 {
105 opp-hz = /bits/ 64 <1128000000>;
106 opp-level = <5>;
107 clock-latency-ns = <32000>;
108 };
109 opp06 {
110 opp-hz = /bits/ 64 <1392000000>;
111 opp-level = <6>;
112 clock-latency-ns = <37000>;
113 };
114 opp07 {
115 opp-hz = /bits/ 64 <1512000000>;
116 opp-level = <7>;
117 clock-latency-ns = <41000>;
118 };
119 };
120
121 soc {
122 compatible = "simple-bus";
123 #address-cells = <2>;
124 #size-cells = <2>;
125 nonposted-mmio;
126 ranges;
127
128 cpufreq: performance-controller@202220000 {
129 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq";
130 reg = <0x2 0x02220000 0 0x1000>;
131 #performance-domain-cells = <0>;
132 };
133
134 serial0: serial@20a0c0000 {
135 compatible = "apple,s5l-uart";
136 reg = <0x2 0x0a0c0000 0x0 0x4000>;
137 reg-io-width = <4>;
138 interrupt-parent = <&aic>;
139 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>;
140 /* Use the bootloader-enabled clocks for now. */
141 clocks = <&clkref>, <&clkref>;
142 clock-names = "uart", "clk_uart_baud0";
143 power-domains = <&ps_uart0>;
144 status = "disabled";
145 };
146
147 i2c0: i2c@20a110000 {
148 compatible = "apple,t7000-i2c", "apple,i2c";
149 reg = <0x2 0x0a110000 0x0 0x1000>;
150 clocks = <&clkref>;
151 interrupt-parent = <&aic>;
152 interrupts = <AIC_IRQ 174 IRQ_TYPE_LEVEL_HIGH>;
153 pinctrl-0 = <&i2c0_pins>;
154 pinctrl-names = "default";
155 power-domains = <&ps_i2c0>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158 status = "disabled";
159 };
160
161 i2c1: i2c@20a111000 {
162 compatible = "apple,t7000-i2c", "apple,i2c";
163 reg = <0x2 0x0a111000 0x0 0x1000>;
164 clocks = <&clkref>;
165 interrupt-parent = <&aic>;
166 interrupts = <AIC_IRQ 175 IRQ_TYPE_LEVEL_HIGH>;
167 pinctrl-0 = <&i2c1_pins>;
168 pinctrl-names = "default";
169 power-domains = <&ps_i2c1>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 status = "disabled";
173 };
174
175 i2c2: i2c@20a112000 {
176 compatible = "apple,t7000-i2c", "apple,i2c";
177 reg = <0x2 0x0a112000 0x0 0x1000>;
178 clocks = <&clkref>;
179 interrupt-parent = <&aic>;
180 interrupts = <AIC_IRQ 176 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-0 = <&i2c2_pins>;
182 pinctrl-names = "default";
183 power-domains = <&ps_i2c2>;
184 #address-cells = <1>;
185 #size-cells = <0>;
186 status = "disabled";
187 };
188
189 i2c3: i2c@20a113000 {
190 compatible = "apple,t7000-i2c", "apple,i2c";
191 reg = <0x2 0x0a113000 0x0 0x1000>;
192 clocks = <&clkref>;
193 interrupt-parent = <&aic>;
194 interrupts = <AIC_IRQ 177 IRQ_TYPE_LEVEL_HIGH>;
195 pinctrl-0 = <&i2c3_pins>;
196 pinctrl-names = "default";
197 power-domains = <&ps_i2c3>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200 status = "disabled";
201 };
202
203 pmgr: power-management@20e000000 {
204 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd";
205 #address-cells = <1>;
206 #size-cells = <1>;
207
208 reg = <0x2 0xe000000 0 0x24000>;
209 };
210
211 wdt: watchdog@20e027000 {
212 compatible = "apple,t7000-wdt", "apple,wdt";
213 reg = <0x2 0x0e027000 0x0 0x1000>;
214 clocks = <&clkref>;
215 interrupt-parent = <&aic>;
216 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>;
217 };
218
219 aic: interrupt-controller@20e100000 {
220 compatible = "apple,t7000-aic", "apple,aic";
221 reg = <0x2 0x0e100000 0x0 0x100000>;
222 #interrupt-cells = <3>;
223 interrupt-controller;
224 power-domains = <&ps_aic>;
225 };
226
227 pinctrl: pinctrl@20e300000 {
228 compatible = "apple,t7000-pinctrl", "apple,pinctrl";
229 reg = <0x2 0x0e300000 0x0 0x100000>;
230 power-domains = <&ps_gpio>;
231
232 gpio-controller;
233 #gpio-cells = <2>;
234 gpio-ranges = <&pinctrl 0 0 184>;
235 apple,npins = <184>;
236
237 interrupt-controller;
238 #interrupt-cells = <2>;
239 interrupt-parent = <&aic>;
240 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>,
241 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>,
242 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>,
243 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>,
244 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>,
245 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>,
246 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>;
247
248 i2c0_pins: i2c0-pins {
249 pinmux = <APPLE_PINMUX(38, 1)>,
250 <APPLE_PINMUX(37, 1)>;
251 };
252
253 i2c1_pins: i2c1-pins {
254 pinmux = <APPLE_PINMUX(66, 1)>,
255 <APPLE_PINMUX(65, 1)>;
256 };
257
258 i2c2_pins: i2c2-pins {
259 pinmux = <APPLE_PINMUX(133, 1)>,
260 <APPLE_PINMUX(132, 1)>;
261 };
262
263 i2c3_pins: i2c3-pins {
264 pinmux = <APPLE_PINMUX(135, 1)>,
265 <APPLE_PINMUX(134, 1)>;
266 };
267 };
268 };
269
270 timer {
271 compatible = "arm,armv8-timer";
272 interrupt-parent = <&aic>;
273 interrupt-names = "phys", "virt";
274 /* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */
275 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
276 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>;
277 };
278};
279
280#include "t7001-pmgr.dtsi"