tjh.dev
Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 arm-pmu {
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
31 };
32
33 psci {
34 compatible = "arm,psci-1.0";
35 method = "smc";
36 };
37
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
41 interrupt-controller;
42 reg = <0xa0021000 0x1000>,
43 <0xa0022000 0x2000>;
44 };
45
46 timer {
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
53 arm,no-tick-in-suspend;
54 };
55
56 clocks {
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62
63 clk_hsi: clk-hsi {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <64000000>;
67 };
68
69 clk_lse: clk-lse {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32768>;
73 };
74
75 clk_lsi: clk-lsi {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <32000>;
79 };
80
81 clk_csi: clk-csi {
82 #clock-cells = <0>;
83 compatible = "fixed-clock";
84 clock-frequency = <4000000>;
85 };
86 };
87
88 thermal-zones {
89 cpu_thermal: cpu-thermal {
90 polling-delay-passive = <0>;
91 polling-delay = <0>;
92 thermal-sensors = <&dts>;
93
94 trips {
95 cpu_alert1: cpu-alert1 {
96 temperature = <85000>;
97 hysteresis = <0>;
98 type = "passive";
99 };
100
101 cpu-crit {
102 temperature = <120000>;
103 hysteresis = <0>;
104 type = "critical";
105 };
106 };
107
108 cooling-maps {
109 };
110 };
111 };
112
113 booster: regulator-booster {
114 compatible = "st,stm32mp1-booster";
115 st,syscfg = <&syscfg>;
116 status = "disabled";
117 };
118
119 soc {
120 compatible = "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 interrupt-parent = <&intc>;
124 ranges;
125
126 ipcc: mailbox@4c001000 {
127 compatible = "st,stm32mp1-ipcc";
128 #mbox-cells = <1>;
129 reg = <0x4c001000 0x400>;
130 st,proc-id = <0>;
131 interrupts-extended =
132 <&exti 61 IRQ_TYPE_LEVEL_HIGH>,
133 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "rx", "tx";
135 clocks = <&rcc IPCC>;
136 wakeup-source;
137 status = "disabled";
138 };
139
140 rcc: rcc@50000000 {
141 compatible = "st,stm32mp1-rcc", "syscon";
142 reg = <0x50000000 0x1000>;
143 #clock-cells = <1>;
144 #reset-cells = <1>;
145 };
146
147 pwr_regulators: pwr@50001000 {
148 compatible = "st,stm32mp1,pwr-reg";
149 reg = <0x50001000 0x10>;
150
151 reg11: reg11 {
152 regulator-name = "reg11";
153 regulator-min-microvolt = <1100000>;
154 regulator-max-microvolt = <1100000>;
155 };
156
157 reg18: reg18 {
158 regulator-name = "reg18";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 };
162
163 usb33: usb33 {
164 regulator-name = "usb33";
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 };
168 };
169
170 pwr_mcu: pwr_mcu@50001014 {
171 compatible = "st,stm32mp151-pwr-mcu", "syscon";
172 reg = <0x50001014 0x4>;
173 };
174
175 exti: interrupt-controller@5000d000 {
176 compatible = "st,stm32mp1-exti", "syscon";
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 reg = <0x5000d000 0x400>;
180 interrupts-extended =
181 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
182 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
183 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
184 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
185 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
186 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
187 <&intc GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
188 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
189 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
190 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
191 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */
192 <&intc GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
193 <&intc GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
194 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
195 <&intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
196 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
197 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
198 <0>,
199 <0>,
200 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
201 <0>, /* EXTI_20 */
202 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
203 <&intc GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
204 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
205 <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
206 <&intc GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
207 <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
208 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
209 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
210 <&intc GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
211 <&intc GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */
212 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
213 <&intc GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
214 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
215 <0>,
216 <0>,
217 <0>,
218 <0>,
219 <0>,
220 <0>,
221 <0>, /* EXTI_40 */
222 <0>,
223 <0>,
224 <0>,
225 <0>,
226 <0>,
227 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
228 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
229 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
230 <0>,
231 <&intc GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */
232 <0>,
233 <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
234 <&intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
235 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
236 <0>,
237 <0>,
238 <0>,
239 <0>,
240 <0>,
241 <0>, /* EXTI_60 */
242 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
243 <0>,
244 <0>,
245 <0>,
246 <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
247 <0>,
248 <0>,
249 <&intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
250 <0>,
251 <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */
252 <0>,
253 <0>,
254 <&intc GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
255 };
256
257 syscfg: syscon@50020000 {
258 compatible = "st,stm32mp157-syscfg", "syscon";
259 reg = <0x50020000 0x400>;
260 clocks = <&rcc SYSCFG>;
261 };
262
263 dts: thermal@50028000 {
264 compatible = "st,stm32-thermal";
265 reg = <0x50028000 0x100>;
266 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&rcc TMPSENS>;
268 clock-names = "pclk";
269 #thermal-sensor-cells = <0>;
270 status = "disabled";
271 };
272
273 hdp: pinctrl@5002a000 {
274 compatible = "st,stm32mp151-hdp";
275 reg = <0x5002a000 0x400>;
276 clocks = <&rcc HDP>;
277 status = "disabled";
278 };
279
280 mdma1: dma-controller@58000000 {
281 compatible = "st,stm32h7-mdma";
282 reg = <0x58000000 0x1000>;
283 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&rcc MDMA>;
285 resets = <&rcc MDMA_R>;
286 #dma-cells = <5>;
287 dma-channels = <32>;
288 dma-requests = <48>;
289 };
290
291 sdmmc1: mmc@58005000 {
292 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
293 arm,primecell-periphid = <0x00253180>;
294 reg = <0x58005000 0x1000>;
295 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&rcc SDMMC1_K>;
297 clock-names = "apb_pclk";
298 resets = <&rcc SDMMC1_R>;
299 cap-sd-highspeed;
300 cap-mmc-highspeed;
301 max-frequency = <120000000>;
302 status = "disabled";
303 };
304
305 sdmmc2: mmc@58007000 {
306 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
307 arm,primecell-periphid = <0x00253180>;
308 reg = <0x58007000 0x1000>;
309 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&rcc SDMMC2_K>;
311 clock-names = "apb_pclk";
312 resets = <&rcc SDMMC2_R>;
313 cap-sd-highspeed;
314 cap-mmc-highspeed;
315 max-frequency = <120000000>;
316 status = "disabled";
317 };
318
319 crc1: crc@58009000 {
320 compatible = "st,stm32f7-crc";
321 reg = <0x58009000 0x400>;
322 clocks = <&rcc CRC1>;
323 status = "disabled";
324 };
325
326 usbh_ohci: usb@5800c000 {
327 compatible = "generic-ohci";
328 reg = <0x5800c000 0x1000>;
329 clocks = <&usbphyc>, <&rcc USBH>;
330 resets = <&rcc USBH_R>;
331 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
332 phys = <&usbphyc_port0>;
333 phy-names = "usb";
334 status = "disabled";
335 };
336
337 usbh_ehci: usb@5800d000 {
338 compatible = "generic-ehci";
339 reg = <0x5800d000 0x1000>;
340 clocks = <&usbphyc>, <&rcc USBH>;
341 resets = <&rcc USBH_R>;
342 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
343 companion = <&usbh_ohci>;
344 phys = <&usbphyc_port0>;
345 phy-names = "usb";
346 status = "disabled";
347 };
348
349 ltdc: display-controller@5a001000 {
350 compatible = "st,stm32-ltdc";
351 reg = <0x5a001000 0x400>;
352 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&rcc LTDC_PX>;
355 clock-names = "lcd";
356 resets = <&rcc LTDC_R>;
357 status = "disabled";
358 };
359
360 iwdg2: watchdog@5a002000 {
361 compatible = "st,stm32mp1-iwdg";
362 reg = <0x5a002000 0x400>;
363 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
364 clock-names = "pclk", "lsi";
365 interrupts-extended = <&exti 46 IRQ_TYPE_LEVEL_HIGH>;
366 wakeup-source;
367 status = "disabled";
368 };
369
370 usbphyc: usbphyc@5a006000 {
371 #address-cells = <1>;
372 #size-cells = <0>;
373 #clock-cells = <0>;
374 compatible = "st,stm32mp1-usbphyc";
375 reg = <0x5a006000 0x1000>;
376 clocks = <&rcc USBPHY_K>;
377 resets = <&rcc USBPHY_R>;
378 vdda1v1-supply = <®11>;
379 vdda1v8-supply = <®18>;
380 status = "disabled";
381
382 usbphyc_port0: usb-phy@0 {
383 #phy-cells = <0>;
384 reg = <0>;
385 };
386
387 usbphyc_port1: usb-phy@1 {
388 #phy-cells = <1>;
389 reg = <1>;
390 };
391 };
392
393 rtc: rtc@5c004000 {
394 compatible = "st,stm32mp1-rtc";
395 reg = <0x5c004000 0x400>;
396 clocks = <&rcc RTCAPB>, <&rcc RTC>;
397 clock-names = "pclk", "rtc_ck";
398 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
399 status = "disabled";
400 };
401
402 bsec: efuse@5c005000 {
403 compatible = "st,stm32mp15-bsec";
404 reg = <0x5c005000 0x400>;
405 #address-cells = <1>;
406 #size-cells = <1>;
407 part_number_otp: part-number-otp@4 {
408 reg = <0x4 0x1>;
409 };
410 vrefint: vrefin-cal@52 {
411 reg = <0x52 0x2>;
412 };
413 ts_cal1: calib@5c {
414 reg = <0x5c 0x2>;
415 };
416 ts_cal2: calib@5e {
417 reg = <0x5e 0x2>;
418 };
419 };
420
421 etzpc: bus@5c007000 {
422 compatible = "st,stm32-etzpc", "simple-bus";
423 reg = <0x5c007000 0x400>;
424 #address-cells = <1>;
425 #size-cells = <1>;
426 #access-controller-cells = <1>;
427 ranges;
428
429 timers2: timer@40000000 {
430 #address-cells = <1>;
431 #size-cells = <0>;
432 compatible = "st,stm32-timers";
433 reg = <0x40000000 0x400>;
434 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
435 interrupt-names = "global";
436 clocks = <&rcc TIM2_K>;
437 clock-names = "int";
438 dmas = <&dmamux1 18 0x400 0x1>,
439 <&dmamux1 19 0x400 0x1>,
440 <&dmamux1 20 0x400 0x1>,
441 <&dmamux1 21 0x400 0x1>,
442 <&dmamux1 22 0x400 0x1>;
443 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
444 access-controllers = <&etzpc 16>;
445 status = "disabled";
446
447 pwm {
448 compatible = "st,stm32-pwm";
449 #pwm-cells = <3>;
450 status = "disabled";
451 };
452
453 timer@1 {
454 compatible = "st,stm32h7-timer-trigger";
455 reg = <1>;
456 status = "disabled";
457 };
458
459 counter {
460 compatible = "st,stm32-timer-counter";
461 status = "disabled";
462 };
463 };
464
465 timers3: timer@40001000 {
466 #address-cells = <1>;
467 #size-cells = <0>;
468 compatible = "st,stm32-timers";
469 reg = <0x40001000 0x400>;
470 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-names = "global";
472 clocks = <&rcc TIM3_K>;
473 clock-names = "int";
474 dmas = <&dmamux1 23 0x400 0x1>,
475 <&dmamux1 24 0x400 0x1>,
476 <&dmamux1 25 0x400 0x1>,
477 <&dmamux1 26 0x400 0x1>,
478 <&dmamux1 27 0x400 0x1>,
479 <&dmamux1 28 0x400 0x1>;
480 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
481 access-controllers = <&etzpc 17>;
482 status = "disabled";
483
484 pwm {
485 compatible = "st,stm32-pwm";
486 #pwm-cells = <3>;
487 status = "disabled";
488 };
489
490 timer@2 {
491 compatible = "st,stm32h7-timer-trigger";
492 reg = <2>;
493 status = "disabled";
494 };
495
496 counter {
497 compatible = "st,stm32-timer-counter";
498 status = "disabled";
499 };
500 };
501
502 timers4: timer@40002000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "st,stm32-timers";
506 reg = <0x40002000 0x400>;
507 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
508 interrupt-names = "global";
509 clocks = <&rcc TIM4_K>;
510 clock-names = "int";
511 dmas = <&dmamux1 29 0x400 0x1>,
512 <&dmamux1 30 0x400 0x1>,
513 <&dmamux1 31 0x400 0x1>,
514 <&dmamux1 32 0x400 0x1>;
515 dma-names = "ch1", "ch2", "ch3", "ch4";
516 access-controllers = <&etzpc 18>;
517 status = "disabled";
518
519 pwm {
520 compatible = "st,stm32-pwm";
521 #pwm-cells = <3>;
522 status = "disabled";
523 };
524
525 timer@3 {
526 compatible = "st,stm32h7-timer-trigger";
527 reg = <3>;
528 status = "disabled";
529 };
530
531 counter {
532 compatible = "st,stm32-timer-counter";
533 status = "disabled";
534 };
535 };
536
537 timers5: timer@40003000 {
538 #address-cells = <1>;
539 #size-cells = <0>;
540 compatible = "st,stm32-timers";
541 reg = <0x40003000 0x400>;
542 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
543 interrupt-names = "global";
544 clocks = <&rcc TIM5_K>;
545 clock-names = "int";
546 dmas = <&dmamux1 55 0x400 0x1>,
547 <&dmamux1 56 0x400 0x1>,
548 <&dmamux1 57 0x400 0x1>,
549 <&dmamux1 58 0x400 0x1>,
550 <&dmamux1 59 0x400 0x1>,
551 <&dmamux1 60 0x400 0x1>;
552 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
553 access-controllers = <&etzpc 19>;
554 status = "disabled";
555
556 pwm {
557 compatible = "st,stm32-pwm";
558 #pwm-cells = <3>;
559 status = "disabled";
560 };
561
562 timer@4 {
563 compatible = "st,stm32h7-timer-trigger";
564 reg = <4>;
565 status = "disabled";
566 };
567
568 counter {
569 compatible = "st,stm32-timer-counter";
570 status = "disabled";
571 };
572 };
573
574 timers6: timer@40004000 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 compatible = "st,stm32-timers";
578 reg = <0x40004000 0x400>;
579 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
580 interrupt-names = "global";
581 clocks = <&rcc TIM6_K>;
582 clock-names = "int";
583 dmas = <&dmamux1 69 0x400 0x1>;
584 dma-names = "up";
585 access-controllers = <&etzpc 20>;
586 status = "disabled";
587
588 counter {
589 compatible = "st,stm32-timer-counter";
590 status = "disabled";
591 };
592
593 timer@5 {
594 compatible = "st,stm32h7-timer-trigger";
595 reg = <5>;
596 status = "disabled";
597 };
598 };
599
600 timers7: timer@40005000 {
601 #address-cells = <1>;
602 #size-cells = <0>;
603 compatible = "st,stm32-timers";
604 reg = <0x40005000 0x400>;
605 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
606 interrupt-names = "global";
607 clocks = <&rcc TIM7_K>;
608 clock-names = "int";
609 dmas = <&dmamux1 70 0x400 0x1>;
610 dma-names = "up";
611 access-controllers = <&etzpc 21>;
612 status = "disabled";
613
614 counter {
615 compatible = "st,stm32-timer-counter";
616 status = "disabled";
617 };
618
619 timer@6 {
620 compatible = "st,stm32h7-timer-trigger";
621 reg = <6>;
622 status = "disabled";
623 };
624 };
625
626 timers12: timer@40006000 {
627 #address-cells = <1>;
628 #size-cells = <0>;
629 compatible = "st,stm32-timers";
630 reg = <0x40006000 0x400>;
631 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
632 interrupt-names = "global";
633 clocks = <&rcc TIM12_K>;
634 clock-names = "int";
635 access-controllers = <&etzpc 22>;
636 status = "disabled";
637
638 counter {
639 compatible = "st,stm32-timer-counter";
640 status = "disabled";
641 };
642
643 pwm {
644 compatible = "st,stm32-pwm";
645 #pwm-cells = <3>;
646 status = "disabled";
647 };
648
649 timer@11 {
650 compatible = "st,stm32h7-timer-trigger";
651 reg = <11>;
652 status = "disabled";
653 };
654 };
655
656 timers13: timer@40007000 {
657 #address-cells = <1>;
658 #size-cells = <0>;
659 compatible = "st,stm32-timers";
660 reg = <0x40007000 0x400>;
661 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
662 interrupt-names = "global";
663 clocks = <&rcc TIM13_K>;
664 clock-names = "int";
665 access-controllers = <&etzpc 23>;
666 status = "disabled";
667
668 counter {
669 compatible = "st,stm32-timer-counter";
670 status = "disabled";
671 };
672
673 pwm {
674 compatible = "st,stm32-pwm";
675 #pwm-cells = <3>;
676 status = "disabled";
677 };
678
679 timer@12 {
680 compatible = "st,stm32h7-timer-trigger";
681 reg = <12>;
682 status = "disabled";
683 };
684 };
685
686 timers14: timer@40008000 {
687 #address-cells = <1>;
688 #size-cells = <0>;
689 compatible = "st,stm32-timers";
690 reg = <0x40008000 0x400>;
691 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
692 interrupt-names = "global";
693 clocks = <&rcc TIM14_K>;
694 clock-names = "int";
695 access-controllers = <&etzpc 24>;
696 status = "disabled";
697
698 counter {
699 compatible = "st,stm32-timer-counter";
700 status = "disabled";
701 };
702
703 pwm {
704 compatible = "st,stm32-pwm";
705 #pwm-cells = <3>;
706 status = "disabled";
707 };
708
709 timer@13 {
710 compatible = "st,stm32h7-timer-trigger";
711 reg = <13>;
712 status = "disabled";
713 };
714 };
715
716 lptimer1: timer@40009000 {
717 #address-cells = <1>;
718 #size-cells = <0>;
719 compatible = "st,stm32-lptimer";
720 reg = <0x40009000 0x400>;
721 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&rcc LPTIM1_K>;
723 clock-names = "mux";
724 wakeup-source;
725 access-controllers = <&etzpc 25>;
726 status = "disabled";
727
728 pwm {
729 compatible = "st,stm32-pwm-lp";
730 #pwm-cells = <3>;
731 status = "disabled";
732 };
733
734 trigger@0 {
735 compatible = "st,stm32-lptimer-trigger";
736 reg = <0>;
737 status = "disabled";
738 };
739
740 counter {
741 compatible = "st,stm32-lptimer-counter";
742 status = "disabled";
743 };
744 };
745
746 i2s2: audio-controller@4000b000 {
747 compatible = "st,stm32h7-i2s";
748 #sound-dai-cells = <0>;
749 reg = <0x4000b000 0x400>;
750 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
751 dmas = <&dmamux1 39 0x400 0x01>,
752 <&dmamux1 40 0x400 0x01>;
753 dma-names = "rx", "tx";
754 access-controllers = <&etzpc 27>;
755 status = "disabled";
756 };
757
758 spi2: spi@4000b000 {
759 #address-cells = <1>;
760 #size-cells = <0>;
761 compatible = "st,stm32h7-spi";
762 reg = <0x4000b000 0x400>;
763 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&rcc SPI2_K>;
765 resets = <&rcc SPI2_R>;
766 dmas = <&dmamux1 39 0x400 0x05>,
767 <&dmamux1 40 0x400 0x05>;
768 dma-names = "rx", "tx";
769 access-controllers = <&etzpc 27>;
770 status = "disabled";
771 };
772
773 i2s3: audio-controller@4000c000 {
774 compatible = "st,stm32h7-i2s";
775 #sound-dai-cells = <0>;
776 reg = <0x4000c000 0x400>;
777 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
778 dmas = <&dmamux1 61 0x400 0x01>,
779 <&dmamux1 62 0x400 0x01>;
780 dma-names = "rx", "tx";
781 access-controllers = <&etzpc 28>;
782 status = "disabled";
783 };
784
785 spi3: spi@4000c000 {
786 #address-cells = <1>;
787 #size-cells = <0>;
788 compatible = "st,stm32h7-spi";
789 reg = <0x4000c000 0x400>;
790 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&rcc SPI3_K>;
792 resets = <&rcc SPI3_R>;
793 dmas = <&dmamux1 61 0x400 0x05>,
794 <&dmamux1 62 0x400 0x05>;
795 dma-names = "rx", "tx";
796 access-controllers = <&etzpc 28>;
797 status = "disabled";
798 };
799
800 spdifrx: audio-controller@4000d000 {
801 compatible = "st,stm32h7-spdifrx";
802 #sound-dai-cells = <0>;
803 reg = <0x4000d000 0x400>;
804 clocks = <&rcc SPDIF_K>;
805 clock-names = "kclk";
806 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
807 dmas = <&dmamux1 93 0x400 0x01>,
808 <&dmamux1 94 0x400 0x01>;
809 dma-names = "rx", "rx-ctrl";
810 access-controllers = <&etzpc 29>;
811 status = "disabled";
812 };
813
814 usart2: serial@4000e000 {
815 compatible = "st,stm32h7-uart";
816 reg = <0x4000e000 0x400>;
817 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&rcc USART2_K>;
819 wakeup-source;
820 dmas = <&dmamux1 43 0x400 0x15>,
821 <&dmamux1 44 0x400 0x11>;
822 dma-names = "rx", "tx";
823 access-controllers = <&etzpc 30>;
824 status = "disabled";
825 };
826
827 usart3: serial@4000f000 {
828 compatible = "st,stm32h7-uart";
829 reg = <0x4000f000 0x400>;
830 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&rcc USART3_K>;
832 wakeup-source;
833 dmas = <&dmamux1 45 0x400 0x15>,
834 <&dmamux1 46 0x400 0x11>;
835 dma-names = "rx", "tx";
836 access-controllers = <&etzpc 31>;
837 status = "disabled";
838 };
839
840 uart4: serial@40010000 {
841 compatible = "st,stm32h7-uart";
842 reg = <0x40010000 0x400>;
843 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&rcc UART4_K>;
845 wakeup-source;
846 dmas = <&dmamux1 63 0x400 0x15>,
847 <&dmamux1 64 0x400 0x11>;
848 dma-names = "rx", "tx";
849 access-controllers = <&etzpc 32>;
850 status = "disabled";
851 };
852
853 uart5: serial@40011000 {
854 compatible = "st,stm32h7-uart";
855 reg = <0x40011000 0x400>;
856 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&rcc UART5_K>;
858 wakeup-source;
859 dmas = <&dmamux1 65 0x400 0x15>,
860 <&dmamux1 66 0x400 0x11>;
861 dma-names = "rx", "tx";
862 access-controllers = <&etzpc 33>;
863 status = "disabled";
864 };
865
866 i2c1: i2c@40012000 {
867 compatible = "st,stm32mp15-i2c";
868 reg = <0x40012000 0x400>;
869 interrupt-names = "event", "error";
870 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&rcc I2C1_K>;
873 resets = <&rcc I2C1_R>;
874 #address-cells = <1>;
875 #size-cells = <0>;
876 st,syscfg-fmp = <&syscfg 0x4 0x1>;
877 wakeup-source;
878 i2c-analog-filter;
879 access-controllers = <&etzpc 34>;
880 status = "disabled";
881 };
882
883 i2c2: i2c@40013000 {
884 compatible = "st,stm32mp15-i2c";
885 reg = <0x40013000 0x400>;
886 interrupt-names = "event", "error";
887 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&rcc I2C2_K>;
890 resets = <&rcc I2C2_R>;
891 #address-cells = <1>;
892 #size-cells = <0>;
893 st,syscfg-fmp = <&syscfg 0x4 0x2>;
894 wakeup-source;
895 i2c-analog-filter;
896 access-controllers = <&etzpc 35>;
897 status = "disabled";
898 };
899
900 i2c3: i2c@40014000 {
901 compatible = "st,stm32mp15-i2c";
902 reg = <0x40014000 0x400>;
903 interrupt-names = "event", "error";
904 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
905 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&rcc I2C3_K>;
907 resets = <&rcc I2C3_R>;
908 #address-cells = <1>;
909 #size-cells = <0>;
910 st,syscfg-fmp = <&syscfg 0x4 0x4>;
911 wakeup-source;
912 i2c-analog-filter;
913 access-controllers = <&etzpc 36>;
914 status = "disabled";
915 };
916
917 i2c5: i2c@40015000 {
918 compatible = "st,stm32mp15-i2c";
919 reg = <0x40015000 0x400>;
920 interrupt-names = "event", "error";
921 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
923 clocks = <&rcc I2C5_K>;
924 resets = <&rcc I2C5_R>;
925 #address-cells = <1>;
926 #size-cells = <0>;
927 st,syscfg-fmp = <&syscfg 0x4 0x10>;
928 wakeup-source;
929 i2c-analog-filter;
930 access-controllers = <&etzpc 37>;
931 status = "disabled";
932 };
933
934 cec: cec@40016000 {
935 compatible = "st,stm32-cec";
936 reg = <0x40016000 0x400>;
937 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&rcc CEC_K>, <&rcc CEC>;
939 clock-names = "cec", "hdmi-cec";
940 access-controllers = <&etzpc 38>;
941 status = "disabled";
942 };
943
944 dac: dac@40017000 {
945 compatible = "st,stm32h7-dac-core";
946 reg = <0x40017000 0x400>;
947 clocks = <&rcc DAC12>;
948 clock-names = "pclk";
949 #address-cells = <1>;
950 #size-cells = <0>;
951 access-controllers = <&etzpc 39>;
952 status = "disabled";
953
954 dac1: dac@1 {
955 compatible = "st,stm32-dac";
956 #io-channel-cells = <1>;
957 reg = <1>;
958 status = "disabled";
959 };
960
961 dac2: dac@2 {
962 compatible = "st,stm32-dac";
963 #io-channel-cells = <1>;
964 reg = <2>;
965 status = "disabled";
966 };
967 };
968
969 uart7: serial@40018000 {
970 compatible = "st,stm32h7-uart";
971 reg = <0x40018000 0x400>;
972 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&rcc UART7_K>;
974 wakeup-source;
975 dmas = <&dmamux1 79 0x400 0x15>,
976 <&dmamux1 80 0x400 0x11>;
977 dma-names = "rx", "tx";
978 access-controllers = <&etzpc 40>;
979 status = "disabled";
980 };
981
982 uart8: serial@40019000 {
983 compatible = "st,stm32h7-uart";
984 reg = <0x40019000 0x400>;
985 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&rcc UART8_K>;
987 wakeup-source;
988 dmas = <&dmamux1 81 0x400 0x15>,
989 <&dmamux1 82 0x400 0x11>;
990 dma-names = "rx", "tx";
991 access-controllers = <&etzpc 41>;
992 status = "disabled";
993 };
994
995 timers1: timer@44000000 {
996 #address-cells = <1>;
997 #size-cells = <0>;
998 compatible = "st,stm32-timers";
999 reg = <0x44000000 0x400>;
1000 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1001 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1004 interrupt-names = "brk", "up", "trg-com", "cc";
1005 clocks = <&rcc TIM1_K>;
1006 clock-names = "int";
1007 dmas = <&dmamux1 11 0x400 0x1>,
1008 <&dmamux1 12 0x400 0x1>,
1009 <&dmamux1 13 0x400 0x1>,
1010 <&dmamux1 14 0x400 0x1>,
1011 <&dmamux1 15 0x400 0x1>,
1012 <&dmamux1 16 0x400 0x1>,
1013 <&dmamux1 17 0x400 0x1>;
1014 dma-names = "ch1", "ch2", "ch3", "ch4",
1015 "up", "trig", "com";
1016 access-controllers = <&etzpc 48>;
1017 status = "disabled";
1018
1019 pwm {
1020 compatible = "st,stm32-pwm";
1021 #pwm-cells = <3>;
1022 status = "disabled";
1023 };
1024
1025 timer@0 {
1026 compatible = "st,stm32h7-timer-trigger";
1027 reg = <0>;
1028 status = "disabled";
1029 };
1030
1031 counter {
1032 compatible = "st,stm32-timer-counter";
1033 status = "disabled";
1034 };
1035 };
1036
1037 timers8: timer@44001000 {
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "st,stm32-timers";
1041 reg = <0x44001000 0x400>;
1042 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1043 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1044 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1045 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1046 interrupt-names = "brk", "up", "trg-com", "cc";
1047 clocks = <&rcc TIM8_K>;
1048 clock-names = "int";
1049 dmas = <&dmamux1 47 0x400 0x1>,
1050 <&dmamux1 48 0x400 0x1>,
1051 <&dmamux1 49 0x400 0x1>,
1052 <&dmamux1 50 0x400 0x1>,
1053 <&dmamux1 51 0x400 0x1>,
1054 <&dmamux1 52 0x400 0x1>,
1055 <&dmamux1 53 0x400 0x1>;
1056 dma-names = "ch1", "ch2", "ch3", "ch4",
1057 "up", "trig", "com";
1058 access-controllers = <&etzpc 49>;
1059 status = "disabled";
1060
1061 pwm {
1062 compatible = "st,stm32-pwm";
1063 #pwm-cells = <3>;
1064 status = "disabled";
1065 };
1066
1067 timer@7 {
1068 compatible = "st,stm32h7-timer-trigger";
1069 reg = <7>;
1070 status = "disabled";
1071 };
1072
1073 counter {
1074 compatible = "st,stm32-timer-counter";
1075 status = "disabled";
1076 };
1077 };
1078
1079 usart6: serial@44003000 {
1080 compatible = "st,stm32h7-uart";
1081 reg = <0x44003000 0x400>;
1082 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&rcc USART6_K>;
1084 wakeup-source;
1085 dmas = <&dmamux1 71 0x400 0x15>,
1086 <&dmamux1 72 0x400 0x11>;
1087 dma-names = "rx", "tx";
1088 access-controllers = <&etzpc 51>;
1089 status = "disabled";
1090 };
1091
1092 i2s1: audio-controller@44004000 {
1093 compatible = "st,stm32h7-i2s";
1094 #sound-dai-cells = <0>;
1095 reg = <0x44004000 0x400>;
1096 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1097 dmas = <&dmamux1 37 0x400 0x01>,
1098 <&dmamux1 38 0x400 0x01>;
1099 dma-names = "rx", "tx";
1100 access-controllers = <&etzpc 52>;
1101 status = "disabled";
1102 };
1103
1104 spi1: spi@44004000 {
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 compatible = "st,stm32h7-spi";
1108 reg = <0x44004000 0x400>;
1109 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1110 clocks = <&rcc SPI1_K>;
1111 resets = <&rcc SPI1_R>;
1112 dmas = <&dmamux1 37 0x400 0x05>,
1113 <&dmamux1 38 0x400 0x05>;
1114 dma-names = "rx", "tx";
1115 access-controllers = <&etzpc 52>;
1116 status = "disabled";
1117 };
1118
1119 spi4: spi@44005000 {
1120 #address-cells = <1>;
1121 #size-cells = <0>;
1122 compatible = "st,stm32h7-spi";
1123 reg = <0x44005000 0x400>;
1124 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&rcc SPI4_K>;
1126 resets = <&rcc SPI4_R>;
1127 dmas = <&dmamux1 83 0x400 0x05>,
1128 <&dmamux1 84 0x400 0x05>;
1129 dma-names = "rx", "tx";
1130 access-controllers = <&etzpc 53>;
1131 status = "disabled";
1132 };
1133
1134 timers15: timer@44006000 {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 compatible = "st,stm32-timers";
1138 reg = <0x44006000 0x400>;
1139 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1140 interrupt-names = "global";
1141 clocks = <&rcc TIM15_K>;
1142 clock-names = "int";
1143 dmas = <&dmamux1 105 0x400 0x1>,
1144 <&dmamux1 106 0x400 0x1>,
1145 <&dmamux1 107 0x400 0x1>,
1146 <&dmamux1 108 0x400 0x1>;
1147 dma-names = "ch1", "up", "trig", "com";
1148 access-controllers = <&etzpc 54>;
1149 status = "disabled";
1150
1151 counter {
1152 compatible = "st,stm32-timer-counter";
1153 status = "disabled";
1154 };
1155
1156 pwm {
1157 compatible = "st,stm32-pwm";
1158 #pwm-cells = <3>;
1159 status = "disabled";
1160 };
1161
1162 timer@14 {
1163 compatible = "st,stm32h7-timer-trigger";
1164 reg = <14>;
1165 status = "disabled";
1166 };
1167 };
1168
1169 timers16: timer@44007000 {
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1172 compatible = "st,stm32-timers";
1173 reg = <0x44007000 0x400>;
1174 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1175 interrupt-names = "global";
1176 clocks = <&rcc TIM16_K>;
1177 clock-names = "int";
1178 dmas = <&dmamux1 109 0x400 0x1>,
1179 <&dmamux1 110 0x400 0x1>;
1180 dma-names = "ch1", "up";
1181 access-controllers = <&etzpc 55>;
1182 status = "disabled";
1183
1184 counter {
1185 compatible = "st,stm32-timer-counter";
1186 status = "disabled";
1187 };
1188
1189 pwm {
1190 compatible = "st,stm32-pwm";
1191 #pwm-cells = <3>;
1192 status = "disabled";
1193 };
1194
1195 timer@15 {
1196 compatible = "st,stm32h7-timer-trigger";
1197 reg = <15>;
1198 status = "disabled";
1199 };
1200 };
1201
1202 timers17: timer@44008000 {
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1205 compatible = "st,stm32-timers";
1206 reg = <0x44008000 0x400>;
1207 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1208 interrupt-names = "global";
1209 clocks = <&rcc TIM17_K>;
1210 clock-names = "int";
1211 dmas = <&dmamux1 111 0x400 0x1>,
1212 <&dmamux1 112 0x400 0x1>;
1213 dma-names = "ch1", "up";
1214 access-controllers = <&etzpc 56>;
1215 status = "disabled";
1216
1217 counter {
1218 compatible = "st,stm32-timer-counter";
1219 status = "disabled";
1220 };
1221
1222 pwm {
1223 compatible = "st,stm32-pwm";
1224 #pwm-cells = <3>;
1225 status = "disabled";
1226 };
1227
1228 timer@16 {
1229 compatible = "st,stm32h7-timer-trigger";
1230 reg = <16>;
1231 status = "disabled";
1232 };
1233 };
1234
1235 spi5: spi@44009000 {
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 compatible = "st,stm32h7-spi";
1239 reg = <0x44009000 0x400>;
1240 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1241 clocks = <&rcc SPI5_K>;
1242 resets = <&rcc SPI5_R>;
1243 dmas = <&dmamux1 85 0x400 0x05>,
1244 <&dmamux1 86 0x400 0x05>;
1245 dma-names = "rx", "tx";
1246 access-controllers = <&etzpc 57>;
1247 status = "disabled";
1248 };
1249
1250 sai1: sai@4400a000 {
1251 compatible = "st,stm32h7-sai";
1252 #address-cells = <1>;
1253 #size-cells = <1>;
1254 ranges = <0 0x4400a000 0x400>;
1255 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
1256 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1257 resets = <&rcc SAI1_R>;
1258 access-controllers = <&etzpc 58>;
1259 status = "disabled";
1260
1261 sai1a: audio-controller@4400a004 {
1262 #sound-dai-cells = <0>;
1263
1264 compatible = "st,stm32-sai-sub-a";
1265 reg = <0x4 0x20>;
1266 clocks = <&rcc SAI1_K>;
1267 clock-names = "sai_ck";
1268 dmas = <&dmamux1 87 0x400 0x01>;
1269 status = "disabled";
1270 };
1271
1272 sai1b: audio-controller@4400a024 {
1273 #sound-dai-cells = <0>;
1274 compatible = "st,stm32-sai-sub-b";
1275 reg = <0x24 0x20>;
1276 clocks = <&rcc SAI1_K>;
1277 clock-names = "sai_ck";
1278 dmas = <&dmamux1 88 0x400 0x01>;
1279 status = "disabled";
1280 };
1281 };
1282
1283 sai2: sai@4400b000 {
1284 compatible = "st,stm32h7-sai";
1285 #address-cells = <1>;
1286 #size-cells = <1>;
1287 ranges = <0 0x4400b000 0x400>;
1288 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
1289 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1290 resets = <&rcc SAI2_R>;
1291 access-controllers = <&etzpc 59>;
1292 status = "disabled";
1293
1294 sai2a: audio-controller@4400b004 {
1295 #sound-dai-cells = <0>;
1296 compatible = "st,stm32-sai-sub-a";
1297 reg = <0x4 0x20>;
1298 clocks = <&rcc SAI2_K>;
1299 clock-names = "sai_ck";
1300 dmas = <&dmamux1 89 0x400 0x01>;
1301 status = "disabled";
1302 };
1303
1304 sai2b: audio-controller@4400b024 {
1305 #sound-dai-cells = <0>;
1306 compatible = "st,stm32-sai-sub-b";
1307 reg = <0x24 0x20>;
1308 clocks = <&rcc SAI2_K>;
1309 clock-names = "sai_ck";
1310 dmas = <&dmamux1 90 0x400 0x01>;
1311 status = "disabled";
1312 };
1313 };
1314
1315 sai3: sai@4400c000 {
1316 compatible = "st,stm32h7-sai";
1317 #address-cells = <1>;
1318 #size-cells = <1>;
1319 ranges = <0 0x4400c000 0x400>;
1320 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
1321 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1322 resets = <&rcc SAI3_R>;
1323 access-controllers = <&etzpc 60>;
1324 status = "disabled";
1325
1326 sai3a: audio-controller@4400c004 {
1327 #sound-dai-cells = <0>;
1328 compatible = "st,stm32-sai-sub-a";
1329 reg = <0x04 0x20>;
1330 clocks = <&rcc SAI3_K>;
1331 clock-names = "sai_ck";
1332 dmas = <&dmamux1 113 0x400 0x01>;
1333 status = "disabled";
1334 };
1335
1336 sai3b: audio-controller@4400c024 {
1337 #sound-dai-cells = <0>;
1338 compatible = "st,stm32-sai-sub-b";
1339 reg = <0x24 0x20>;
1340 clocks = <&rcc SAI3_K>;
1341 clock-names = "sai_ck";
1342 dmas = <&dmamux1 114 0x400 0x01>;
1343 status = "disabled";
1344 };
1345 };
1346
1347 dfsdm: dfsdm@4400d000 {
1348 compatible = "st,stm32mp1-dfsdm";
1349 reg = <0x4400d000 0x800>;
1350 clocks = <&rcc DFSDM_K>;
1351 clock-names = "dfsdm";
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1354 access-controllers = <&etzpc 61>;
1355 status = "disabled";
1356
1357 dfsdm0: filter@0 {
1358 compatible = "st,stm32-dfsdm-adc";
1359 #io-channel-cells = <1>;
1360 reg = <0>;
1361 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1362 dmas = <&dmamux1 101 0x400 0x01>;
1363 dma-names = "rx";
1364 status = "disabled";
1365 };
1366
1367 dfsdm1: filter@1 {
1368 compatible = "st,stm32-dfsdm-adc";
1369 #io-channel-cells = <1>;
1370 reg = <1>;
1371 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1372 dmas = <&dmamux1 102 0x400 0x01>;
1373 dma-names = "rx";
1374 status = "disabled";
1375 };
1376
1377 dfsdm2: filter@2 {
1378 compatible = "st,stm32-dfsdm-adc";
1379 #io-channel-cells = <1>;
1380 reg = <2>;
1381 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1382 dmas = <&dmamux1 103 0x400 0x01>;
1383 dma-names = "rx";
1384 status = "disabled";
1385 };
1386
1387 dfsdm3: filter@3 {
1388 compatible = "st,stm32-dfsdm-adc";
1389 #io-channel-cells = <1>;
1390 reg = <3>;
1391 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1392 dmas = <&dmamux1 104 0x400 0x01>;
1393 dma-names = "rx";
1394 status = "disabled";
1395 };
1396
1397 dfsdm4: filter@4 {
1398 compatible = "st,stm32-dfsdm-adc";
1399 #io-channel-cells = <1>;
1400 reg = <4>;
1401 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1402 dmas = <&dmamux1 91 0x400 0x01>;
1403 dma-names = "rx";
1404 status = "disabled";
1405 };
1406
1407 dfsdm5: filter@5 {
1408 compatible = "st,stm32-dfsdm-adc";
1409 #io-channel-cells = <1>;
1410 reg = <5>;
1411 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1412 dmas = <&dmamux1 92 0x400 0x01>;
1413 dma-names = "rx";
1414 status = "disabled";
1415 };
1416 };
1417
1418 dma1: dma-controller@48000000 {
1419 compatible = "st,stm32-dma";
1420 reg = <0x48000000 0x400>;
1421 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1425 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1426 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1427 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1428 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1429 clocks = <&rcc DMA1>;
1430 resets = <&rcc DMA1_R>;
1431 #dma-cells = <4>;
1432 st,mem2mem;
1433 dma-requests = <8>;
1434 access-controllers = <&etzpc 88>;
1435 };
1436
1437 dma2: dma-controller@48001000 {
1438 compatible = "st,stm32-dma";
1439 reg = <0x48001000 0x400>;
1440 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1448 clocks = <&rcc DMA2>;
1449 resets = <&rcc DMA2_R>;
1450 #dma-cells = <4>;
1451 st,mem2mem;
1452 dma-requests = <8>;
1453 access-controllers = <&etzpc 89>;
1454 };
1455
1456 dmamux1: dma-router@48002000 {
1457 compatible = "st,stm32h7-dmamux";
1458 reg = <0x48002000 0x40>;
1459 #dma-cells = <3>;
1460 dma-requests = <128>;
1461 dma-masters = <&dma1 &dma2>;
1462 dma-channels = <16>;
1463 clocks = <&rcc DMAMUX>;
1464 resets = <&rcc DMAMUX_R>;
1465 access-controllers = <&etzpc 90>;
1466 };
1467
1468 adc: adc@48003000 {
1469 compatible = "st,stm32mp1-adc-core";
1470 reg = <0x48003000 0x400>;
1471 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1473 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1474 clock-names = "bus", "adc";
1475 interrupt-controller;
1476 st,syscfg = <&syscfg>;
1477 #interrupt-cells = <1>;
1478 #address-cells = <1>;
1479 #size-cells = <0>;
1480 access-controllers = <&etzpc 72>;
1481 status = "disabled";
1482
1483 adc1: adc@0 {
1484 compatible = "st,stm32mp1-adc";
1485 #io-channel-cells = <1>;
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1488 reg = <0x0>;
1489 interrupt-parent = <&adc>;
1490 interrupts = <0>;
1491 dmas = <&dmamux1 9 0x400 0x01>;
1492 dma-names = "rx";
1493 status = "disabled";
1494 };
1495
1496 adc2: adc@100 {
1497 compatible = "st,stm32mp1-adc";
1498 #io-channel-cells = <1>;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1501 reg = <0x100>;
1502 interrupt-parent = <&adc>;
1503 interrupts = <1>;
1504 dmas = <&dmamux1 10 0x400 0x01>;
1505 dma-names = "rx";
1506 nvmem-cells = <&vrefint>;
1507 nvmem-cell-names = "vrefint";
1508 status = "disabled";
1509 channel@13 {
1510 reg = <13>;
1511 label = "vrefint";
1512 };
1513 channel@14 {
1514 reg = <14>;
1515 label = "vddcore";
1516 };
1517 };
1518 };
1519
1520 sdmmc3: mmc@48004000 {
1521 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1522 arm,primecell-periphid = <0x00253180>;
1523 reg = <0x48004000 0x400>;
1524 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1525 clocks = <&rcc SDMMC3_K>;
1526 clock-names = "apb_pclk";
1527 resets = <&rcc SDMMC3_R>;
1528 cap-sd-highspeed;
1529 cap-mmc-highspeed;
1530 max-frequency = <120000000>;
1531 access-controllers = <&etzpc 86>;
1532 status = "disabled";
1533 };
1534
1535 usbotg_hs: usb-otg@49000000 {
1536 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1537 reg = <0x49000000 0x10000>;
1538 clocks = <&rcc USBO_K>, <&usbphyc>;
1539 clock-names = "otg", "utmi";
1540 resets = <&rcc USBO_R>;
1541 reset-names = "dwc2";
1542 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1543 g-rx-fifo-size = <512>;
1544 g-np-tx-fifo-size = <32>;
1545 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1546 dr_mode = "otg";
1547 otg-rev = <0x200>;
1548 usb33d-supply = <&usb33>;
1549 access-controllers = <&etzpc 85>;
1550 status = "disabled";
1551 };
1552
1553 dcmi: dcmi@4c006000 {
1554 compatible = "st,stm32-dcmi";
1555 reg = <0x4c006000 0x400>;
1556 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1557 resets = <&rcc CAMITF_R>;
1558 clocks = <&rcc DCMI>;
1559 clock-names = "mclk";
1560 dmas = <&dmamux1 75 0x400 0x01>;
1561 dma-names = "tx";
1562 access-controllers = <&etzpc 70>;
1563 status = "disabled";
1564 };
1565
1566 lptimer2: timer@50021000 {
1567 #address-cells = <1>;
1568 #size-cells = <0>;
1569 compatible = "st,stm32-lptimer";
1570 reg = <0x50021000 0x400>;
1571 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1572 clocks = <&rcc LPTIM2_K>;
1573 clock-names = "mux";
1574 wakeup-source;
1575 access-controllers = <&etzpc 64>;
1576 status = "disabled";
1577
1578 pwm {
1579 compatible = "st,stm32-pwm-lp";
1580 #pwm-cells = <3>;
1581 status = "disabled";
1582 };
1583
1584 trigger@1 {
1585 compatible = "st,stm32-lptimer-trigger";
1586 reg = <1>;
1587 status = "disabled";
1588 };
1589
1590 counter {
1591 compatible = "st,stm32-lptimer-counter";
1592 status = "disabled";
1593 };
1594 };
1595
1596 lptimer3: timer@50022000 {
1597 #address-cells = <1>;
1598 #size-cells = <0>;
1599 compatible = "st,stm32-lptimer";
1600 reg = <0x50022000 0x400>;
1601 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1602 clocks = <&rcc LPTIM3_K>;
1603 clock-names = "mux";
1604 wakeup-source;
1605 access-controllers = <&etzpc 65>;
1606 status = "disabled";
1607
1608 pwm {
1609 compatible = "st,stm32-pwm-lp";
1610 #pwm-cells = <3>;
1611 status = "disabled";
1612 };
1613
1614 trigger@2 {
1615 compatible = "st,stm32-lptimer-trigger";
1616 reg = <2>;
1617 status = "disabled";
1618 };
1619 };
1620
1621 lptimer4: timer@50023000 {
1622 compatible = "st,stm32-lptimer";
1623 reg = <0x50023000 0x400>;
1624 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1625 clocks = <&rcc LPTIM4_K>;
1626 clock-names = "mux";
1627 wakeup-source;
1628 access-controllers = <&etzpc 66>;
1629 status = "disabled";
1630
1631 pwm {
1632 compatible = "st,stm32-pwm-lp";
1633 #pwm-cells = <3>;
1634 status = "disabled";
1635 };
1636 };
1637
1638 lptimer5: timer@50024000 {
1639 compatible = "st,stm32-lptimer";
1640 reg = <0x50024000 0x400>;
1641 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1642 clocks = <&rcc LPTIM5_K>;
1643 clock-names = "mux";
1644 wakeup-source;
1645 access-controllers = <&etzpc 67>;
1646 status = "disabled";
1647
1648 pwm {
1649 compatible = "st,stm32-pwm-lp";
1650 #pwm-cells = <3>;
1651 status = "disabled";
1652 };
1653 };
1654
1655 vrefbuf: vrefbuf@50025000 {
1656 compatible = "st,stm32-vrefbuf";
1657 reg = <0x50025000 0x8>;
1658 regulator-min-microvolt = <1500000>;
1659 regulator-max-microvolt = <2500000>;
1660 clocks = <&rcc VREF>;
1661 access-controllers = <&etzpc 69>;
1662 status = "disabled";
1663 };
1664
1665 sai4: sai@50027000 {
1666 compatible = "st,stm32h7-sai";
1667 #address-cells = <1>;
1668 #size-cells = <1>;
1669 ranges = <0 0x50027000 0x400>;
1670 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1671 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1672 resets = <&rcc SAI4_R>;
1673 access-controllers = <&etzpc 68>;
1674 status = "disabled";
1675
1676 sai4a: audio-controller@50027004 {
1677 #sound-dai-cells = <0>;
1678 compatible = "st,stm32-sai-sub-a";
1679 reg = <0x04 0x20>;
1680 clocks = <&rcc SAI4_K>;
1681 clock-names = "sai_ck";
1682 dmas = <&dmamux1 99 0x400 0x01>;
1683 status = "disabled";
1684 };
1685
1686 sai4b: audio-controller@50027024 {
1687 #sound-dai-cells = <0>;
1688 compatible = "st,stm32-sai-sub-b";
1689 reg = <0x24 0x20>;
1690 clocks = <&rcc SAI4_K>;
1691 clock-names = "sai_ck";
1692 dmas = <&dmamux1 100 0x400 0x01>;
1693 status = "disabled";
1694 };
1695 };
1696
1697 hash1: hash@54002000 {
1698 compatible = "st,stm32f756-hash";
1699 reg = <0x54002000 0x400>;
1700 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1701 clocks = <&rcc HASH1>;
1702 resets = <&rcc HASH1_R>;
1703 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1704 dma-names = "in";
1705 dma-maxburst = <2>;
1706 access-controllers = <&etzpc 8>;
1707 status = "disabled";
1708 };
1709
1710 rng1: rng@54003000 {
1711 compatible = "st,stm32-rng";
1712 reg = <0x54003000 0x400>;
1713 clocks = <&rcc RNG1_K>;
1714 resets = <&rcc RNG1_R>;
1715 access-controllers = <&etzpc 7>;
1716 status = "disabled";
1717 };
1718
1719 fmc: memory-controller@58002000 {
1720 #address-cells = <2>;
1721 #size-cells = <1>;
1722 compatible = "st,stm32mp1-fmc2-ebi";
1723 reg = <0x58002000 0x1000>;
1724 clocks = <&rcc FMC_K>;
1725 resets = <&rcc FMC_R>;
1726 access-controllers = <&etzpc 91>;
1727 status = "disabled";
1728
1729 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1730 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1731 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1732 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1733 <4 0 0x80000000 0x10000000>; /* NAND */
1734
1735 nand-controller@4,0 {
1736 #address-cells = <1>;
1737 #size-cells = <0>;
1738 compatible = "st,stm32mp1-fmc2-nfc";
1739 reg = <4 0x00000000 0x1000>,
1740 <4 0x08010000 0x1000>,
1741 <4 0x08020000 0x1000>,
1742 <4 0x01000000 0x1000>,
1743 <4 0x09010000 0x1000>,
1744 <4 0x09020000 0x1000>;
1745 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1746 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1747 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1748 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1749 dma-names = "tx", "rx", "ecc";
1750 status = "disabled";
1751 };
1752 };
1753
1754 qspi: spi@58003000 {
1755 compatible = "st,stm32f469-qspi";
1756 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1757 reg-names = "qspi", "qspi_mm";
1758 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1759 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1760 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1761 dma-names = "tx", "rx";
1762 clocks = <&rcc QSPI_K>;
1763 resets = <&rcc QSPI_R>;
1764 #address-cells = <1>;
1765 #size-cells = <0>;
1766 access-controllers = <&etzpc 92>;
1767 status = "disabled";
1768 };
1769
1770 ethernet0: ethernet@5800a000 {
1771 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1772 reg = <0x5800a000 0x2000>;
1773 reg-names = "stmmaceth";
1774 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1775 interrupt-names = "macirq";
1776 clock-names = "stmmaceth",
1777 "mac-clk-tx",
1778 "mac-clk-rx",
1779 "eth-ck",
1780 "ptp_ref",
1781 "ethstp";
1782 clocks = <&rcc ETHMAC>,
1783 <&rcc ETHTX>,
1784 <&rcc ETHRX>,
1785 <&rcc ETHCK_K>,
1786 <&rcc ETHPTP_K>,
1787 <&rcc ETHSTP>;
1788 st,syscon = <&syscfg 0x4>;
1789 snps,mixed-burst;
1790 snps,pbl = <2>;
1791 snps,axi-config = <&stmmac_axi_config_0>;
1792 snps,tso;
1793 access-controllers = <&etzpc 94>;
1794 status = "disabled";
1795
1796 stmmac_axi_config_0: stmmac-axi-config {
1797 snps,wr_osr_lmt = <0x7>;
1798 snps,rd_osr_lmt = <0x7>;
1799 snps,blen = <0 0 0 0 16 8 4>;
1800 };
1801 };
1802
1803 usart1: serial@5c000000 {
1804 compatible = "st,stm32h7-uart";
1805 reg = <0x5c000000 0x400>;
1806 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1807 clocks = <&rcc USART1_K>;
1808 wakeup-source;
1809 access-controllers = <&etzpc 3>;
1810 status = "disabled";
1811 };
1812
1813 spi6: spi@5c001000 {
1814 #address-cells = <1>;
1815 #size-cells = <0>;
1816 compatible = "st,stm32h7-spi";
1817 reg = <0x5c001000 0x400>;
1818 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&rcc SPI6_K>;
1820 resets = <&rcc SPI6_R>;
1821 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1822 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1823 access-controllers = <&etzpc 4>;
1824 dma-names = "rx", "tx";
1825 status = "disabled";
1826 };
1827
1828 i2c4: i2c@5c002000 {
1829 compatible = "st,stm32mp15-i2c";
1830 reg = <0x5c002000 0x400>;
1831 interrupt-names = "event", "error";
1832 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1834 clocks = <&rcc I2C4_K>;
1835 resets = <&rcc I2C4_R>;
1836 #address-cells = <1>;
1837 #size-cells = <0>;
1838 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1839 wakeup-source;
1840 i2c-analog-filter;
1841 access-controllers = <&etzpc 5>;
1842 status = "disabled";
1843 };
1844
1845 i2c6: i2c@5c009000 {
1846 compatible = "st,stm32mp15-i2c";
1847 reg = <0x5c009000 0x400>;
1848 interrupt-names = "event", "error";
1849 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1851 clocks = <&rcc I2C6_K>;
1852 resets = <&rcc I2C6_R>;
1853 #address-cells = <1>;
1854 #size-cells = <0>;
1855 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1856 wakeup-source;
1857 i2c-analog-filter;
1858 access-controllers = <&etzpc 12>;
1859 status = "disabled";
1860 };
1861 };
1862
1863 tamp: tamp@5c00a000 {
1864 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1865 reg = <0x5c00a000 0x400>;
1866 };
1867
1868 /*
1869 * Break node order to solve dependency probe issue between
1870 * pinctrl and exti.
1871 */
1872 pinctrl: pinctrl@50002000 {
1873 #address-cells = <1>;
1874 #size-cells = <1>;
1875 compatible = "st,stm32mp157-pinctrl";
1876 ranges = <0 0x50002000 0xa400>;
1877 interrupt-parent = <&exti>;
1878 st,syscfg = <&exti 0x60 0xff>;
1879
1880 gpioa: gpio@50002000 {
1881 gpio-controller;
1882 #gpio-cells = <2>;
1883 interrupt-controller;
1884 #interrupt-cells = <2>;
1885 reg = <0x0 0x400>;
1886 clocks = <&rcc GPIOA>;
1887 st,bank-name = "GPIOA";
1888 status = "disabled";
1889 };
1890
1891 gpiob: gpio@50003000 {
1892 gpio-controller;
1893 #gpio-cells = <2>;
1894 interrupt-controller;
1895 #interrupt-cells = <2>;
1896 reg = <0x1000 0x400>;
1897 clocks = <&rcc GPIOB>;
1898 st,bank-name = "GPIOB";
1899 status = "disabled";
1900 };
1901
1902 gpioc: gpio@50004000 {
1903 gpio-controller;
1904 #gpio-cells = <2>;
1905 interrupt-controller;
1906 #interrupt-cells = <2>;
1907 reg = <0x2000 0x400>;
1908 clocks = <&rcc GPIOC>;
1909 st,bank-name = "GPIOC";
1910 status = "disabled";
1911 };
1912
1913 gpiod: gpio@50005000 {
1914 gpio-controller;
1915 #gpio-cells = <2>;
1916 interrupt-controller;
1917 #interrupt-cells = <2>;
1918 reg = <0x3000 0x400>;
1919 clocks = <&rcc GPIOD>;
1920 st,bank-name = "GPIOD";
1921 status = "disabled";
1922 };
1923
1924 gpioe: gpio@50006000 {
1925 gpio-controller;
1926 #gpio-cells = <2>;
1927 interrupt-controller;
1928 #interrupt-cells = <2>;
1929 reg = <0x4000 0x400>;
1930 clocks = <&rcc GPIOE>;
1931 st,bank-name = "GPIOE";
1932 status = "disabled";
1933 };
1934
1935 gpiof: gpio@50007000 {
1936 gpio-controller;
1937 #gpio-cells = <2>;
1938 interrupt-controller;
1939 #interrupt-cells = <2>;
1940 reg = <0x5000 0x400>;
1941 clocks = <&rcc GPIOF>;
1942 st,bank-name = "GPIOF";
1943 status = "disabled";
1944 };
1945
1946 gpiog: gpio@50008000 {
1947 gpio-controller;
1948 #gpio-cells = <2>;
1949 interrupt-controller;
1950 #interrupt-cells = <2>;
1951 reg = <0x6000 0x400>;
1952 clocks = <&rcc GPIOG>;
1953 st,bank-name = "GPIOG";
1954 status = "disabled";
1955 };
1956
1957 gpioh: gpio@50009000 {
1958 gpio-controller;
1959 #gpio-cells = <2>;
1960 interrupt-controller;
1961 #interrupt-cells = <2>;
1962 reg = <0x7000 0x400>;
1963 clocks = <&rcc GPIOH>;
1964 st,bank-name = "GPIOH";
1965 status = "disabled";
1966 };
1967
1968 gpioi: gpio@5000a000 {
1969 gpio-controller;
1970 #gpio-cells = <2>;
1971 interrupt-controller;
1972 #interrupt-cells = <2>;
1973 reg = <0x8000 0x400>;
1974 clocks = <&rcc GPIOI>;
1975 st,bank-name = "GPIOI";
1976 status = "disabled";
1977 };
1978
1979 gpioj: gpio@5000b000 {
1980 gpio-controller;
1981 #gpio-cells = <2>;
1982 interrupt-controller;
1983 #interrupt-cells = <2>;
1984 reg = <0x9000 0x400>;
1985 clocks = <&rcc GPIOJ>;
1986 st,bank-name = "GPIOJ";
1987 status = "disabled";
1988 };
1989
1990 gpiok: gpio@5000c000 {
1991 gpio-controller;
1992 #gpio-cells = <2>;
1993 interrupt-controller;
1994 #interrupt-cells = <2>;
1995 reg = <0xa000 0x400>;
1996 clocks = <&rcc GPIOK>;
1997 st,bank-name = "GPIOK";
1998 status = "disabled";
1999 };
2000 };
2001
2002 pinctrl_z: pinctrl@54004000 {
2003 #address-cells = <1>;
2004 #size-cells = <1>;
2005 compatible = "st,stm32mp157-z-pinctrl";
2006 ranges = <0 0x54004000 0x400>;
2007 interrupt-parent = <&exti>;
2008 st,syscfg = <&exti 0x60 0xff>;
2009
2010 gpioz: gpio@54004000 {
2011 gpio-controller;
2012 #gpio-cells = <2>;
2013 interrupt-controller;
2014 #interrupt-cells = <2>;
2015 reg = <0 0x400>;
2016 clocks = <&rcc GPIOZ>;
2017 st,bank-name = "GPIOZ";
2018 st,bank-ioport = <11>;
2019 status = "disabled";
2020 };
2021 };
2022 };
2023
2024 mlahb: ahb {
2025 compatible = "st,mlahb", "simple-bus";
2026 #address-cells = <1>;
2027 #size-cells = <1>;
2028 ranges;
2029 dma-ranges = <0x00000000 0x38000000 0x10000>,
2030 <0x10000000 0x10000000 0x60000>,
2031 <0x30000000 0x30000000 0x60000>;
2032
2033 m4_rproc: m4@10000000 {
2034 compatible = "st,stm32mp1-m4";
2035 reg = <0x10000000 0x40000>,
2036 <0x30000000 0x40000>,
2037 <0x38000000 0x10000>;
2038 resets = <&rcc MCU_R>;
2039 reset-names = "mcu_rst";
2040 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
2041 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
2042 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
2043 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
2044 status = "disabled";
2045 };
2046 };
2047};