tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1.. SPDX-License-Identifier: GPL-2.0
2
3======================================
4Coherent Device Attribute Table (CDAT)
5======================================
6
7The CDAT provides functional and performance attributes of devices such
8as CXL accelerators, switches, or endpoints. The table formatting is
9similar to ACPI tables. CDAT data may be parsed by BIOS at boot or may
10be enumerated at runtime (after device hotplug, for example).
11
12Terminology:
13DPA - Device Physical Address, used by the CXL device to denote the address
14it supports for that device.
15
16DSMADHandle - A device unique handle that is associated with a DPA range
17defined by the DSMAS table.
18
19
20===============================================
21Device Scoped Memory Affinity Structure (DSMAS)
22===============================================
23
24The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
25Length.
26
27This table is used by Linux in conjunction with the Device Scoped Latency and
28Bandwidth Information Structure (DSLBIS) to determine the performance
29attributes of the CXL device itself.
30
31Example ::
32
33 Structure Type : 00 [DSMAS]
34 Reserved : 00
35 Length : 0018 <- 24d, size of structure
36 DSMADHandle : 01
37 Flags : 00
38 Reserved : 0000
39 DPA Base : 0000000040000000 <- 1GiB base
40 DPA Length : 0000000080000000 <- 2GiB size
41
42
43==================================================================
44Device Scoped Latency and Bandwidth Information Structure (DSLBIS)
45==================================================================
46
47This table is used by Linux in conjunction with DSMAS to determine the
48performance attributes of a CXL device. The DSLBIS contains latency
49and bandwidth information based on DSMADHandle matching.
50
51Example ::
52
53 Structure Type : 01 [DSLBIS]
54 Reserved : 00
55 Length : 18 <- 24d, size of structure
56 Handle : 0001 <- DSMAS handle
57 Flags : 00 <- Matches flag field for HMAT SLLBIS
58 Data Type : 00 <- Latency
59 Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
60 Entry : 010000000000 <- First byte used here, CXL LTC
61 Reserved : 0000
62
63 Structure Type : 01 [DSLBIS]
64 Reserved : 00
65 Length : 18 <- 24d, size of structure
66 Handle : 0001 <- DSMAS handle
67 Flags : 00 <- Matches flag field for HMAT SLLBIS
68 Data Type : 03 <- Bandwidth
69 Entry Basee Unit : 0000000000001000 <- Entry Base Unit field in HMAT SSLBIS
70 Entry : 020000000000 <- First byte used here, CXL BW
71 Reserved : 0000
72
73
74==================================================================
75Switch Scoped Latency and Bandwidth Information Structure (SSLBIS)
76==================================================================
77
78The SSLBIS contains information about the latency and bandwidth of a switch.
79
80The table is used by Linux to compute the performance coordinates of a CXL path
81from the device to the root port where a switch is part of the path.
82
83Example ::
84
85 Structure Type : 05 [SSLBIS]
86 Reserved : 00
87 Length : 20 <- 32d, length of record, including SSLB entries
88 Data Type : 00 <- Latency
89 Reserved : 000000
90 Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
91
92 <- SSLB Entry 0
93 Port X ID : 0100 <- First port, 0100h represents an upstream port
94 Port Y ID : 0000 <- Second port, downstream port 0
95 Latency : 0100 <- Port latency
96 Reserved : 0000
97 <- SSLB Entry 1
98 Port X ID : 0100
99 Port Y ID : 0001
100 Latency : 0100
101 Reserved : 0000
102
103
104 Structure Type : 05 [SSLBIS]
105 Reserved : 00
106 Length : 18 <- 24d, length of record, including SSLB entry
107 Data Type : 03 <- Bandwidth
108 Reserved : 000000
109 Entry Base Unit : 00000000000000001000 <- Matches Entry Base Unit in HMAT SSLBIS
110
111 <- SSLB Entry 0
112 Port X ID : 0100 <- First port, 0100h represents an upstream port
113 Port Y ID : FFFF <- Second port, FFFFh indicates any port
114 Bandwidth : 1200 <- Port bandwidth
115 Reserved : 0000
116
117The CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
118generate "whole path performance" data for a CXL device.