tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1.. SPDX-License-Identifier: GPL-2.0
2
3================================
4CEDT - CXL Early Discovery Table
5================================
6
7The CXL Early Discovery Table is generated by BIOS to describe the CXL memory
8regions configured at boot by the BIOS.
9
10CHBS
11====
12The CXL Host Bridge Structure describes CXL host bridges. Other than describing
13device register information, it reports the specific host bridge UID for this
14host bridge. These host bridge ID's will be referenced in other tables.
15
16Example ::
17
18 Subtable Type : 00 [CXL Host Bridge Structure]
19 Reserved : 00
20 Length : 0020
21 Associated host bridge : 00000007 <- Host bridge _UID
22 Specification version : 00000001
23 Reserved : 00000000
24 Register base : 0000010370400000
25 Register length : 0000000000010000
26
27CFMWS
28=====
29The CXL Fixed Memory Window structure describes a memory region associated
30with one or more CXL host bridges (as described by the CHBS). It additionally
31describes any inter-host-bridge interleave configuration that may have been
32programmed by BIOS.
33
34Example ::
35
36 Subtable Type : 01 [CXL Fixed Memory Window Structure]
37 Reserved : 00
38 Length : 002C
39 Reserved : 00000000
40 Window base address : 000000C050000000 <- Memory Region
41 Window size : 0000003CA0000000
42 Interleave Members (2^n) : 01 <- Interleave configuration
43 Interleave Arithmetic : 00
44 Reserved : 0000
45 Granularity : 00000000
46 Restrictions : 0006
47 QtgId : 0001
48 First Target : 00000007 <- Host Bridge _UID
49 Next Target : 00000006 <- Host Bridge _UID
50
51The restriction field dictates what this SPA range may be used for (memory type,
52voltile vs persistent, etc). One or more bits may be set. ::
53
54 Bit[0]: CXL Type 2 Memory
55 Bit[1]: CXL Type 3 Memory
56 Bit[2]: Volatile Memory
57 Bit[3]: Persistent Memory
58 Bit[4]: Fixed Config (HPA cannot be re-used)
59
60INTRA-host-bridge interleave (multiple devices on one host bridge) is NOT
61reported in this structure, and is solely defined via CXL device decoder
62programming (host bridge and endpoint decoders).