tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm CAMSS ISP
8
9maintainers:
10 - Robert Foss <robert.foss@linaro.org>
11 - Todor Tomov <todor.too@gmail.com>
12
13description: |
14 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
15
16properties:
17 compatible:
18 const: qcom,msm8996-camss
19
20 clocks:
21 minItems: 36
22 maxItems: 36
23
24 clock-names:
25 items:
26 - const: top_ahb
27 - const: ispif_ahb
28 - const: csiphy0_timer
29 - const: csiphy1_timer
30 - const: csiphy2_timer
31 - const: csi0_ahb
32 - const: csi0
33 - const: csi0_phy
34 - const: csi0_pix
35 - const: csi0_rdi
36 - const: csi1_ahb
37 - const: csi1
38 - const: csi1_phy
39 - const: csi1_pix
40 - const: csi1_rdi
41 - const: csi2_ahb
42 - const: csi2
43 - const: csi2_phy
44 - const: csi2_pix
45 - const: csi2_rdi
46 - const: csi3_ahb
47 - const: csi3
48 - const: csi3_phy
49 - const: csi3_pix
50 - const: csi3_rdi
51 - const: ahb
52 - const: vfe0
53 - const: csi_vfe0
54 - const: vfe0_ahb
55 - const: vfe0_stream
56 - const: vfe1
57 - const: csi_vfe1
58 - const: vfe1_ahb
59 - const: vfe1_stream
60 - const: vfe_ahb
61 - const: vfe_axi
62
63 interrupts:
64 minItems: 10
65 maxItems: 10
66
67 interrupt-names:
68 items:
69 - const: csiphy0
70 - const: csiphy1
71 - const: csiphy2
72 - const: csid0
73 - const: csid1
74 - const: csid2
75 - const: csid3
76 - const: ispif
77 - const: vfe0
78 - const: vfe1
79
80 iommus:
81 maxItems: 4
82
83 power-domains:
84 items:
85 - description: VFE0 GDSC - Video Front End, Global Distributed Switch Controller.
86 - description: VFE1 GDSC - Video Front End, Global Distributed Switch Controller.
87
88 ports:
89 $ref: /schemas/graph.yaml#/properties/ports
90
91 description:
92 CSI input ports.
93
94 properties:
95 port@0:
96 $ref: /schemas/graph.yaml#/$defs/port-base
97 unevaluatedProperties: false
98 description:
99 Input port for receiving CSI data.
100
101 properties:
102 endpoint:
103 $ref: video-interfaces.yaml#
104 unevaluatedProperties: false
105
106 properties:
107 data-lanes:
108 description:
109 An array of physical data lanes indexes.
110 Position of an entry determines the logical
111 lane number, while the value of an entry
112 indicates physical lane index. Lane swapping
113 is supported. Physical lane indexes are;
114 0, 1, 2, 3
115 minItems: 1
116 maxItems: 4
117
118 bus-type:
119 enum:
120 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
121 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
122
123 required:
124 - data-lanes
125
126 port@1:
127 $ref: /schemas/graph.yaml#/$defs/port-base
128 unevaluatedProperties: false
129 description:
130 Input port for receiving CSI data.
131
132 properties:
133 endpoint:
134 $ref: video-interfaces.yaml#
135 unevaluatedProperties: false
136
137 properties:
138 data-lanes:
139 minItems: 1
140 maxItems: 4
141
142 bus-type:
143 enum:
144 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
145 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
146
147 required:
148 - data-lanes
149
150 port@2:
151 $ref: /schemas/graph.yaml#/$defs/port-base
152 unevaluatedProperties: false
153 description:
154 Input port for receiving CSI data.
155
156 properties:
157 endpoint:
158 $ref: video-interfaces.yaml#
159 unevaluatedProperties: false
160
161 properties:
162 data-lanes:
163 minItems: 1
164 maxItems: 4
165
166 bus-type:
167 enum:
168 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
169 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
170
171 required:
172 - data-lanes
173
174 port@3:
175 $ref: /schemas/graph.yaml#/$defs/port-base
176 unevaluatedProperties: false
177 description:
178 Input port for receiving CSI data.
179
180 properties:
181 endpoint:
182 $ref: video-interfaces.yaml#
183 unevaluatedProperties: false
184
185 properties:
186 data-lanes:
187 minItems: 1
188 maxItems: 4
189
190 bus-type:
191 enum:
192 - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
193 - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
194
195 required:
196 - data-lanes
197
198 reg:
199 minItems: 14
200 maxItems: 14
201
202 reg-names:
203 items:
204 - const: csiphy0
205 - const: csiphy0_clk_mux
206 - const: csiphy1
207 - const: csiphy1_clk_mux
208 - const: csiphy2
209 - const: csiphy2_clk_mux
210 - const: csid0
211 - const: csid1
212 - const: csid2
213 - const: csid3
214 - const: ispif
215 - const: csi_clk_mux
216 - const: vfe0
217 - const: vfe1
218
219 vdda-supply:
220 description:
221 Definition of the regulator used as analog power supply.
222
223required:
224 - clock-names
225 - clocks
226 - compatible
227 - interrupt-names
228 - interrupts
229 - iommus
230 - power-domains
231 - reg
232 - reg-names
233 - vdda-supply
234
235additionalProperties: false
236
237examples:
238 - |
239 #include <dt-bindings/interrupt-controller/arm-gic.h>
240 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
241 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
242
243 camss: camss@a34000 {
244 compatible = "qcom,msm8996-camss";
245
246 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
247 <&mmcc CAMSS_ISPIF_AHB_CLK>,
248 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
249 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
250 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
251 <&mmcc CAMSS_CSI0_AHB_CLK>,
252 <&mmcc CAMSS_CSI0_CLK>,
253 <&mmcc CAMSS_CSI0PHY_CLK>,
254 <&mmcc CAMSS_CSI0PIX_CLK>,
255 <&mmcc CAMSS_CSI0RDI_CLK>,
256 <&mmcc CAMSS_CSI1_AHB_CLK>,
257 <&mmcc CAMSS_CSI1_CLK>,
258 <&mmcc CAMSS_CSI1PHY_CLK>,
259 <&mmcc CAMSS_CSI1PIX_CLK>,
260 <&mmcc CAMSS_CSI1RDI_CLK>,
261 <&mmcc CAMSS_CSI2_AHB_CLK>,
262 <&mmcc CAMSS_CSI2_CLK>,
263 <&mmcc CAMSS_CSI2PHY_CLK>,
264 <&mmcc CAMSS_CSI2PIX_CLK>,
265 <&mmcc CAMSS_CSI2RDI_CLK>,
266 <&mmcc CAMSS_CSI3_AHB_CLK>,
267 <&mmcc CAMSS_CSI3_CLK>,
268 <&mmcc CAMSS_CSI3PHY_CLK>,
269 <&mmcc CAMSS_CSI3PIX_CLK>,
270 <&mmcc CAMSS_CSI3RDI_CLK>,
271 <&mmcc CAMSS_AHB_CLK>,
272 <&mmcc CAMSS_VFE0_CLK>,
273 <&mmcc CAMSS_CSI_VFE0_CLK>,
274 <&mmcc CAMSS_VFE0_AHB_CLK>,
275 <&mmcc CAMSS_VFE0_STREAM_CLK>,
276 <&mmcc CAMSS_VFE1_CLK>,
277 <&mmcc CAMSS_CSI_VFE1_CLK>,
278 <&mmcc CAMSS_VFE1_AHB_CLK>,
279 <&mmcc CAMSS_VFE1_STREAM_CLK>,
280 <&mmcc CAMSS_VFE_AHB_CLK>,
281 <&mmcc CAMSS_VFE_AXI_CLK>;
282
283 clock-names = "top_ahb",
284 "ispif_ahb",
285 "csiphy0_timer",
286 "csiphy1_timer",
287 "csiphy2_timer",
288 "csi0_ahb",
289 "csi0",
290 "csi0_phy",
291 "csi0_pix",
292 "csi0_rdi",
293 "csi1_ahb",
294 "csi1",
295 "csi1_phy",
296 "csi1_pix",
297 "csi1_rdi",
298 "csi2_ahb",
299 "csi2",
300 "csi2_phy",
301 "csi2_pix",
302 "csi2_rdi",
303 "csi3_ahb",
304 "csi3",
305 "csi3_phy",
306 "csi3_pix",
307 "csi3_rdi",
308 "ahb",
309 "vfe0",
310 "csi_vfe0",
311 "vfe0_ahb",
312 "vfe0_stream",
313 "vfe1",
314 "csi_vfe1",
315 "vfe1_ahb",
316 "vfe1_stream",
317 "vfe_ahb",
318 "vfe_axi";
319
320 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
321 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
322 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
323 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
324 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
325 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
326 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
327 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
328 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
329 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
330
331 interrupt-names = "csiphy0",
332 "csiphy1",
333 "csiphy2",
334 "csid0",
335 "csid1",
336 "csid2",
337 "csid3",
338 "ispif",
339 "vfe0",
340 "vfe1";
341
342 iommus = <&vfe_smmu 0>,
343 <&vfe_smmu 1>,
344 <&vfe_smmu 2>,
345 <&vfe_smmu 3>;
346
347 power-domains = <&mmcc VFE0_GDSC>,
348 <&mmcc VFE1_GDSC>;
349
350 reg = <0x00a34000 0x1000>,
351 <0x00a00030 0x4>,
352 <0x00a35000 0x1000>,
353 <0x00a00038 0x4>,
354 <0x00a36000 0x1000>,
355 <0x00a00040 0x4>,
356 <0x00a30000 0x100>,
357 <0x00a30400 0x100>,
358 <0x00a30800 0x100>,
359 <0x00a30c00 0x100>,
360 <0x00a31000 0x500>,
361 <0x00a00020 0x10>,
362 <0x00a10000 0x1000>,
363 <0x00a14000 0x1000>;
364
365 reg-names = "csiphy0",
366 "csiphy0_clk_mux",
367 "csiphy1",
368 "csiphy1_clk_mux",
369 "csiphy2",
370 "csiphy2_clk_mux",
371 "csid0",
372 "csid1",
373 "csid2",
374 "csid3",
375 "ispif",
376 "csi_clk_mux",
377 "vfe0",
378 "vfe1";
379
380 vdda-supply = <®_2v8>;
381
382 ports {
383 #address-cells = <1>;
384 #size-cells = <0>;
385 };
386 };