Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Video Decode Accelerator
8
9maintainers:
10 - Yunfei Dong <yunfei.dong@mediatek.com>
11
12description: |+
13 Mediatek Video Decode is the video decode hardware present in Mediatek
14 SoCs which supports high resolution decoding functionalities.
15
16properties:
17 compatible:
18 enum:
19 - mediatek,mt8173-vcodec-dec
20 - mediatek,mt8183-vcodec-dec
21
22 reg:
23 minItems: 11
24 maxItems: 11
25
26 reg-names:
27 items:
28 - const: misc
29 - const: ld
30 - const: top
31 - const: cm
32 - const: ad
33 - const: av
34 - const: pp
35 - const: hwd
36 - const: hwq
37 - const: hwb
38 - const: hwg
39
40 interrupts:
41 maxItems: 1
42
43 clocks:
44 minItems: 1
45 maxItems: 8
46
47 clock-names:
48 minItems: 1
49 maxItems: 8
50
51 assigned-clocks: true
52
53 assigned-clock-parents: true
54
55 assigned-clock-rates: true
56
57 power-domains:
58 maxItems: 1
59
60 iommus:
61 minItems: 1
62 maxItems: 32
63 description: |
64 List of the hardware port in respective IOMMU block for current Socs.
65 Refer to bindings/iommu/mediatek,iommu.yaml.
66
67 mediatek,vpu:
68 $ref: /schemas/types.yaml#/definitions/phandle
69 description:
70 Describes point to vpu.
71
72 mediatek,scp:
73 $ref: /schemas/types.yaml#/definitions/phandle
74 description:
75 Describes point to scp.
76
77 mediatek,vdecsys:
78 $ref: /schemas/types.yaml#/definitions/phandle
79 description: Phandle to the vdecsys syscon node.
80
81required:
82 - compatible
83 - reg
84 - interrupts
85 - clocks
86 - clock-names
87 - iommus
88 - mediatek,vdecsys
89
90allOf:
91 - if:
92 properties:
93 compatible:
94 contains:
95 enum:
96 - mediatek,mt8183-vcodec-dec
97
98 then:
99 required:
100 - mediatek,scp
101
102 properties:
103 clocks:
104 minItems: 1
105 maxItems: 1
106
107 clock-names:
108 items:
109 - const: vdec
110
111 - if:
112 properties:
113 compatible:
114 contains:
115 enum:
116 - mediatek,mt8173-vcodec-dec
117
118 then:
119 required:
120 - mediatek,vpu
121
122 properties:
123 clocks:
124 minItems: 8
125 maxItems: 8
126
127 clock-names:
128 items:
129 - const: vcodecpll
130 - const: univpll_d2
131 - const: clk_cci400_sel
132 - const: vdec_sel
133 - const: vdecpll
134 - const: vencpll
135 - const: venc_lt_sel
136 - const: vdec_bus_clk_src
137
138additionalProperties: false
139
140examples:
141 - |
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
143 #include <dt-bindings/clock/mt8173-clk.h>
144 #include <dt-bindings/memory/mt8173-larb-port.h>
145 #include <dt-bindings/interrupt-controller/irq.h>
146 #include <dt-bindings/power/mt8173-power.h>
147
148 vcodec_dec: vcodec@16020000 {
149 compatible = "mediatek,mt8173-vcodec-dec";
150 reg = <0x16020000 0x1000>, /*VDEC_MISC*/
151 <0x16021000 0x800>, /*VDEC_LD*/
152 <0x16021800 0x800>, /*VDEC_TOP*/
153 <0x16022000 0x1000>, /*VDEC_CM*/
154 <0x16023000 0x1000>, /*VDEC_AD*/
155 <0x16024000 0x1000>, /*VDEC_AV*/
156 <0x16025000 0x1000>, /*VDEC_PP*/
157 <0x16026800 0x800>, /*VP8_VD*/
158 <0x16027000 0x800>, /*VP6_VD*/
159 <0x16027800 0x800>, /*VP8_VL*/
160 <0x16028400 0x400>; /*VP9_VD*/
161 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
162 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
163 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
164 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
165 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
166 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
167 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
168 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
169 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
170 mediatek,vpu = <&vpu>;
171 mediatek,vdecsys = <&vdecsys>;
172 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
173 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
174 <&topckgen CLK_TOP_UNIVPLL_D2>,
175 <&topckgen CLK_TOP_CCI400_SEL>,
176 <&topckgen CLK_TOP_VDEC_SEL>,
177 <&topckgen CLK_TOP_VCODECPLL>,
178 <&apmixedsys CLK_APMIXED_VENCPLL>,
179 <&topckgen CLK_TOP_VENC_LT_SEL>,
180 <&topckgen CLK_TOP_VCODECPLL_370P5>;
181 clock-names = "vcodecpll",
182 "univpll_d2",
183 "clk_cci400_sel",
184 "vdec_sel",
185 "vdecpll",
186 "vencpll",
187 "venc_lt_sel",
188 "vdec_bus_clk_src";
189 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
190 <&topckgen CLK_TOP_CCI400_SEL>,
191 <&topckgen CLK_TOP_VDEC_SEL>,
192 <&apmixedsys CLK_APMIXED_VCODECPLL>,
193 <&apmixedsys CLK_APMIXED_VENCPLL>;
194 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
195 <&topckgen CLK_TOP_UNIVPLL_D2>,
196 <&topckgen CLK_TOP_VCODECPLL>;
197 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
198 };