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Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dc-blit-engine.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale i.MX8qxp Display Controller Blit Engine
8
9description: |
10 A blit operation (block based image transfer) reads up to 3 source images
11 from memory and computes one destination image from it, which is written
12 back to memory. The following basic operations are supported:
13
14 * Buffer Fill
15 Fills a buffer with constant color
16
17 * Buffer Copy
18 Copies one source to a destination buffer.
19
20 * Image Blend
21 Combines two source images by a blending equation and writes result to
22 destination (which can be one of the sources).
23
24 * Image Rop2/3
25 Combines up to three source images by a logical equation (raster operation)
26 and writes result to destination (which can be one of the sources).
27
28 * Image Flip
29 Mirrors the source image in horizontal and/or vertical direction.
30
31 * Format Convert
32 Convert between the supported color and buffer formats.
33
34 * Color Transform
35 Modify colors by linear or non-linear transformations.
36
37 * Image Scale
38 Changes size of the source image.
39
40 * Image Rotate
41 Rotates the source image by any angle.
42
43 * Image Filter
44 Performs an FIR filter operation on the source image.
45
46 * Image Warp
47 Performs a re-sampling of the source image with any pattern. The sample
48 point positions are read from a compressed coordinate buffer.
49
50 * Buffer Pack
51 Writes an image with color components stored in up to three different
52 buffers (planar formats) into a single buffer (packed format).
53
54 * Chroma Resample
55 Converts between different YUV formats that differ in chroma sampling rate
56 (4:4:4, 4:2:2, 4:2:0).
57
58maintainers:
59 - Liu Ying <victor.liu@nxp.com>
60
61properties:
62 compatible:
63 const: fsl,imx8qxp-dc-blit-engine
64
65 reg:
66 maxItems: 2
67
68 reg-names:
69 items:
70 - const: pec
71 - const: cfg
72
73 "#address-cells":
74 const: 1
75
76 "#size-cells":
77 const: 1
78
79 ranges: true
80
81patternProperties:
82 "^blitblend@[0-9a-f]+$":
83 type: object
84 additionalProperties: true
85
86 properties:
87 compatible:
88 const: fsl,imx8qxp-dc-blitblend
89
90 "^clut@[0-9a-f]+$":
91 type: object
92 additionalProperties: true
93
94 properties:
95 compatible:
96 const: fsl,imx8qxp-dc-clut
97
98 "^fetchdecode@[0-9a-f]+$":
99 type: object
100 additionalProperties: true
101
102 properties:
103 compatible:
104 const: fsl,imx8qxp-dc-fetchdecode
105
106 "^fetcheco@[0-9a-f]+$":
107 type: object
108 additionalProperties: true
109
110 properties:
111 compatible:
112 const: fsl,imx8qxp-dc-fetcheco
113
114 "^fetchwarp@[0-9a-f]+$":
115 type: object
116 additionalProperties: true
117
118 properties:
119 compatible:
120 const: fsl,imx8qxp-dc-fetchwarp
121
122 "^filter@[0-9a-f]+$":
123 type: object
124 additionalProperties: true
125
126 properties:
127 compatible:
128 const: fsl,imx8qxp-dc-filter
129
130 "^hscaler@[0-9a-f]+$":
131 type: object
132 additionalProperties: true
133
134 properties:
135 compatible:
136 const: fsl,imx8qxp-dc-hscaler
137
138 "^matrix@[0-9a-f]+$":
139 type: object
140 additionalProperties: true
141
142 properties:
143 compatible:
144 const: fsl,imx8qxp-dc-matrix
145
146 "^rop@[0-9a-f]+$":
147 type: object
148 additionalProperties: true
149
150 properties:
151 compatible:
152 const: fsl,imx8qxp-dc-rop
153
154 "^store@[0-9a-f]+$":
155 type: object
156 additionalProperties: true
157
158 properties:
159 compatible:
160 const: fsl,imx8qxp-dc-store
161
162 "^vscaler@[0-9a-f]+$":
163 type: object
164 additionalProperties: true
165
166 properties:
167 compatible:
168 const: fsl,imx8qxp-dc-vscaler
169
170required:
171 - compatible
172 - reg
173 - reg-names
174 - "#address-cells"
175 - "#size-cells"
176 - ranges
177
178additionalProperties: false
179
180examples:
181 - |
182 blit-engine@56180820 {
183 compatible = "fsl,imx8qxp-dc-blit-engine";
184 reg = <0x56180820 0x13c>, <0x56181000 0x3400>;
185 reg-names = "pec", "cfg";
186 #address-cells = <1>;
187 #size-cells = <1>;
188 ranges;
189
190 fetchdecode@56180820 {
191 compatible = "fsl,imx8qxp-dc-fetchdecode";
192 reg = <0x56180820 0x10>, <0x56181000 0x404>;
193 reg-names = "pec", "cfg";
194 };
195
196 store@56180940 {
197 compatible = "fsl,imx8qxp-dc-store";
198 reg = <0x56180940 0x1c>, <0x56184000 0x5c>;
199 reg-names = "pec", "cfg";
200 interrupt-parent = <&dc0_intc>;
201 interrupts = <0>, <1>, <2>;
202 interrupt-names = "shdload", "framecomplete", "seqcomplete";
203 };
204 };