tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Analog Devices ADF4371 SPI Wideband Synthesizer driver
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7#include "linux/dev_printk.h"
8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/gcd.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/regmap.h>
16#include <linux/sysfs.h>
17#include <linux/spi/spi.h>
18
19#include <linux/iio/iio.h>
20
21/* Registers address macro */
22#define ADF4371_REG(x) (x)
23
24/* ADF4371_REG0 */
25#define ADF4371_ADDR_ASC_MSK BIT(2)
26#define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x)
27#define ADF4371_ADDR_ASC_R_MSK BIT(5)
28#define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x)
29#define ADF4371_RESET_CMD 0x81
30
31/* ADF4371_REG17 */
32#define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1)
33#define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x)
34#define ADF4371_FRAC1WORD_MSK BIT(0)
35#define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x)
36
37/* ADF4371_REG18 */
38#define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0)
39#define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x)
40
41/* ADF4371_REG1A */
42#define ADF4371_MOD2WORD_MSK GENMASK(5, 0)
43#define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x)
44
45/* ADF4371_REG22 */
46#define ADF4371_REFIN_MODE_MASK BIT(6)
47#define ADF4371_REFIN_MODE(x) FIELD_PREP(ADF4371_REFIN_MODE_MASK, x)
48#define ADF4371_REF_DOUB_MASK BIT(5)
49#define ADF4371_REF_DOUB(x) FIELD_PREP(ADF4371_REF_DOUB_MASK, x)\
50
51/* ADF4371_REG24 */
52#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4)
53#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x)
54
55/* ADF4371_REG25 */
56#define ADF4371_MUTE_LD_MSK BIT(7)
57#define ADF4371_MUTE_LD(x) FIELD_PREP(ADF4371_MUTE_LD_MSK, x)
58
59/* ADF4371_REG32 */
60#define ADF4371_TIMEOUT_MSK GENMASK(1, 0)
61#define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x)
62
63/* ADF4371_REG34 */
64#define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0)
65#define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x)
66
67/* Specifications */
68#define ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */
69#define ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */
70#define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */
71#define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */
72#define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */
73#define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */
74#define ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */
75#define ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */
76
77#define ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */
78#define ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */
79#define ADF4371_MAX_FREQ_REFIN_SE 500000000UL /* Hz */
80
81#define ADF4371_MIN_CLKIN_DOUB_FREQ 10000000ULL /* Hz */
82#define ADF4371_MAX_CLKIN_DOUB_FREQ 125000000ULL /* Hz */
83
84/* MOD1 is a 24-bit primary modulus with fixed value of 2^25 */
85#define ADF4371_MODULUS1 33554432ULL
86/* MOD2 is the programmable, 14-bit auxiliary fractional modulus */
87#define ADF4371_MAX_MODULUS2 BIT(14)
88
89#define ADF4371_CHECK_RANGE(freq, range) \
90 ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range))
91
92enum {
93 ADF4371_FREQ,
94 ADF4371_POWER_DOWN,
95 ADF4371_CHANNEL_NAME
96};
97
98enum {
99 ADF4371_CH_RF8,
100 ADF4371_CH_RFAUX8,
101 ADF4371_CH_RF16,
102 ADF4371_CH_RF32
103};
104
105enum adf4371_variant {
106 ADF4371,
107 ADF4372
108};
109
110struct adf4371_pwrdown {
111 unsigned int reg;
112 unsigned int bit;
113};
114
115static const char * const adf4371_ch_names[] = {
116 "RF8x", "RFAUX8x", "RF16x", "RF32x"
117};
118
119static const struct adf4371_pwrdown adf4371_pwrdown_ch[4] = {
120 [ADF4371_CH_RF8] = { ADF4371_REG(0x25), 2 },
121 [ADF4371_CH_RFAUX8] = { ADF4371_REG(0x72), 3 },
122 [ADF4371_CH_RF16] = { ADF4371_REG(0x25), 3 },
123 [ADF4371_CH_RF32] = { ADF4371_REG(0x25), 4 },
124};
125
126static const struct reg_sequence adf4371_reg_defaults[] = {
127 { ADF4371_REG(0x0), 0x18 },
128 { ADF4371_REG(0x12), 0x40 },
129 { ADF4371_REG(0x1E), 0x48 },
130 { ADF4371_REG(0x20), 0x14 },
131 { ADF4371_REG(0x22), 0x00 },
132 { ADF4371_REG(0x23), 0x00 },
133 { ADF4371_REG(0x24), 0x80 },
134 { ADF4371_REG(0x25), 0x07 },
135 { ADF4371_REG(0x27), 0xC5 },
136 { ADF4371_REG(0x28), 0x83 },
137 { ADF4371_REG(0x2C), 0x44 },
138 { ADF4371_REG(0x2D), 0x11 },
139 { ADF4371_REG(0x2E), 0x12 },
140 { ADF4371_REG(0x2F), 0x94 },
141 { ADF4371_REG(0x32), 0x04 },
142 { ADF4371_REG(0x35), 0xFA },
143 { ADF4371_REG(0x36), 0x30 },
144 { ADF4371_REG(0x39), 0x07 },
145 { ADF4371_REG(0x3A), 0x55 },
146 { ADF4371_REG(0x3E), 0x0C },
147 { ADF4371_REG(0x3F), 0x80 },
148 { ADF4371_REG(0x40), 0x50 },
149 { ADF4371_REG(0x41), 0x28 },
150 { ADF4371_REG(0x47), 0xC0 },
151 { ADF4371_REG(0x52), 0xF4 },
152 { ADF4371_REG(0x70), 0x03 },
153 { ADF4371_REG(0x71), 0x60 },
154 { ADF4371_REG(0x72), 0x32 },
155};
156
157static const struct regmap_config adf4371_regmap_config = {
158 .reg_bits = 16,
159 .val_bits = 8,
160 .read_flag_mask = BIT(7),
161};
162
163struct adf4371_chip_info {
164 const char *name;
165 unsigned int num_channels;
166 const struct iio_chan_spec *channels;
167};
168
169struct adf4371_state {
170 struct spi_device *spi;
171 struct regmap *regmap;
172 /*
173 * Lock for accessing device registers. Some operations require
174 * multiple consecutive R/W operations, during which the device
175 * shouldn't be interrupted. The buffers are also shared across
176 * all operations so need to be protected on stand alone reads and
177 * writes.
178 */
179 struct mutex lock;
180 const struct adf4371_chip_info *chip_info;
181 unsigned long clkin_freq;
182 unsigned long fpfd;
183 unsigned int integer;
184 unsigned int fract1;
185 unsigned int fract2;
186 unsigned int mod2;
187 unsigned int rf_div_sel;
188 unsigned int ref_div_factor;
189 bool ref_diff_en;
190 u8 buf[10] __aligned(IIO_DMA_MINALIGN);
191};
192
193static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,
194 u32 channel)
195{
196 unsigned long long val, tmp;
197 unsigned int ref_div_sel;
198
199 val = (((u64)st->integer * ADF4371_MODULUS1) + st->fract1) * st->fpfd;
200 tmp = (u64)st->fract2 * st->fpfd;
201 do_div(tmp, st->mod2);
202 val += tmp + ADF4371_MODULUS1 / 2;
203
204 if (channel == ADF4371_CH_RF8 || channel == ADF4371_CH_RFAUX8)
205 ref_div_sel = st->rf_div_sel;
206 else
207 ref_div_sel = 0;
208
209 do_div(val, ADF4371_MODULUS1 * (1 << ref_div_sel));
210
211 if (channel == ADF4371_CH_RF16)
212 val <<= 1;
213 else if (channel == ADF4371_CH_RF32)
214 val <<= 2;
215
216 return val;
217}
218
219static void adf4371_pll_fract_n_compute(unsigned long long vco,
220 unsigned long long pfd,
221 unsigned int *integer,
222 unsigned int *fract1,
223 unsigned int *fract2,
224 unsigned int *mod2)
225{
226 unsigned long long tmp;
227 u32 gcd_div;
228
229 tmp = do_div(vco, pfd);
230 tmp = tmp * ADF4371_MODULUS1;
231 *fract2 = do_div(tmp, pfd);
232
233 *integer = vco;
234 *fract1 = tmp;
235
236 *mod2 = pfd;
237
238 while (*mod2 > ADF4371_MAX_MODULUS2) {
239 *mod2 >>= 1;
240 *fract2 >>= 1;
241 }
242
243 gcd_div = gcd(*fract2, *mod2);
244 *mod2 /= gcd_div;
245 *fract2 /= gcd_div;
246}
247
248static int adf4371_set_freq(struct adf4371_state *st, unsigned long long freq,
249 unsigned int channel)
250{
251 u32 cp_bleed;
252 u8 int_mode = 0;
253 int ret;
254
255 switch (channel) {
256 case ADF4371_CH_RF8:
257 case ADF4371_CH_RFAUX8:
258 if (ADF4371_CHECK_RANGE(freq, OUT_RF8_FREQ))
259 return -EINVAL;
260
261 st->rf_div_sel = 0;
262
263 while (freq < ADF4371_MIN_VCO_FREQ) {
264 freq <<= 1;
265 st->rf_div_sel++;
266 }
267 break;
268 case ADF4371_CH_RF16:
269 /* ADF4371 RF16 8000...16000 MHz */
270 if (ADF4371_CHECK_RANGE(freq, OUT_RF16_FREQ))
271 return -EINVAL;
272
273 freq >>= 1;
274 break;
275 case ADF4371_CH_RF32:
276 /* ADF4371 RF32 16000...32000 MHz */
277 if (ADF4371_CHECK_RANGE(freq, OUT_RF32_FREQ))
278 return -EINVAL;
279
280 freq >>= 2;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 adf4371_pll_fract_n_compute(freq, st->fpfd, &st->integer, &st->fract1,
287 &st->fract2, &st->mod2);
288 st->buf[0] = st->integer >> 8;
289 st->buf[1] = 0x40; /* REG12 default */
290 st->buf[2] = 0x00;
291 st->buf[3] = st->fract1 & 0xFF;
292 st->buf[4] = st->fract1 >> 8;
293 st->buf[5] = st->fract1 >> 16;
294 st->buf[6] = ADF4371_FRAC2WORD_L(st->fract2 & 0x7F) |
295 ADF4371_FRAC1WORD(st->fract1 >> 24);
296 st->buf[7] = ADF4371_FRAC2WORD_H(st->fract2 >> 7);
297 st->buf[8] = st->mod2 & 0xFF;
298 st->buf[9] = ADF4371_MOD2WORD(st->mod2 >> 8);
299
300 ret = regmap_bulk_write(st->regmap, ADF4371_REG(0x11), st->buf, 10);
301 if (ret < 0)
302 return ret;
303 /*
304 * The R counter allows the input reference frequency to be
305 * divided down to produce the reference clock to the PFD
306 */
307 ret = regmap_write(st->regmap, ADF4371_REG(0x1F), st->ref_div_factor);
308 if (ret < 0)
309 return ret;
310
311 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x24),
312 ADF4371_RF_DIV_SEL_MSK,
313 ADF4371_RF_DIV_SEL(st->rf_div_sel));
314 if (ret < 0)
315 return ret;
316
317 cp_bleed = DIV_ROUND_UP(400 * 1750, st->integer * 375);
318 cp_bleed = clamp(cp_bleed, 1U, 255U);
319 ret = regmap_write(st->regmap, ADF4371_REG(0x26), cp_bleed);
320 if (ret < 0)
321 return ret;
322 /*
323 * Set to 1 when in INT mode (when FRAC1 = FRAC2 = 0),
324 * and set to 0 when in FRAC mode.
325 */
326 if (st->fract1 == 0 && st->fract2 == 0)
327 int_mode = 0x01;
328
329 ret = regmap_write(st->regmap, ADF4371_REG(0x2B), int_mode);
330 if (ret < 0)
331 return ret;
332
333 return regmap_write(st->regmap, ADF4371_REG(0x10), st->integer & 0xFF);
334}
335
336static ssize_t adf4371_read(struct iio_dev *indio_dev,
337 uintptr_t private,
338 const struct iio_chan_spec *chan,
339 char *buf)
340{
341 struct adf4371_state *st = iio_priv(indio_dev);
342 unsigned long long val = 0;
343 unsigned int readval, reg, bit;
344 int ret;
345
346 switch ((u32)private) {
347 case ADF4371_FREQ:
348 val = adf4371_pll_fract_n_get_rate(st, chan->channel);
349 ret = regmap_read(st->regmap, ADF4371_REG(0x7C), &readval);
350 if (ret < 0)
351 break;
352
353 if (readval == 0x00) {
354 dev_dbg(&st->spi->dev, "PLL un-locked\n");
355 ret = -EBUSY;
356 }
357 break;
358 case ADF4371_POWER_DOWN:
359 reg = adf4371_pwrdown_ch[chan->channel].reg;
360 bit = adf4371_pwrdown_ch[chan->channel].bit;
361
362 ret = regmap_read(st->regmap, reg, &readval);
363 if (ret < 0)
364 break;
365
366 val = !(readval & BIT(bit));
367 break;
368 case ADF4371_CHANNEL_NAME:
369 return sprintf(buf, "%s\n", adf4371_ch_names[chan->channel]);
370 default:
371 ret = -EINVAL;
372 val = 0;
373 break;
374 }
375
376 return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
377}
378
379static ssize_t adf4371_write(struct iio_dev *indio_dev,
380 uintptr_t private,
381 const struct iio_chan_spec *chan,
382 const char *buf, size_t len)
383{
384 struct adf4371_state *st = iio_priv(indio_dev);
385 unsigned long long freq;
386 bool power_down;
387 unsigned int bit, readval, reg;
388 int ret;
389
390 mutex_lock(&st->lock);
391 switch ((u32)private) {
392 case ADF4371_FREQ:
393 ret = kstrtoull(buf, 10, &freq);
394 if (ret)
395 break;
396
397 ret = adf4371_set_freq(st, freq, chan->channel);
398 break;
399 case ADF4371_POWER_DOWN:
400 ret = kstrtobool(buf, &power_down);
401 if (ret)
402 break;
403
404 reg = adf4371_pwrdown_ch[chan->channel].reg;
405 bit = adf4371_pwrdown_ch[chan->channel].bit;
406 ret = regmap_read(st->regmap, reg, &readval);
407 if (ret < 0)
408 break;
409
410 readval &= ~BIT(bit);
411 readval |= (!power_down << bit);
412
413 ret = regmap_write(st->regmap, reg, readval);
414 break;
415 default:
416 ret = -EINVAL;
417 break;
418 }
419 mutex_unlock(&st->lock);
420
421 return ret ? ret : len;
422}
423
424#define _ADF4371_EXT_INFO(_name, _ident) { \
425 .name = _name, \
426 .read = adf4371_read, \
427 .write = adf4371_write, \
428 .private = _ident, \
429 .shared = IIO_SEPARATE, \
430}
431
432static const struct iio_chan_spec_ext_info adf4371_ext_info[] = {
433 /*
434 * Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
435 * values > 2^32 in order to support the entire frequency range
436 * in Hz. Using scale is a bit ugly.
437 */
438 _ADF4371_EXT_INFO("frequency", ADF4371_FREQ),
439 _ADF4371_EXT_INFO("powerdown", ADF4371_POWER_DOWN),
440 _ADF4371_EXT_INFO("name", ADF4371_CHANNEL_NAME),
441 { }
442};
443
444#define ADF4371_CHANNEL(index) { \
445 .type = IIO_ALTVOLTAGE, \
446 .output = 1, \
447 .channel = index, \
448 .ext_info = adf4371_ext_info, \
449 .indexed = 1, \
450 }
451
452static const struct iio_chan_spec adf4371_chan[] = {
453 ADF4371_CHANNEL(ADF4371_CH_RF8),
454 ADF4371_CHANNEL(ADF4371_CH_RFAUX8),
455 ADF4371_CHANNEL(ADF4371_CH_RF16),
456 ADF4371_CHANNEL(ADF4371_CH_RF32),
457};
458
459static const struct adf4371_chip_info adf4371_chip_info = {
460 .name = "adf4371",
461 .channels = adf4371_chan,
462 .num_channels = 4,
463};
464
465static const struct adf4371_chip_info adf4372_chip_info = {
466 .name = "adf4372",
467 .channels = adf4371_chan,
468 .num_channels = 3,
469};
470
471static int adf4371_reg_access(struct iio_dev *indio_dev,
472 unsigned int reg,
473 unsigned int writeval,
474 unsigned int *readval)
475{
476 struct adf4371_state *st = iio_priv(indio_dev);
477
478 if (readval)
479 return regmap_read(st->regmap, reg, readval);
480 else
481 return regmap_write(st->regmap, reg, writeval);
482}
483
484static const struct iio_info adf4371_info = {
485 .debugfs_reg_access = &adf4371_reg_access,
486};
487
488static int adf4371_setup(struct adf4371_state *st)
489{
490 unsigned int synth_timeout = 2, timeout = 1, vco_alc_timeout = 1;
491 unsigned int vco_band_div, tmp, ref_doubler_en = 0;
492 int ret;
493
494 /* Perform a software reset */
495 ret = regmap_write(st->regmap, ADF4371_REG(0x0), ADF4371_RESET_CMD);
496 if (ret < 0)
497 return ret;
498
499 ret = regmap_multi_reg_write(st->regmap, adf4371_reg_defaults,
500 ARRAY_SIZE(adf4371_reg_defaults));
501 if (ret < 0)
502 return ret;
503
504 /* Mute to Lock Detect */
505 if (device_property_read_bool(&st->spi->dev, "adi,mute-till-lock-en")) {
506 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x25),
507 ADF4371_MUTE_LD_MSK,
508 ADF4371_MUTE_LD(1));
509 if (ret < 0)
510 return ret;
511 }
512
513 /* Set address in ascending order, so the bulk_write() will work */
514 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x0),
515 ADF4371_ADDR_ASC_MSK | ADF4371_ADDR_ASC_R_MSK,
516 ADF4371_ADDR_ASC(1) | ADF4371_ADDR_ASC_R(1));
517 if (ret < 0)
518 return ret;
519
520 if ((st->ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN) ||
521 (!st->ref_diff_en && st->clkin_freq > ADF4371_MAX_FREQ_REFIN_SE))
522 return -EINVAL;
523
524 if (st->clkin_freq < ADF4371_MAX_CLKIN_DOUB_FREQ &&
525 st->clkin_freq > ADF4371_MIN_CLKIN_DOUB_FREQ)
526 ref_doubler_en = 1;
527
528 ret = regmap_update_bits(st->regmap, ADF4371_REG(0x22),
529 ADF4371_REF_DOUB_MASK |
530 ADF4371_REFIN_MODE_MASK,
531 ADF4371_REF_DOUB(ref_doubler_en) |
532 ADF4371_REFIN_MODE(st->ref_diff_en));
533 if (ret < 0)
534 return ret;
535
536 /*
537 * Calculate and maximize PFD frequency
538 * fPFD = REFIN × ((1 + D)/(R × (1 + T)))
539 * Where D is the REFIN doubler bit, T is the reference divide by 2,
540 * R is the reference division factor
541 * TODO: it is assumed D and T equal 0.
542 */
543 do {
544 st->ref_div_factor++;
545 st->fpfd = st->clkin_freq * (1 + ref_doubler_en) /
546 st->ref_div_factor;
547 } while (st->fpfd > ADF4371_MAX_FREQ_PFD);
548
549 /* Calculate Timeouts */
550 vco_band_div = DIV_ROUND_UP(st->fpfd, 2400000U);
551
552 tmp = DIV_ROUND_CLOSEST(st->fpfd, 1000000U);
553 do {
554 timeout++;
555 if (timeout > 1023) {
556 timeout = 2;
557 synth_timeout++;
558 }
559 } while (synth_timeout * 1024 + timeout <= 20 * tmp);
560
561 do {
562 vco_alc_timeout++;
563 } while (vco_alc_timeout * 1024 - timeout <= 50 * tmp);
564
565 st->buf[0] = vco_band_div;
566 st->buf[1] = timeout & 0xFF;
567 st->buf[2] = ADF4371_TIMEOUT(timeout >> 8) | 0x04;
568 st->buf[3] = synth_timeout;
569 st->buf[4] = ADF4371_VCO_ALC_TOUT(vco_alc_timeout);
570
571 return regmap_bulk_write(st->regmap, ADF4371_REG(0x30), st->buf, 5);
572}
573
574static int adf4371_probe(struct spi_device *spi)
575{
576 struct iio_dev *indio_dev;
577 struct adf4371_state *st;
578 struct regmap *regmap;
579 struct clk *clkin;
580 int ret;
581
582 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
583 if (!indio_dev)
584 return -ENOMEM;
585
586 regmap = devm_regmap_init_spi(spi, &adf4371_regmap_config);
587 if (IS_ERR(regmap))
588 return dev_err_probe(&spi->dev, PTR_ERR(regmap),
589 "Error initializing spi regmap\n");
590
591 st = iio_priv(indio_dev);
592 st->spi = spi;
593 st->regmap = regmap;
594 mutex_init(&st->lock);
595
596 st->chip_info = spi_get_device_match_data(spi);
597 if (!st->chip_info)
598 return -ENODEV;
599
600 indio_dev->name = st->chip_info->name;
601 indio_dev->info = &adf4371_info;
602 indio_dev->modes = INDIO_DIRECT_MODE;
603 indio_dev->channels = st->chip_info->channels;
604 indio_dev->num_channels = st->chip_info->num_channels;
605
606 st->ref_diff_en = false;
607
608 clkin = devm_clk_get_enabled(&spi->dev, "clkin");
609 if (IS_ERR(clkin)) {
610 clkin = devm_clk_get_enabled(&spi->dev, "clkin-diff");
611 if (IS_ERR(clkin))
612 return dev_err_probe(&spi->dev, PTR_ERR(clkin),
613 "Failed to get clkin/clkin-diff\n");
614 st->ref_diff_en = true;
615 }
616
617 st->clkin_freq = clk_get_rate(clkin);
618
619 ret = adf4371_setup(st);
620 if (ret < 0)
621 return dev_err_probe(&spi->dev, ret, "ADF4371 setup failed\n");
622
623 return devm_iio_device_register(&spi->dev, indio_dev);
624}
625
626static const struct spi_device_id adf4371_id_table[] = {
627 { "adf4371", (kernel_ulong_t)&adf4371_chip_info },
628 { "adf4372", (kernel_ulong_t)&adf4372_chip_info },
629 { }
630};
631MODULE_DEVICE_TABLE(spi, adf4371_id_table);
632
633static const struct of_device_id adf4371_of_match[] = {
634 { .compatible = "adi,adf4371", .data = &adf4371_chip_info },
635 { .compatible = "adi,adf4372", .data = &adf4372_chip_info},
636 { }
637};
638MODULE_DEVICE_TABLE(of, adf4371_of_match);
639
640static struct spi_driver adf4371_driver = {
641 .driver = {
642 .name = "adf4371",
643 .of_match_table = adf4371_of_match,
644 },
645 .probe = adf4371_probe,
646 .id_table = adf4371_id_table,
647};
648module_spi_driver(adf4371_driver);
649
650MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
651MODULE_DESCRIPTION("Analog Devices ADF4371 SPI PLL");
652MODULE_LICENSE("GPL");