tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ADF4350/ADF4351 SPI Wideband Synthesizer driver
4 *
5 * Copyright 2012-2013 Analog Devices Inc.
6 */
7
8#include <linux/device.h>
9#include <linux/kernel.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
12#include <linux/property.h>
13#include <linux/slab.h>
14#include <linux/sysfs.h>
15#include <linux/spi/spi.h>
16#include <linux/regulator/consumer.h>
17#include <linux/err.h>
18#include <linux/gcd.h>
19#include <linux/gpio/consumer.h>
20#include <asm/div64.h>
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
23
24#include <linux/iio/iio.h>
25#include <linux/iio/sysfs.h>
26#include <linux/iio/frequency/adf4350.h>
27
28enum {
29 ADF4350_FREQ,
30 ADF4350_FREQ_REFIN,
31 ADF4350_FREQ_RESOLUTION,
32 ADF4350_PWRDOWN,
33};
34
35struct adf4350_state {
36 struct spi_device *spi;
37 struct gpio_desc *lock_detect_gpiod;
38 struct adf4350_platform_data *pdata;
39 struct clk *clk;
40 struct clk *clkout;
41 const char *clk_out_name;
42 struct clk_hw hw;
43 unsigned long clkin;
44 unsigned long chspc; /* Channel Spacing */
45 unsigned long fpfd; /* Phase Frequency Detector */
46 unsigned long min_out_freq;
47 unsigned r0_fract;
48 unsigned r0_int;
49 unsigned r1_mod;
50 unsigned r4_rf_div_sel;
51 unsigned long regs[6];
52 unsigned long regs_hw[6];
53 unsigned long long freq_req;
54 /*
55 * Lock to protect the state of the device from potential concurrent
56 * writes. The device is configured via a sequence of SPI writes,
57 * and this lock is meant to prevent the start of another sequence
58 * before another one has finished.
59 */
60 struct mutex lock;
61 /*
62 * DMA (thus cache coherency maintenance) may require that
63 * transfer buffers live in their own cache lines.
64 */
65 __be32 val __aligned(IIO_DMA_MINALIGN);
66};
67
68#define to_adf4350_state(_hw) container_of(_hw, struct adf4350_state, hw)
69
70static struct adf4350_platform_data default_pdata = {
71 .channel_spacing = 10000,
72 .r2_user_settings = ADF4350_REG2_PD_POLARITY_POS |
73 ADF4350_REG2_CHARGE_PUMP_CURR_uA(2500),
74 .r3_user_settings = ADF4350_REG3_12BIT_CLKDIV_MODE(0),
75 .r4_user_settings = ADF4350_REG4_OUTPUT_PWR(3) |
76 ADF4350_REG4_MUTE_TILL_LOCK_EN,
77};
78
79static int adf4350_sync_config(struct adf4350_state *st)
80{
81 int ret, i, doublebuf = 0;
82
83 for (i = ADF4350_REG5; i >= ADF4350_REG0; i--) {
84 if ((st->regs_hw[i] != st->regs[i]) ||
85 ((i == ADF4350_REG0) && doublebuf)) {
86 switch (i) {
87 case ADF4350_REG1:
88 case ADF4350_REG4:
89 doublebuf = 1;
90 break;
91 }
92
93 st->val = cpu_to_be32(st->regs[i] | i);
94 ret = spi_write(st->spi, &st->val, 4);
95 if (ret < 0)
96 return ret;
97 st->regs_hw[i] = st->regs[i];
98 dev_dbg(&st->spi->dev, "[%d] 0x%X\n",
99 i, (u32)st->regs[i] | i);
100 }
101 }
102 return 0;
103}
104
105static int adf4350_reg_access(struct iio_dev *indio_dev,
106 unsigned reg, unsigned writeval,
107 unsigned *readval)
108{
109 struct adf4350_state *st = iio_priv(indio_dev);
110 int ret;
111
112 if (reg > ADF4350_REG5)
113 return -EINVAL;
114
115 mutex_lock(&st->lock);
116 if (readval == NULL) {
117 st->regs[reg] = writeval & ~(BIT(0) | BIT(1) | BIT(2));
118 ret = adf4350_sync_config(st);
119 } else {
120 *readval = st->regs_hw[reg];
121 ret = 0;
122 }
123 mutex_unlock(&st->lock);
124
125 return ret;
126}
127
128static int adf4350_tune_r_cnt(struct adf4350_state *st, unsigned short r_cnt)
129{
130 struct adf4350_platform_data *pdata = st->pdata;
131
132 do {
133 r_cnt++;
134 st->fpfd = (st->clkin * (pdata->ref_doubler_en ? 2 : 1)) /
135 (r_cnt * (pdata->ref_div2_en ? 2 : 1));
136 } while (st->fpfd > ADF4350_MAX_FREQ_PFD);
137
138 return r_cnt;
139}
140
141static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
142{
143 struct adf4350_platform_data *pdata = st->pdata;
144 u64 tmp;
145 u32 div_gcd, prescaler, chspc;
146 u16 mdiv, r_cnt = 0;
147 u8 band_sel_div;
148
149 if (freq > ADF4350_MAX_OUT_FREQ || freq < st->min_out_freq)
150 return -EINVAL;
151
152 st->r4_rf_div_sel = 0;
153
154 /*
155 * !\TODO: The below computation is making sure we get a power of 2
156 * shift (st->r4_rf_div_sel) so that freq becomes higher or equal to
157 * ADF4350_MIN_VCO_FREQ. This might be simplified with fls()/fls_long()
158 * and friends.
159 */
160 while (freq < ADF4350_MIN_VCO_FREQ) {
161 freq <<= 1;
162 st->r4_rf_div_sel++;
163 }
164
165 if (freq > ADF4350_MAX_FREQ_45_PRESC) {
166 prescaler = ADF4350_REG1_PRESCALER;
167 mdiv = 75;
168 } else {
169 prescaler = 0;
170 mdiv = 23;
171 }
172
173 /*
174 * Allow a predefined reference division factor
175 * if not set, compute our own
176 */
177 if (pdata->ref_div_factor)
178 r_cnt = pdata->ref_div_factor - 1;
179
180 chspc = st->chspc;
181
182 do {
183 do {
184 do {
185 r_cnt = adf4350_tune_r_cnt(st, r_cnt);
186 st->r1_mod = st->fpfd / chspc;
187 if (r_cnt > ADF4350_MAX_R_CNT) {
188 /* try higher spacing values */
189 chspc++;
190 r_cnt = 0;
191 }
192 } while ((st->r1_mod > ADF4350_MAX_MODULUS) && r_cnt);
193 } while (r_cnt == 0);
194
195 tmp = freq * (u64)st->r1_mod + (st->fpfd >> 1);
196 do_div(tmp, st->fpfd); /* Div round closest (n + d/2)/d */
197 st->r0_fract = do_div(tmp, st->r1_mod);
198 st->r0_int = tmp;
199 } while (mdiv > st->r0_int);
200
201 band_sel_div = DIV_ROUND_UP(st->fpfd, ADF4350_MAX_BANDSEL_CLK);
202
203 if (st->r0_fract && st->r1_mod) {
204 div_gcd = gcd(st->r1_mod, st->r0_fract);
205 st->r1_mod /= div_gcd;
206 st->r0_fract /= div_gcd;
207 } else {
208 st->r0_fract = 0;
209 st->r1_mod = 1;
210 }
211
212 dev_dbg(&st->spi->dev, "VCO: %llu Hz, PFD %lu Hz\n"
213 "REF_DIV %d, R0_INT %d, R0_FRACT %d\n"
214 "R1_MOD %d, RF_DIV %d\nPRESCALER %s, BAND_SEL_DIV %d\n",
215 freq, st->fpfd, r_cnt, st->r0_int, st->r0_fract, st->r1_mod,
216 1 << st->r4_rf_div_sel, prescaler ? "8/9" : "4/5",
217 band_sel_div);
218
219 st->regs[ADF4350_REG0] = ADF4350_REG0_INT(st->r0_int) |
220 ADF4350_REG0_FRACT(st->r0_fract);
221
222 st->regs[ADF4350_REG1] = ADF4350_REG1_PHASE(1) |
223 ADF4350_REG1_MOD(st->r1_mod) |
224 prescaler;
225
226 st->regs[ADF4350_REG2] =
227 ADF4350_REG2_10BIT_R_CNT(r_cnt) |
228 ADF4350_REG2_DOUBLE_BUFF_EN |
229 (pdata->ref_doubler_en ? ADF4350_REG2_RMULT2_EN : 0) |
230 (pdata->ref_div2_en ? ADF4350_REG2_RDIV2_EN : 0) |
231 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
232 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
233 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
234 ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
235
236 st->regs[ADF4350_REG3] = pdata->r3_user_settings &
237 (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
238 ADF4350_REG3_12BIT_CLKDIV_MODE(0x3) |
239 ADF4350_REG3_12BIT_CSR_EN |
240 ADF4351_REG3_CHARGE_CANCELLATION_EN |
241 ADF4351_REG3_ANTI_BACKLASH_3ns_EN |
242 ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH);
243
244 st->regs[ADF4350_REG4] =
245 ADF4350_REG4_FEEDBACK_FUND |
246 ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) |
247 ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(band_sel_div) |
248 ADF4350_REG4_RF_OUT_EN |
249 (pdata->r4_user_settings &
250 (ADF4350_REG4_OUTPUT_PWR(0x3) |
251 ADF4350_REG4_AUX_OUTPUT_PWR(0x3) |
252 ADF4350_REG4_AUX_OUTPUT_EN |
253 ADF4350_REG4_AUX_OUTPUT_FUND |
254 ADF4350_REG4_MUTE_TILL_LOCK_EN));
255
256 st->regs[ADF4350_REG5] = ADF4350_REG5_LD_PIN_MODE_DIGITAL;
257 st->freq_req = freq;
258
259 return adf4350_sync_config(st);
260}
261
262static ssize_t adf4350_write(struct iio_dev *indio_dev,
263 uintptr_t private,
264 const struct iio_chan_spec *chan,
265 const char *buf, size_t len)
266{
267 struct adf4350_state *st = iio_priv(indio_dev);
268 unsigned long long readin;
269 unsigned long tmp;
270 int ret;
271
272 ret = kstrtoull(buf, 10, &readin);
273 if (ret)
274 return ret;
275
276 mutex_lock(&st->lock);
277 switch ((u32)private) {
278 case ADF4350_FREQ:
279 ret = adf4350_set_freq(st, readin);
280 break;
281 case ADF4350_FREQ_REFIN:
282 if (readin > ADF4350_MAX_FREQ_REFIN) {
283 ret = -EINVAL;
284 break;
285 }
286
287 if (st->clk) {
288 tmp = clk_round_rate(st->clk, readin);
289 if (tmp != readin) {
290 ret = -EINVAL;
291 break;
292 }
293 ret = clk_set_rate(st->clk, tmp);
294 if (ret < 0)
295 break;
296 }
297 st->clkin = readin;
298 ret = adf4350_set_freq(st, st->freq_req);
299 break;
300 case ADF4350_FREQ_RESOLUTION:
301 if (readin == 0)
302 ret = -EINVAL;
303 else
304 st->chspc = readin;
305 break;
306 case ADF4350_PWRDOWN:
307 if (readin)
308 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
309 else
310 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
311
312 adf4350_sync_config(st);
313 break;
314 default:
315 ret = -EINVAL;
316 }
317 mutex_unlock(&st->lock);
318
319 return ret ? ret : len;
320}
321
322static ssize_t adf4350_read(struct iio_dev *indio_dev,
323 uintptr_t private,
324 const struct iio_chan_spec *chan,
325 char *buf)
326{
327 struct adf4350_state *st = iio_priv(indio_dev);
328 unsigned long long val;
329 int ret = 0;
330
331 mutex_lock(&st->lock);
332 switch ((u32)private) {
333 case ADF4350_FREQ:
334 val = (u64)((st->r0_int * st->r1_mod) + st->r0_fract) *
335 (u64)st->fpfd;
336 do_div(val, st->r1_mod * (1 << st->r4_rf_div_sel));
337 /* PLL unlocked? return error */
338 if (st->lock_detect_gpiod)
339 if (!gpiod_get_value(st->lock_detect_gpiod)) {
340 dev_dbg(&st->spi->dev, "PLL un-locked\n");
341 ret = -EBUSY;
342 }
343 break;
344 case ADF4350_FREQ_REFIN:
345 if (st->clk)
346 st->clkin = clk_get_rate(st->clk);
347
348 val = st->clkin;
349 break;
350 case ADF4350_FREQ_RESOLUTION:
351 val = st->chspc;
352 break;
353 case ADF4350_PWRDOWN:
354 val = !!(st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
355 break;
356 default:
357 ret = -EINVAL;
358 val = 0;
359 }
360 mutex_unlock(&st->lock);
361
362 return ret < 0 ? ret : sprintf(buf, "%llu\n", val);
363}
364
365#define _ADF4350_EXT_INFO(_name, _ident) { \
366 .name = _name, \
367 .read = adf4350_read, \
368 .write = adf4350_write, \
369 .private = _ident, \
370 .shared = IIO_SEPARATE, \
371}
372
373static const struct iio_chan_spec_ext_info adf4350_ext_info[] = {
374 /* Ideally we use IIO_CHAN_INFO_FREQUENCY, but there are
375 * values > 2^32 in order to support the entire frequency range
376 * in Hz. Using scale is a bit ugly.
377 */
378 _ADF4350_EXT_INFO("frequency", ADF4350_FREQ),
379 _ADF4350_EXT_INFO("frequency_resolution", ADF4350_FREQ_RESOLUTION),
380 _ADF4350_EXT_INFO("refin_frequency", ADF4350_FREQ_REFIN),
381 _ADF4350_EXT_INFO("powerdown", ADF4350_PWRDOWN),
382 { }
383};
384
385static const struct iio_chan_spec adf4350_chan = {
386 .type = IIO_ALTVOLTAGE,
387 .indexed = 1,
388 .output = 1,
389 .ext_info = adf4350_ext_info,
390};
391
392static const struct iio_info adf4350_info = {
393 .debugfs_reg_access = &adf4350_reg_access,
394};
395
396static void adf4350_clk_del_provider(void *data)
397{
398 struct adf4350_state *st = data;
399
400 of_clk_del_provider(st->spi->dev.of_node);
401}
402
403static unsigned long adf4350_clk_recalc_rate(struct clk_hw *hw,
404 unsigned long parent_rate)
405{
406 struct adf4350_state *st = to_adf4350_state(hw);
407 unsigned long long tmp;
408
409 tmp = (u64)(st->r0_int * st->r1_mod + st->r0_fract) * st->fpfd;
410 do_div(tmp, st->r1_mod * (1 << st->r4_rf_div_sel));
411
412 return tmp;
413}
414
415static int adf4350_clk_set_rate(struct clk_hw *hw,
416 unsigned long rate,
417 unsigned long parent_rate)
418{
419 struct adf4350_state *st = to_adf4350_state(hw);
420
421 if (parent_rate == 0 || parent_rate > ADF4350_MAX_FREQ_REFIN)
422 return -EINVAL;
423
424 st->clkin = parent_rate;
425
426 return adf4350_set_freq(st, rate);
427}
428
429static int adf4350_clk_prepare(struct clk_hw *hw)
430{
431 struct adf4350_state *st = to_adf4350_state(hw);
432
433 st->regs[ADF4350_REG2] &= ~ADF4350_REG2_POWER_DOWN_EN;
434
435 return adf4350_sync_config(st);
436}
437
438static void adf4350_clk_unprepare(struct clk_hw *hw)
439{
440 struct adf4350_state *st = to_adf4350_state(hw);
441
442 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
443
444 adf4350_sync_config(st);
445}
446
447static int adf4350_clk_is_enabled(struct clk_hw *hw)
448{
449 struct adf4350_state *st = to_adf4350_state(hw);
450
451 return (st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN);
452}
453
454static const struct clk_ops adf4350_clk_ops = {
455 .recalc_rate = adf4350_clk_recalc_rate,
456 .set_rate = adf4350_clk_set_rate,
457 .prepare = adf4350_clk_prepare,
458 .unprepare = adf4350_clk_unprepare,
459 .is_enabled = adf4350_clk_is_enabled,
460};
461
462static int adf4350_clk_register(struct adf4350_state *st)
463{
464 struct spi_device *spi = st->spi;
465 struct clk_init_data init;
466 struct clk *clk;
467 const char *parent_name;
468 int ret;
469
470 if (!device_property_present(&spi->dev, "#clock-cells"))
471 return 0;
472
473 if (device_property_read_string(&spi->dev, "clock-output-names", &init.name)) {
474 init.name = devm_kasprintf(&spi->dev, GFP_KERNEL, "%s-clk",
475 fwnode_get_name(dev_fwnode(&spi->dev)));
476 if (!init.name)
477 return -ENOMEM;
478 }
479
480 parent_name = of_clk_get_parent_name(spi->dev.of_node, 0);
481 if (!parent_name)
482 return -EINVAL;
483
484 init.ops = &adf4350_clk_ops;
485 init.parent_names = &parent_name;
486 init.num_parents = 1;
487 init.flags = CLK_SET_RATE_PARENT;
488
489 st->hw.init = &init;
490 clk = devm_clk_register(&spi->dev, &st->hw);
491 if (IS_ERR(clk))
492 return PTR_ERR(clk);
493
494 ret = of_clk_add_provider(spi->dev.of_node, of_clk_src_simple_get, clk);
495 if (ret)
496 return ret;
497
498 st->clkout = clk;
499
500 return devm_add_action_or_reset(&spi->dev, adf4350_clk_del_provider, st);
501}
502
503static struct adf4350_platform_data *adf4350_parse_dt(struct device *dev)
504{
505 struct adf4350_platform_data *pdata;
506 unsigned int tmp;
507
508 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
509 if (!pdata)
510 return NULL;
511
512 snprintf(pdata->name, sizeof(pdata->name), "%pfw", dev_fwnode(dev));
513
514 tmp = 10000;
515 device_property_read_u32(dev, "adi,channel-spacing", &tmp);
516 pdata->channel_spacing = tmp;
517
518 tmp = 0;
519 device_property_read_u32(dev, "adi,power-up-frequency", &tmp);
520 pdata->power_up_frequency = tmp;
521
522 tmp = 0;
523 device_property_read_u32(dev, "adi,reference-div-factor", &tmp);
524 pdata->ref_div_factor = tmp;
525
526 pdata->ref_doubler_en = device_property_read_bool(dev, "adi,reference-doubler-enable");
527 pdata->ref_div2_en = device_property_read_bool(dev, "adi,reference-div2-enable");
528
529 /* r2_user_settings */
530 pdata->r2_user_settings = 0;
531 if (device_property_read_bool(dev, "adi,phase-detector-polarity-positive-enable"))
532 pdata->r2_user_settings |= ADF4350_REG2_PD_POLARITY_POS;
533 if (device_property_read_bool(dev, "adi,lock-detect-precision-6ns-enable"))
534 pdata->r2_user_settings |= ADF4350_REG2_LDP_6ns;
535 if (device_property_read_bool(dev, "adi,lock-detect-function-integer-n-enable"))
536 pdata->r2_user_settings |= ADF4350_REG2_LDF_INT_N;
537
538 tmp = 2500;
539 device_property_read_u32(dev, "adi,charge-pump-current", &tmp);
540 pdata->r2_user_settings |= ADF4350_REG2_CHARGE_PUMP_CURR_uA(tmp);
541
542 tmp = 0;
543 device_property_read_u32(dev, "adi,muxout-select", &tmp);
544 pdata->r2_user_settings |= ADF4350_REG2_MUXOUT(tmp);
545
546 if (device_property_read_bool(dev, "adi,low-spur-mode-enable"))
547 pdata->r2_user_settings |= ADF4350_REG2_NOISE_MODE(0x3);
548
549 /* r3_user_settings */
550
551 pdata->r3_user_settings = 0;
552 if (device_property_read_bool(dev, "adi,cycle-slip-reduction-enable"))
553 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CSR_EN;
554 if (device_property_read_bool(dev, "adi,charge-cancellation-enable"))
555 pdata->r3_user_settings |= ADF4351_REG3_CHARGE_CANCELLATION_EN;
556 if (device_property_read_bool(dev, "adi,anti-backlash-3ns-enable"))
557 pdata->r3_user_settings |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN;
558 if (device_property_read_bool(dev, "adi,band-select-clock-mode-high-enable"))
559 pdata->r3_user_settings |= ADF4351_REG3_BAND_SEL_CLOCK_MODE_HIGH;
560
561 tmp = 0;
562 device_property_read_u32(dev, "adi,12bit-clk-divider", &tmp);
563 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV(tmp);
564
565 tmp = 0;
566 device_property_read_u32(dev, "adi,clk-divider-mode", &tmp);
567 pdata->r3_user_settings |= ADF4350_REG3_12BIT_CLKDIV_MODE(tmp);
568
569 /* r4_user_settings */
570
571 pdata->r4_user_settings = 0;
572 if (device_property_read_bool(dev, "adi,aux-output-enable"))
573 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_EN;
574 if (device_property_read_bool(dev, "adi,aux-output-fundamental-enable"))
575 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_FUND;
576 if (device_property_read_bool(dev, "adi,mute-till-lock-enable"))
577 pdata->r4_user_settings |= ADF4350_REG4_MUTE_TILL_LOCK_EN;
578
579 tmp = 0;
580 device_property_read_u32(dev, "adi,output-power", &tmp);
581 pdata->r4_user_settings |= ADF4350_REG4_OUTPUT_PWR(tmp);
582
583 tmp = 0;
584 device_property_read_u32(dev, "adi,aux-output-power", &tmp);
585 pdata->r4_user_settings |= ADF4350_REG4_AUX_OUTPUT_PWR(tmp);
586
587 return pdata;
588}
589
590static void adf4350_power_down(void *data)
591{
592 struct iio_dev *indio_dev = data;
593 struct adf4350_state *st = iio_priv(indio_dev);
594
595 st->regs[ADF4350_REG2] |= ADF4350_REG2_POWER_DOWN_EN;
596 adf4350_sync_config(st);
597}
598
599static int adf4350_probe(struct spi_device *spi)
600{
601 struct adf4350_platform_data *pdata;
602 struct iio_dev *indio_dev;
603 struct adf4350_state *st;
604 struct clk *clk = NULL;
605 int ret;
606
607 if (dev_fwnode(&spi->dev)) {
608 pdata = adf4350_parse_dt(&spi->dev);
609 if (pdata == NULL)
610 return -EINVAL;
611 } else {
612 pdata = dev_get_platdata(&spi->dev);
613 }
614
615 if (!pdata) {
616 dev_warn(&spi->dev, "no platform data? using default\n");
617 pdata = &default_pdata;
618 }
619
620 if (!pdata->clkin) {
621 clk = devm_clk_get_enabled(&spi->dev, "clkin");
622 if (IS_ERR(clk))
623 return PTR_ERR(clk);
624 }
625
626 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
627 if (indio_dev == NULL)
628 return -ENOMEM;
629
630 st = iio_priv(indio_dev);
631
632 ret = devm_regulator_get_enable(&spi->dev, "vcc");
633 if (ret)
634 return ret;
635
636 st->spi = spi;
637 st->pdata = pdata;
638
639 indio_dev->name = (pdata->name[0] != 0) ? pdata->name :
640 spi_get_device_id(spi)->name;
641
642 indio_dev->info = &adf4350_info;
643 indio_dev->modes = INDIO_DIRECT_MODE;
644
645 mutex_init(&st->lock);
646
647 st->chspc = pdata->channel_spacing;
648 if (clk) {
649 st->clk = clk;
650 st->clkin = clk_get_rate(clk);
651 } else {
652 st->clkin = pdata->clkin;
653 }
654
655 st->min_out_freq = spi_get_device_id(spi)->driver_data == 4351 ?
656 ADF4351_MIN_OUT_FREQ : ADF4350_MIN_OUT_FREQ;
657
658 memset(st->regs_hw, 0xFF, sizeof(st->regs_hw));
659
660 st->lock_detect_gpiod = devm_gpiod_get_optional(&spi->dev, NULL,
661 GPIOD_IN);
662 if (IS_ERR(st->lock_detect_gpiod))
663 return PTR_ERR(st->lock_detect_gpiod);
664
665 if (pdata->power_up_frequency) {
666 ret = adf4350_set_freq(st, pdata->power_up_frequency);
667 if (ret)
668 return ret;
669 }
670
671 ret = adf4350_clk_register(st);
672 if (ret)
673 return ret;
674
675 if (!st->clkout) {
676 indio_dev->channels = &adf4350_chan;
677 indio_dev->num_channels = 1;
678 }
679
680 ret = devm_add_action_or_reset(&spi->dev, adf4350_power_down, indio_dev);
681 if (ret)
682 return ret;
683
684 return devm_iio_device_register(&spi->dev, indio_dev);
685}
686
687static const struct of_device_id adf4350_of_match[] = {
688 { .compatible = "adi,adf4350", },
689 { .compatible = "adi,adf4351", },
690 { }
691};
692MODULE_DEVICE_TABLE(of, adf4350_of_match);
693
694static const struct spi_device_id adf4350_id[] = {
695 {"adf4350", 4350},
696 {"adf4351", 4351},
697 { }
698};
699MODULE_DEVICE_TABLE(spi, adf4350_id);
700
701static struct spi_driver adf4350_driver = {
702 .driver = {
703 .name = "adf4350",
704 .of_match_table = adf4350_of_match,
705 },
706 .probe = adf4350_probe,
707 .id_table = adf4350_id,
708};
709module_spi_driver(adf4350_driver);
710
711MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
712MODULE_DESCRIPTION("Analog Devices ADF4350/ADF4351 PLL");
713MODULE_LICENSE("GPL v2");