tjh.dev
Linux kernel mirror (for testing)
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linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * GPIO driver for AMD 8111 south bridges
4 *
5 * Copyright (c) 2012 Dmitry Eremin-Solenikov
6 *
7 * Based on the AMD RNG driver:
8 * Copyright 2005 (c) MontaVista Software, Inc.
9 * with the majority of the code coming from:
10 *
11 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
12 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
13 *
14 * derived from
15 *
16 * Hardware driver for the AMD 768 Random Number Generator (RNG)
17 * (c) Copyright 2001 Red Hat Inc
18 *
19 * derived from
20 *
21 * Hardware driver for Intel i810 Random Number Generator (RNG)
22 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
23 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
24 */
25#include <linux/ioport.h>
26#include <linux/module.h>
27#include <linux/kernel.h>
28#include <linux/gpio/driver.h>
29#include <linux/pci.h>
30#include <linux/spinlock.h>
31
32#define PMBASE_OFFSET 0xb0
33#define PMBASE_SIZE 0x30
34
35#define AMD_REG_GPIO(i) (0x10 + (i))
36
37#define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
38#define AMD_GPIO_RTIN 0x20 /* Real Time in, ro */
39#define AMD_GPIO_DEBOUNCE 0x10 /* Debounce, rw */
40#define AMD_GPIO_MODE_MASK 0x0c /* Pin Mode Select, rw */
41#define AMD_GPIO_MODE_IN 0x00
42#define AMD_GPIO_MODE_OUT 0x04
43/* Enable alternative (e.g. clkout, IRQ, etc) function of the pin */
44#define AMD_GPIO_MODE_ALTFN 0x08 /* Or 0x09 */
45#define AMD_GPIO_X_MASK 0x03 /* In/Out specific, rw */
46#define AMD_GPIO_X_IN_ACTIVEHI 0x01 /* Active High */
47#define AMD_GPIO_X_IN_LATCH 0x02 /* Latched version is selected */
48#define AMD_GPIO_X_OUT_LOW 0x00
49#define AMD_GPIO_X_OUT_HI 0x01
50#define AMD_GPIO_X_OUT_CLK0 0x02
51#define AMD_GPIO_X_OUT_CLK1 0x03
52
53/*
54 * Data for PCI driver interface
55 *
56 * This data only exists for exporting the supported
57 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
58 * register a pci_driver, because someone else might one day
59 * want to register another driver on the same PCI id.
60 */
61static const struct pci_device_id pci_tbl[] = {
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS), 0 },
63 { 0, }, /* terminate list */
64};
65MODULE_DEVICE_TABLE(pci, pci_tbl);
66
67struct amd_gpio {
68 struct gpio_chip chip;
69 u32 pmbase;
70 void __iomem *pm;
71 struct pci_dev *pdev;
72 spinlock_t lock; /* guards hw registers and orig table */
73 u8 orig[32];
74};
75
76static int amd_gpio_request(struct gpio_chip *chip, unsigned offset)
77{
78 struct amd_gpio *agp = gpiochip_get_data(chip);
79
80 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) &
81 (AMD_GPIO_DEBOUNCE | AMD_GPIO_MODE_MASK | AMD_GPIO_X_MASK);
82
83 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]);
84
85 return 0;
86}
87
88static void amd_gpio_free(struct gpio_chip *chip, unsigned offset)
89{
90 struct amd_gpio *agp = gpiochip_get_data(chip);
91
92 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]);
93
94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset));
95}
96
97static int amd_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
98{
99 struct amd_gpio *agp = gpiochip_get_data(chip);
100 u8 temp;
101 unsigned long flags;
102
103 spin_lock_irqsave(&agp->lock, flags);
104 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
105 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
106 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
107 spin_unlock_irqrestore(&agp->lock, flags);
108
109 dev_dbg(&agp->pdev->dev, "Setting gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
110
111 return 0;
112}
113
114static int amd_gpio_get(struct gpio_chip *chip, unsigned offset)
115{
116 struct amd_gpio *agp = gpiochip_get_data(chip);
117 u8 temp;
118
119 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
120
121 dev_dbg(&agp->pdev->dev, "Getting gpio %d, reg=%02x\n", offset, temp);
122
123 return (temp & AMD_GPIO_RTIN) ? 1 : 0;
124}
125
126static int amd_gpio_dirout(struct gpio_chip *chip, unsigned offset, int value)
127{
128 struct amd_gpio *agp = gpiochip_get_data(chip);
129 u8 temp;
130 unsigned long flags;
131
132 spin_lock_irqsave(&agp->lock, flags);
133 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
134 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_OUT | (value ? AMD_GPIO_X_OUT_HI : AMD_GPIO_X_OUT_LOW);
135 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
136 spin_unlock_irqrestore(&agp->lock, flags);
137
138 dev_dbg(&agp->pdev->dev, "Dirout gpio %d, value %d, reg=%02x\n", offset, !!value, temp);
139
140 return 0;
141}
142
143static int amd_gpio_dirin(struct gpio_chip *chip, unsigned offset)
144{
145 struct amd_gpio *agp = gpiochip_get_data(chip);
146 u8 temp;
147 unsigned long flags;
148
149 spin_lock_irqsave(&agp->lock, flags);
150 temp = ioread8(agp->pm + AMD_REG_GPIO(offset));
151 temp = (temp & AMD_GPIO_DEBOUNCE) | AMD_GPIO_MODE_IN;
152 iowrite8(temp, agp->pm + AMD_REG_GPIO(offset));
153 spin_unlock_irqrestore(&agp->lock, flags);
154
155 dev_dbg(&agp->pdev->dev, "Dirin gpio %d, reg=%02x\n", offset, temp);
156
157 return 0;
158}
159
160static struct amd_gpio gp = {
161 .chip = {
162 .label = "AMD GPIO",
163 .owner = THIS_MODULE,
164 .base = -1,
165 .ngpio = 32,
166 .request = amd_gpio_request,
167 .free = amd_gpio_free,
168 .set = amd_gpio_set,
169 .get = amd_gpio_get,
170 .direction_output = amd_gpio_dirout,
171 .direction_input = amd_gpio_dirin,
172 },
173};
174
175static int __init amd_gpio_init(void)
176{
177 int err = -ENODEV;
178 struct pci_dev *pdev = NULL;
179 const struct pci_device_id *ent;
180
181 /* We look for our device - AMD South Bridge
182 * I don't know about a system with two such bridges,
183 * so we can assume that there is max. one device.
184 *
185 * We can't use plain pci_driver mechanism,
186 * as the device is really a multiple function device,
187 * main driver that binds to the pci_device is an smbus
188 * driver and have to find & bind to the device this way.
189 */
190 for_each_pci_dev(pdev) {
191 ent = pci_match_id(pci_tbl, pdev);
192 if (ent)
193 goto found;
194 }
195 /* Device not found. */
196 goto out;
197
198found:
199 err = pci_read_config_dword(pdev, 0x58, &gp.pmbase);
200 if (err) {
201 err = pcibios_err_to_errno(err);
202 goto out;
203 }
204 err = -EIO;
205 gp.pmbase &= 0x0000FF00;
206 if (gp.pmbase == 0)
207 goto out;
208 if (!devm_request_region(&pdev->dev, gp.pmbase + PMBASE_OFFSET,
209 PMBASE_SIZE, "AMD GPIO")) {
210 dev_err(&pdev->dev, "AMD GPIO region 0x%x already in use!\n",
211 gp.pmbase + PMBASE_OFFSET);
212 err = -EBUSY;
213 goto out;
214 }
215 gp.pm = ioport_map(gp.pmbase + PMBASE_OFFSET, PMBASE_SIZE);
216 if (!gp.pm) {
217 dev_err(&pdev->dev, "Couldn't map io port into io memory\n");
218 err = -ENOMEM;
219 goto out;
220 }
221 gp.pdev = pdev;
222 gp.chip.parent = &pdev->dev;
223
224 spin_lock_init(&gp.lock);
225
226 dev_info(&pdev->dev, "AMD-8111 GPIO detected\n");
227 err = gpiochip_add_data(&gp.chip, &gp);
228 if (err) {
229 dev_err(&pdev->dev, "GPIO registering failed (%d)\n", err);
230 ioport_unmap(gp.pm);
231 goto out;
232 }
233 return 0;
234
235out:
236 pci_dev_put(pdev);
237 return err;
238}
239
240static void __exit amd_gpio_exit(void)
241{
242 gpiochip_remove(&gp.chip);
243 ioport_unmap(gp.pm);
244 pci_dev_put(gp.pdev);
245}
246
247module_init(amd_gpio_init);
248module_exit(amd_gpio_exit);
249
250MODULE_AUTHOR("The Linux Kernel team");
251MODULE_DESCRIPTION("GPIO driver for AMD chipsets");
252MODULE_LICENSE("GPL");