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1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Atmel Timer Counter Block
8
9maintainers:
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11
12description: |
13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
14 timer has three channels with two counters each.
15
16properties:
17 compatible:
18 oneOf:
19 - items:
20 - enum:
21 - atmel,at91rm9200-tcb
22 - atmel,at91sam9x5-tcb
23 - atmel,sama5d2-tcb
24 - const: simple-mfd
25 - const: syscon
26 - items:
27 - const: microchip,sam9x7-tcb
28 - const: atmel,sama5d2-tcb
29 - const: simple-mfd
30 - const: syscon
31
32 reg:
33 maxItems: 1
34
35 interrupts:
36 description:
37 List of interrupts. One interrupt per TCB channel if available or one
38 interrupt for the TC block
39 minItems: 1
40 maxItems: 3
41
42 clock-names:
43 description:
44 List of clock names. Always includes t0_clk and slow clk. Also includes
45 t1_clk and t2_clk if a clock per channel is available.
46 minItems: 2
47 maxItems: 4
48
49 clocks:
50 minItems: 2
51 maxItems: 4
52
53 '#address-cells':
54 const: 1
55
56 '#size-cells':
57 const: 0
58
59patternProperties:
60 '^timer@[0-2]$':
61 description: The timer block channels that are used as timers or counters.
62 type: object
63 additionalProperties: false
64 properties:
65 compatible:
66 items:
67 - enum:
68 - atmel,tcb-timer
69 - atmel,tcb-pwm
70 - microchip,tcb-capture
71 reg:
72 description:
73 List of channels to use for this particular timer. In Microchip TCB capture
74 mode channels are registered as a counter devices, for the qdec mode TCB0's
75 channel <0> and <1> are required.
76
77 minItems: 1
78 maxItems: 3
79 required:
80 - compatible
81 - reg
82
83 '^pwm@[0-2]$':
84 description: The timer block channels that are used as PWMs.
85 $ref: /schemas/pwm/pwm.yaml#
86 type: object
87 properties:
88 compatible:
89 const: atmel,tcb-pwm
90 reg:
91 description:
92 TCB channel to use for this PWM.
93 enum: [ 0, 1, 2 ]
94
95 '#pwm-cells':
96 description:
97 The only third cell flag supported by this binding is
98 PWM_POLARITY_INVERTED.
99 const: 3
100
101 required:
102 - compatible
103 - reg
104 - '#pwm-cells'
105
106 additionalProperties: false
107
108allOf:
109 - if:
110 properties:
111 compatible:
112 contains:
113 const: atmel,sama5d2-tcb
114 then:
115 properties:
116 clocks:
117 minItems: 3
118 maxItems: 3
119 clock-names:
120 items:
121 - const: t0_clk
122 - const: gclk
123 - const: slow_clk
124 else:
125 properties:
126 clocks:
127 minItems: 2
128 maxItems: 4
129 clock-names:
130 oneOf:
131 - items:
132 - const: t0_clk
133 - const: slow_clk
134 - items:
135 - const: t0_clk
136 - const: t1_clk
137 - const: t2_clk
138 - const: slow_clk
139
140required:
141 - compatible
142 - reg
143 - interrupts
144 - clocks
145 - clock-names
146 - '#address-cells'
147 - '#size-cells'
148
149additionalProperties: false
150
151examples:
152 - |
153 /* One interrupt per TC block: */
154 tcb0: timer@fff7c000 {
155 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0xfff7c000 0x100>;
159 interrupts = <18 4>;
160 clocks = <&tcb0_clk>, <&clk32k>;
161 clock-names = "t0_clk", "slow_clk";
162
163 timer@0 {
164 compatible = "atmel,tcb-timer";
165 reg = <0>, <1>;
166 };
167
168 timer@2 {
169 compatible = "atmel,tcb-timer";
170 reg = <2>;
171 };
172 };
173
174 /* One interrupt per TC channel in a TC block: */
175 tcb1: timer@fffdc000 {
176 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
177 #address-cells = <1>;
178 #size-cells = <0>;
179 reg = <0xfffdc000 0x100>;
180 interrupts = <26 4>, <27 4>, <28 4>;
181 clocks = <&tcb1_clk>, <&clk32k>;
182 clock-names = "t0_clk", "slow_clk";
183
184 timer@0 {
185 compatible = "atmel,tcb-timer";
186 reg = <0>;
187 };
188
189 timer@1 {
190 compatible = "atmel,tcb-timer";
191 reg = <1>;
192 };
193
194 pwm@2 {
195 compatible = "atmel,tcb-pwm";
196 reg = <2>;
197 #pwm-cells = <3>;
198 };
199 };
200 /* TCB0 Capture with QDEC: */
201 timer@f800c000 {
202 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
203 #address-cells = <1>;
204 #size-cells = <0>;
205 reg = <0xfff7c000 0x100>;
206 interrupts = <18 4>;
207 clocks = <&tcb0_clk>, <&clk32k>;
208 clock-names = "t0_clk", "slow_clk";
209
210 timer@0 {
211 compatible = "microchip,tcb-capture";
212 reg = <0>, <1>;
213 };
214
215 timer@2 {
216 compatible = "atmel,tcb-timer";
217 reg = <2>;
218 };
219 };