tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX Messaging Unit (MU)
8
9maintainers:
10 - Dong Aisheng <aisheng.dong@nxp.com>
11
12description: |
13 The Messaging Unit module enables two processors within the SoC to
14 communicate and coordinate by passing messages (e.g. data, status
15 and control) through the MU interface. The MU also provides the ability
16 for one processor to signal the other processor using interrupts.
17
18 Because the MU manages the messaging between processors, the MU uses
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
21 other. The MU accomplishes synchronization using two sets of matching
22 registers (Processor A-facing, Processor B-facing).
23
24properties:
25 compatible:
26 oneOf:
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8ulp-mu
30 - const: fsl,imx8-mu-scu
31 - const: fsl,imx8-mu-seco
32 - const: fsl,imx8ulp-mu-s4
33 - const: fsl,imx93-mu-s4
34 - const: fsl,imx95-mu
35 - const: fsl,imx95-mu-ele
36 - const: fsl,imx95-mu-v2x
37 - items:
38 - const: fsl,imx93-mu
39 - const: fsl,imx8ulp-mu
40 - items:
41 - enum:
42 - fsl,imx7s-mu
43 - fsl,imx8mq-mu
44 - fsl,imx8mm-mu
45 - fsl,imx8mn-mu
46 - fsl,imx8mp-mu
47 - fsl,imx8qm-mu
48 - fsl,imx8qxp-mu
49 - const: fsl,imx6sx-mu
50 - description: To communicate with i.MX8 SCU with fast IPC
51 items:
52 - const: fsl,imx8-mu-scu
53 - enum:
54 - fsl,imx8qm-mu
55 - fsl,imx8qxp-mu
56 - const: fsl,imx6sx-mu
57 - items:
58 - enum:
59 - fsl,imx94-mu
60 - const: fsl,imx95-mu
61
62 reg:
63 maxItems: 1
64
65 interrupts:
66 minItems: 1
67 maxItems: 2
68
69 interrupt-names:
70 minItems: 1
71 items:
72 - const: tx
73 - const: rx
74
75 "#mbox-cells":
76 description: |
77 <&phandle type channel>
78 phandle : Label name of controller
79 type : Channel type
80 channel : Channel number
81
82 This MU support 6 type of unidirectional channels, each type
83 has 4 channels except RST channel which only has 1 channel.
84 A total of 21 channels. Following types are
85 supported:
86 0 - TX channel with 32bit transmit register and IRQ transmit
87 acknowledgment support.
88 1 - RX channel with 32bit receive register and IRQ support
89 2 - TX doorbell channel. Without own register and no ACK support.
90 3 - RX doorbell channel.
91 4 - RST channel
92 5 - Tx doorbell channel. With S/W ACK from the other side.
93 const: 2
94
95 clocks:
96 maxItems: 1
97
98 fsl,mu-side-b:
99 description: boolean, if present, means it is for side B MU.
100 type: boolean
101
102 power-domains:
103 maxItems: 1
104
105 ranges: true
106
107 '#address-cells':
108 const: 1
109
110 '#size-cells':
111 const: 1
112
113patternProperties:
114 "^sram@[a-f0-9]+":
115 $ref: /schemas/sram/sram.yaml#
116 unevaluatedProperties: false
117
118required:
119 - compatible
120 - reg
121 - interrupts
122 - "#mbox-cells"
123
124allOf:
125 - if:
126 properties:
127 compatible:
128 enum:
129 - fsl,imx93-mu-s4
130 then:
131 properties:
132 interrupt-names:
133 minItems: 2
134 interrupts:
135 minItems: 2
136
137 else:
138 properties:
139 interrupts:
140 maxItems: 1
141 not:
142 required:
143 - interrupt-names
144
145 - if:
146 not:
147 properties:
148 compatible:
149 contains:
150 const: fsl,imx95-mu
151 then:
152 patternProperties:
153 "^sram@[a-f0-9]+": false
154
155additionalProperties: false
156
157examples:
158 - |
159 #include <dt-bindings/interrupt-controller/arm-gic.h>
160
161 mailbox@5d1b0000 {
162 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
163 reg = <0x5d1b0000 0x10000>;
164 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
165 #mbox-cells = <2>;
166 };
167
168 - |
169 #include <dt-bindings/interrupt-controller/arm-gic.h>
170
171 mailbox@445b0000 {
172 compatible = "fsl,imx95-mu";
173 reg = <0x445b0000 0x10000>;
174 ranges;
175 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
176 #address-cells = <1>;
177 #size-cells = <1>;
178 #mbox-cells = <2>;
179
180 sram@445b1000 {
181 compatible = "mmio-sram";
182 reg = <0x445b1000 0x400>;
183 ranges = <0x0 0x445b1000 0x400>;
184 #address-cells = <1>;
185 #size-cells = <1>;
186
187 scmi-sram-section@0 {
188 compatible = "arm,scmi-shmem";
189 reg = <0x0 0x80>;
190 };
191
192 scmi-sram-section@80 {
193 compatible = "arm,scmi-shmem";
194 reg = <0x80 0x80>;
195 };
196 };
197 };