tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware DMA Controller
8
9maintainers:
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
12
13allOf:
14 - $ref: dma-controller.yaml#
15
16properties:
17 compatible:
18 oneOf:
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
22 - renesas,r9a06g032-dma
23 - const: renesas,rzn1-dma
24
25 "#dma-cells":
26 minimum: 3
27 maximum: 4
28 description: |
29 First cell is a phandle pointing to the DMA controller. Second one is
30 the DMA request line number. Third cell is the memory master identifier
31 for transfers on dynamically allocated channel. Fourth cell is the
32 peripheral master identifier for transfers on an allocated channel. Fifth
33 cell is an optional mask of the DMA channels permitted to be allocated
34 for the corresponding client device.
35
36 reg:
37 maxItems: 1
38
39 interrupts:
40 maxItems: 1
41
42 clocks:
43 maxItems: 1
44
45 clock-names:
46 description: AHB interface reference clock.
47 const: hclk
48
49 dma-channels:
50 description: |
51 Number of DMA channels supported by the controller. In case if
52 not specified the driver will try to auto-detect this and
53 the rest of the optional parameters.
54 minimum: 1
55 maximum: 8
56
57 dma-requests:
58 minimum: 1
59 maximum: 16
60
61 dma-masters:
62 $ref: /schemas/types.yaml#/definitions/uint32
63 description: |
64 Number of DMA masters supported by the controller. In case if
65 not specified the driver will try to auto-detect this and
66 the rest of the optional parameters.
67 minimum: 1
68 maximum: 4
69
70 chan_allocation_order:
71 $ref: /schemas/types.yaml#/definitions/uint32
72 description: |
73 DMA channels allocation order specifier. Zero means ascending order
74 (first free allocated), while one - descending (last free allocated).
75 default: 0
76 enum: [0, 1]
77
78 chan_priority:
79 $ref: /schemas/types.yaml#/definitions/uint32
80 description: |
81 DMA channels priority order. Zero means ascending channels priority
82 so the very first channel has the highest priority. While 1 means
83 descending priority (the last channel has the highest priority).
84 default: 0
85 enum: [0, 1]
86
87 block_size:
88 $ref: /schemas/types.yaml#/definitions/uint32
89 description: Maximum block size supported by the DMA controller.
90 enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
91
92 data-width:
93 $ref: /schemas/types.yaml#/definitions/uint32-array
94 description: Data bus width per each DMA master in bytes.
95 minItems: 1
96 maxItems: 4
97 items:
98 enum: [4, 8, 16, 32]
99
100 data_width:
101 $ref: /schemas/types.yaml#/definitions/uint32-array
102 deprecated: true
103 description: |
104 Data bus width per each DMA master in (2^n * 8) bits. This property is
105 deprecated. It' usage is discouraged in favor of data-width one. Moreover
106 the property incorrectly permits to define data-bus width of 8 and 16
107 bits, which is impossible in accordance with DW DMAC IP-core data book.
108 minItems: 1
109 maxItems: 4
110 items:
111 enum:
112 - 0 # 8 bits
113 - 1 # 16 bits
114 - 2 # 32 bits
115 - 3 # 64 bits
116 - 4 # 128 bits
117 - 5 # 256 bits
118 default: 0
119
120 multi-block:
121 $ref: /schemas/types.yaml#/definitions/uint32-array
122 description: |
123 LLP-based multi-block transfer supported by hardware per
124 each DMA channel.
125 minItems: 1
126 maxItems: 8
127 items:
128 enum: [0, 1]
129 default: 1
130
131 snps,max-burst-len:
132 $ref: /schemas/types.yaml#/definitions/uint32-array
133 description: |
134 Maximum length of the burst transactions supported by the controller.
135 This property defines the upper limit of the run-time burst setting
136 (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
137 will be from 1 to max-burst-len words. It's an array property with one
138 cell per channel in the units determined by the value set in the
139 CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
140 minItems: 1
141 maxItems: 8
142 items:
143 enum: [4, 8, 16, 32, 64, 128, 256]
144 default: 256
145
146 snps,dma-protection-control:
147 $ref: /schemas/types.yaml#/definitions/uint32
148 description: |
149 Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
150 indicates the following features: bit 0 - privileged mode,
151 bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
152 default: 0
153 minimum: 0
154 maximum: 7
155
156unevaluatedProperties: false
157
158required:
159 - compatible
160 - "#dma-cells"
161 - reg
162 - interrupts
163
164examples:
165 - |
166 dma-controller@fc000000 {
167 compatible = "snps,dma-spear1340";
168 reg = <0xfc000000 0x1000>;
169 interrupt-parent = <&vic1>;
170 interrupts = <12>;
171
172 dma-channels = <8>;
173 dma-requests = <16>;
174 dma-masters = <4>;
175 #dma-cells = <3>;
176
177 chan_allocation_order = <1>;
178 chan_priority = <1>;
179 block_size = <0xfff>;
180 data-width = <8 8>;
181 multi-block = <0 0 0 0 0 0 0 0>;
182 snps,max-burst-len = <16 16 4 4 4 4 4 4>;
183 };
184...